llvm::HexagonInstrInfo Member List

This is the complete list of members for llvm::HexagonInstrInfo, including all inherited members.

AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const	llvm::HexagonInstrInfo	virtual
analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const	llvm::HexagonInstrInfo	virtual
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const	llvm::HexagonInstrInfo	virtual
CreateTargetScheduleState(const TargetMachine *TM, const ScheduleDAG *DAG) const	llvm::HexagonInstrInfo	virtual
createVR(MachineFunction *MF, MVT VT) const	llvm::HexagonInstrInfo
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const	llvm::HexagonInstrInfo	virtual
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const	llvm::HexagonInstrInfo	virtual
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const	llvm::HexagonInstrInfo	inlinevirtual
getAddrMode(const MachineInstr *MI) const	llvm::HexagonInstrInfo
getCExtOpNum(const MachineInstr *MI) const	llvm::HexagonInstrInfo
GetDotNewOp(const MachineInstr *MI) const	llvm::HexagonInstrInfo
getDotNewPredJumpOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const	llvm::HexagonInstrInfo
GetDotNewPredOp(MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const	llvm::HexagonInstrInfo
GetDotOldOp(const int opc) const	llvm::HexagonInstrInfo
getInvertedPredicatedOpcode(const int Opc) const	llvm::HexagonInstrInfo
getMaxValue(const MachineInstr *MI) const	llvm::HexagonInstrInfo
getMinValue(const MachineInstr *MI) const	llvm::HexagonInstrInfo
getNonExtOpcode(const MachineInstr *MI) const	llvm::HexagonInstrInfo
getRegisterInfo() const	llvm::HexagonInstrInfo	inlinevirtual
HexagonInstrInfo(HexagonSubtarget &ST)	llvm::HexagonInstrInfo	explicit
immediateExtend(MachineInstr *MI) const	llvm::HexagonInstrInfo
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const	llvm::HexagonInstrInfo	virtual
isBranch(const MachineInstr *MI) const	llvm::HexagonInstrInfo	virtual
isConditionalALU32(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isConditionalLoad(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isConditionalStore(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isConditionalTransfer(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isConstExtended(MachineInstr *MI) const	llvm::HexagonInstrInfo
isDeallocRet(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isDotNewInst(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isExtendable(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isExtended(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::HexagonInstrInfo	virtual
isMemOp(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isNewValue(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isNewValueInst(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isNewValueJump(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isNewValueJumpCandidate(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isNewValueStore(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isNewValueStore(unsigned Opcode) const	llvm::HexagonInstrInfo
isOperandExtended(const MachineInstr *MI, unsigned short OperandNum) const	llvm::HexagonInstrInfo
isPostIncrement(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isPredicable(MachineInstr *MI) const	llvm::HexagonInstrInfo	virtual
isPredicated(const MachineInstr *MI) const	llvm::HexagonInstrInfo	virtual
isPredicated(unsigned Opcode) const	llvm::HexagonInstrInfo	virtual
isPredicatedNew(const MachineInstr *MI) const	llvm::HexagonInstrInfo	virtual
isPredicatedNew(unsigned Opcode) const	llvm::HexagonInstrInfo	virtual
isPredicatedTrue(const MachineInstr *MI) const	llvm::HexagonInstrInfo	virtual
isPredicatedTrue(unsigned Opcode) const	llvm::HexagonInstrInfo	virtual
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const	llvm::HexagonInstrInfo	virtual
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const	llvm::HexagonInstrInfo	virtual
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, const BranchProbability &Probability) const	llvm::HexagonInstrInfo	virtual
isS12_Immediate(const int value) const	llvm::HexagonInstrInfo
isS4_0Immediate(const int value) const	llvm::HexagonInstrInfo
isS4_1Immediate(const int value) const	llvm::HexagonInstrInfo
isS4_2Immediate(const int value) const	llvm::HexagonInstrInfo
isS4_3Immediate(const int value) const	llvm::HexagonInstrInfo
isS6_Immediate(const int value) const	llvm::HexagonInstrInfo
isS8_Immediate(const int value) const	llvm::HexagonInstrInfo
isSaveCalleeSavedRegsCall(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const	llvm::HexagonInstrInfo	virtual
isSpillPredRegOp(const MachineInstr *MI) const	llvm::HexagonInstrInfo
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::HexagonInstrInfo	virtual
isU6_0Immediate(const int value) const	llvm::HexagonInstrInfo
isU6_1Immediate(const int value) const	llvm::HexagonInstrInfo
isU6_2Immediate(const int value) const	llvm::HexagonInstrInfo
isU6_3Immediate(const int value) const	llvm::HexagonInstrInfo
isU6_Immediate(const int value) const	llvm::HexagonInstrInfo
isValidAutoIncImm(const EVT VT, const int Offset) const	llvm::HexagonInstrInfo
isValidOffset(const int Opcode, const int Offset) const	llvm::HexagonInstrInfo
loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::HexagonInstrInfo	virtual
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::HexagonInstrInfo	virtual
mayBeNewStore(const MachineInstr *MI) const	llvm::HexagonInstrInfo
NonExtEquivalentExists(const MachineInstr *MI) const	llvm::HexagonInstrInfo
PredicateInstruction(MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Cond) const	llvm::HexagonInstrInfo	virtual
PredOpcodeHasJMP_c(Opcode_t Opcode) const	llvm::HexagonInstrInfo
PredOpcodeHasNot(Opcode_t Opcode) const	llvm::HexagonInstrInfo
RemoveBranch(MachineBasicBlock &MBB) const	llvm::HexagonInstrInfo	virtual
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const	llvm::HexagonInstrInfo	virtual
storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::HexagonInstrInfo	virtual
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::HexagonInstrInfo	virtual
SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const	llvm::HexagonInstrInfo	virtual