llvm::VirtRegMap Member List

This is the complete list of members for llvm::VirtRegMap, including all inherited members.

assignPassManager(PMStack &PMS, PassManagerType T)	llvm::FunctionPass	virtual
assignVirt2Phys(unsigned virtReg, unsigned physReg)	llvm::VirtRegMap	inline
assignVirt2StackSlot(unsigned virtReg)	llvm::VirtRegMap
assignVirt2StackSlot(unsigned virtReg, int frameIndex)	llvm::VirtRegMap
clearAllVirt()	llvm::VirtRegMap	inline
clearVirt(unsigned virtReg)	llvm::VirtRegMap	inline
createPass(AnalysisID ID)	llvm::Pass	static
doFinalization(Module &)	llvm::Pass	inlinevirtual
doInitialization(Module &)	llvm::Pass	inlinevirtual
dump() const	llvm::VirtRegMap
dumpPassStructure(unsigned Offset=0)	llvm::Pass	virtual
FunctionPass(char &pid)	llvm::FunctionPass	inlineexplicit
getAdjustedAnalysisPointer(AnalysisID ID)	llvm::Pass	virtual
getAnalysis() const	llvm::Pass
getAnalysis(Function &F)	llvm::Pass
getAnalysisID(AnalysisID PI) const	llvm::Pass
getAnalysisID(AnalysisID PI, Function &F)	llvm::Pass
getAnalysisIfAvailable() const	llvm::Pass
getAnalysisUsage(AnalysisUsage &AU) const	llvm::VirtRegMap	inlinevirtual
getAsImmutablePass()	llvm::Pass	virtual
getAsPMDataManager()	llvm::Pass	virtual
getMachineFunction() const	llvm::VirtRegMap	inline
getOriginal(unsigned VirtReg) const	llvm::VirtRegMap	inline
getPassID() const	llvm::Pass	inline
getPassKind() const	llvm::Pass	inline
getPassName() const	llvm::Pass	virtual
getPhys(unsigned virtReg) const	llvm::VirtRegMap	inline
getPotentialPassManagerType() const	llvm::FunctionPass	virtual
getPreSplitReg(unsigned virtReg) const	llvm::VirtRegMap	inline
getRegInfo() const	llvm::VirtRegMap	inline
getResolver() const	llvm::Pass	inline
getStackSlot(unsigned virtReg) const	llvm::VirtRegMap	inline
getTargetRegInfo() const	llvm::VirtRegMap	inline
grow()	llvm::VirtRegMap
hasKnownPreference(unsigned VirtReg)	llvm::VirtRegMap
hasPhys(unsigned virtReg) const	llvm::VirtRegMap	inline
hasPreferredPhys(unsigned VirtReg)	llvm::VirtRegMap
ID	llvm::VirtRegMap	static
isAssignedReg(unsigned virtReg) const	llvm::VirtRegMap	inline
lookupPassInfo(const void *TI)	llvm::Pass	static
lookupPassInfo(StringRef Arg)	llvm::Pass	static
MachineFunctionPass(char &ID)	llvm::MachineFunctionPass	inlineexplicitprotected
MAX_STACK_SLOT enum value	llvm::VirtRegMap
mustPreserveAnalysisID(char &AID) const	llvm::Pass
NO_PHYS_REG enum value	llvm::VirtRegMap
NO_STACK_SLOT enum value	llvm::VirtRegMap
Pass(PassKind K, char &pid)	llvm::Pass	inlineexplicit
preparePassManager(PMStack &)	llvm::Pass	virtual
print(raw_ostream &OS, const Module *M=0) const	llvm::VirtRegMap	virtual
releaseMemory()	llvm::Pass	virtual
runOnMachineFunction(MachineFunction &MF)	llvm::VirtRegMap	virtual
setIsSplitFromReg(unsigned virtReg, unsigned SReg)	llvm::VirtRegMap	inline
setResolver(AnalysisResolver *AR)	llvm::Pass
verifyAnalysis() const	llvm::Pass	virtual
VirtRegMap()	llvm::VirtRegMap	inline
~Pass()	llvm::Pass	virtual