llvm::X86InstrInfo Member List

This is the complete list of members for llvm::X86InstrInfo, including all inherited members.

AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const	llvm::X86InstrInfo	virtual
analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const	llvm::X86InstrInfo	virtual
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const	llvm::X86InstrInfo	virtual
breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const	llvm::X86InstrInfo
canFoldMemoryOperand(const MachineInstr *, const SmallVectorImpl< unsigned > &) const	llvm::X86InstrInfo	virtual
canInsertSelect(const MachineBasicBlock &, const SmallVectorImpl< MachineOperand > &Cond, unsigned, unsigned, int &, int &, int &) const	llvm::X86InstrInfo	virtual
classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp) const	llvm::X86InstrInfo
commuteInstruction(MachineInstr *MI, bool NewMI) const	llvm::X86InstrInfo	virtual
convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const	llvm::X86InstrInfo	virtual
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const	llvm::X86InstrInfo	virtual
expandPostRAPseudo(MachineBasicBlock::iterator MI) const	llvm::X86InstrInfo	virtual
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const	llvm::X86InstrInfo	virtual
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const	llvm::X86InstrInfo	virtual
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, unsigned OpNum, const SmallVectorImpl< MachineOperand > &MOs, unsigned Size, unsigned Alignment) const	llvm::X86InstrInfo
getExecutionDomain(const MachineInstr *MI) const	llvm::X86InstrInfo
getGlobalBaseReg(MachineFunction *MF) const	llvm::X86InstrInfo
getNoopForMachoTarget(MCInst &NopInst) const	llvm::X86InstrInfo	virtual
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=0) const	llvm::X86InstrInfo	virtual
getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const	llvm::X86InstrInfo
getRegisterInfo() const	llvm::X86InstrInfo	inlinevirtual
getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const	llvm::X86InstrInfo
hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const	llvm::X86InstrInfo
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const	llvm::X86InstrInfo	virtual
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, const SmallVectorImpl< MachineOperand > &Cond, unsigned TrueReg, unsigned FalseReg) const	llvm::X86InstrInfo	virtual
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const	llvm::X86InstrInfo	virtual
isHighLatencyDef(int opc) const	llvm::X86InstrInfo
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::X86InstrInfo
isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const	llvm::X86InstrInfo
isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const	llvm::X86InstrInfo
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const	llvm::X86InstrInfo
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::X86InstrInfo
isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const	llvm::X86InstrInfo
isUnpredicatedTerminator(const MachineInstr *MI) const	llvm::X86InstrInfo	virtual
isX86_64ExtendedReg(const MachineOperand &MO)	llvm::X86InstrInfo	inlinestatic
loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::X86InstrInfo	virtual
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::X86InstrInfo	virtual
optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const	llvm::X86InstrInfo	virtual
optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const	llvm::X86InstrInfo	virtual
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const	llvm::X86InstrInfo
RemoveBranch(MachineBasicBlock &MBB) const	llvm::X86InstrInfo	virtual
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const	llvm::X86InstrInfo	virtual
setExecutionDomain(MachineInstr *MI, unsigned Domain) const	llvm::X86InstrInfo
shouldScheduleAdjacent(MachineInstr *First, MachineInstr *Second) const LLVM_OVERRIDE	llvm::X86InstrInfo	virtual
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const	llvm::X86InstrInfo	virtual
storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::X86InstrInfo	virtual
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::X86InstrInfo	virtual
unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::X86InstrInfo	virtual
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const	llvm::X86InstrInfo	virtual
X86InstrInfo(X86TargetMachine &tm)	llvm::X86InstrInfo	explicit