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ARMBaseInfo.h
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1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the ARM target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef ARMBASEINFO_H
18 #define ARMBASEINFO_H
19 
20 #include "ARMMCTargetDesc.h"
22 
23 namespace llvm {
24 
25 // Enums corresponding to ARM condition codes
26 namespace ARMCC {
27  // The CondCodes constants map directly to the 4-bit encoding of the
28  // condition field for predicated instructions.
29  enum CondCodes { // Meaning (integer) Meaning (floating-point)
30  EQ, // Equal Equal
31  NE, // Not equal Not equal, or unordered
32  HS, // Carry set >, ==, or unordered
33  LO, // Carry clear Less than
34  MI, // Minus, negative Less than
35  PL, // Plus, positive or zero >, ==, or unordered
36  VS, // Overflow Unordered
37  VC, // No overflow Not unordered
38  HI, // Unsigned higher Greater than, or unordered
39  LS, // Unsigned lower or same Less than or equal
40  GE, // Greater than or equal Greater than or equal
41  LT, // Less than Less than, or unordered
42  GT, // Greater than Greater than
43  LE, // Less than or equal <, ==, or unordered
44  AL // Always (unconditional) Always (unconditional)
45  };
46 
48  switch (CC) {
49  default: llvm_unreachable("Unknown condition code");
50  case EQ: return NE;
51  case NE: return EQ;
52  case HS: return LO;
53  case LO: return HS;
54  case MI: return PL;
55  case PL: return MI;
56  case VS: return VC;
57  case VC: return VS;
58  case HI: return LS;
59  case LS: return HI;
60  case GE: return LT;
61  case LT: return GE;
62  case GT: return LE;
63  case LE: return GT;
64  }
65  }
66 } // namespace ARMCC
67 
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
69  switch (CC) {
70  case ARMCC::EQ: return "eq";
71  case ARMCC::NE: return "ne";
72  case ARMCC::HS: return "hs";
73  case ARMCC::LO: return "lo";
74  case ARMCC::MI: return "mi";
75  case ARMCC::PL: return "pl";
76  case ARMCC::VS: return "vs";
77  case ARMCC::VC: return "vc";
78  case ARMCC::HI: return "hi";
79  case ARMCC::LS: return "ls";
80  case ARMCC::GE: return "ge";
81  case ARMCC::LT: return "lt";
82  case ARMCC::GT: return "gt";
83  case ARMCC::LE: return "le";
84  case ARMCC::AL: return "al";
85  }
86  llvm_unreachable("Unknown condition code");
87 }
88 
89 namespace ARM_PROC {
90  enum IMod {
91  IE = 2,
92  ID = 3
93  };
94 
95  enum IFlags {
96  F = 1,
97  I = 2,
98  A = 4
99  };
100 
101  inline static const char *IFlagsToString(unsigned val) {
102  switch (val) {
103  default: llvm_unreachable("Unknown iflags operand");
104  case F: return "f";
105  case I: return "i";
106  case A: return "a";
107  }
108  }
109 
110  inline static const char *IModToString(unsigned val) {
111  switch (val) {
112  default: llvm_unreachable("Unknown imod operand");
113  case IE: return "ie";
114  case ID: return "id";
115  }
116  }
117 }
118 
119 namespace ARM_MB {
120  // The Memory Barrier Option constants map directly to the 4-bit encoding of
121  // the option field for memory barrier operations.
122  enum MemBOpt {
124  OSHLD = 1,
125  OSHST = 2,
126  OSH = 3,
128  NSHLD = 5,
129  NSHST = 6,
130  NSH = 7,
132  ISHLD = 9,
133  ISHST = 10,
134  ISH = 11,
136  LD = 13,
137  ST = 14,
138  SY = 15
139  };
140 
141  inline static const char *MemBOptToString(unsigned val, bool HasV8) {
142  switch (val) {
143  default: llvm_unreachable("Unknown memory operation");
144  case SY: return "sy";
145  case ST: return "st";
146  case LD: return HasV8 ? "ld" : "#0xd";
147  case RESERVED_12: return "#0xc";
148  case ISH: return "ish";
149  case ISHST: return "ishst";
150  case ISHLD: return HasV8 ? "ishld" : "#0x9";
151  case RESERVED_8: return "#0x8";
152  case NSH: return "nsh";
153  case NSHST: return "nshst";
154  case NSHLD: return HasV8 ? "nshld" : "#0x5";
155  case RESERVED_4: return "#0x4";
156  case OSH: return "osh";
157  case OSHST: return "oshst";
158  case OSHLD: return HasV8 ? "oshld" : "#0x1";
159  case RESERVED_0: return "#0x0";
160  }
161  }
162 } // namespace ARM_MB
163 
164 namespace ARM_ISB {
181  SY = 15
182  };
183 
184  inline static const char *InstSyncBOptToString(unsigned val) {
185  switch (val) {
186  default: llvm_unreachable("Unkown memory operation");
187  case RESERVED_0: return "#0x0";
188  case RESERVED_1: return "#0x1";
189  case RESERVED_2: return "#0x2";
190  case RESERVED_3: return "#0x3";
191  case RESERVED_4: return "#0x4";
192  case RESERVED_5: return "#0x5";
193  case RESERVED_6: return "#0x6";
194  case RESERVED_7: return "#0x7";
195  case RESERVED_8: return "#0x8";
196  case RESERVED_9: return "#0x9";
197  case RESERVED_10: return "#0xa";
198  case RESERVED_11: return "#0xb";
199  case RESERVED_12: return "#0xc";
200  case RESERVED_13: return "#0xd";
201  case RESERVED_14: return "#0xe";
202  case SY: return "sy";
203  }
204  }
205 } // namespace ARM_ISB
206 
207 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
208 ///
209 static inline bool isARMLowRegister(unsigned Reg) {
210  using namespace ARM;
211  switch (Reg) {
212  case R0: case R1: case R2: case R3:
213  case R4: case R5: case R6: case R7:
214  return true;
215  default:
216  return false;
217  }
218 }
219 
220 /// ARMII - This namespace holds all of the target specific flags that
221 /// instruction info tracks.
222 ///
223 namespace ARMII {
224 
225  /// ARM Index Modes
226  enum IndexMode {
231  };
232 
233  /// ARM Addressing Modes
234  enum AddrMode {
245  AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
249  AddrModeT2_pc = 14, // +/- i12 for pc relative data
250  AddrModeT2_i8s4 = 15, // i8 * 4
252  };
253 
254  inline static const char *AddrModeToString(AddrMode addrmode) {
255  switch (addrmode) {
256  case AddrModeNone: return "AddrModeNone";
257  case AddrMode1: return "AddrMode1";
258  case AddrMode2: return "AddrMode2";
259  case AddrMode3: return "AddrMode3";
260  case AddrMode4: return "AddrMode4";
261  case AddrMode5: return "AddrMode5";
262  case AddrMode6: return "AddrMode6";
263  case AddrModeT1_1: return "AddrModeT1_1";
264  case AddrModeT1_2: return "AddrModeT1_2";
265  case AddrModeT1_4: return "AddrModeT1_4";
266  case AddrModeT1_s: return "AddrModeT1_s";
267  case AddrModeT2_i12: return "AddrModeT2_i12";
268  case AddrModeT2_i8: return "AddrModeT2_i8";
269  case AddrModeT2_so: return "AddrModeT2_so";
270  case AddrModeT2_pc: return "AddrModeT2_pc";
271  case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
272  case AddrMode_i12: return "AddrMode_i12";
273  }
274  }
275 
276  /// Target Operand Flag enum.
277  enum TOF {
278  //===------------------------------------------------------------------===//
279  // ARM Specific MachineOperand flags.
280 
282 
283  /// MO_LO16 - On a symbol operand, this represents a relocation containing
284  /// lower 16 bit of the address. Used only via movw instruction.
286 
287  /// MO_HI16 - On a symbol operand, this represents a relocation containing
288  /// higher 16 bit of the address. Used only via movt instruction.
290 
291  /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
292  /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
293  /// i.e. "FOO$non_lazy_ptr".
294  /// Used only via movw instruction.
296 
297  /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
298  /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
299  /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
301 
302  /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
303  /// relocation containing lower 16 bit of the PC relative address of the
304  /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
305  /// Used only via movw instruction.
307 
308  /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
309  /// relocation containing lower 16 bit of the PC relative address of the
310  /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
311  /// Used only via movt instruction.
313 
314  /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
315  /// call operand.
317  };
318 
319  enum {
320  //===------------------------------------------------------------------===//
321  // Instruction Flags.
322 
323  //===------------------------------------------------------------------===//
324  // This four-bit field describes the addressing mode used.
325  AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
326 
327  // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
328  // and store ops only. Generic "updating" flag is used for ld/st multiple.
329  // The index mode enums are declared in ARMBaseInfo.h
332 
333  //===------------------------------------------------------------------===//
334  // Instruction encoding formats.
335  //
337  FormMask = 0x3f << FormShift,
338 
339  // Pseudo instructions
341 
342  // Multiply instructions
344 
345  // Branch instructions
346  BrFrm = 2 << FormShift,
348 
349  // Data Processing instructions
350  DPFrm = 4 << FormShift,
352 
353  // Load and Store
354  LdFrm = 6 << FormShift,
355  StFrm = 7 << FormShift,
359 
361 
362  // Miscellaneous arithmetic instructions
364  SatFrm = 13 << FormShift,
365 
366  // Extend instructions
367  ExtFrm = 14 << FormShift,
368 
369  // VFP formats
380 
381  // Thumb format
383 
384  // Miscelleaneous format
386 
387  // NEON formats
403 
404  //===------------------------------------------------------------------===//
405  // Misc flags.
406 
407  // UnaryDP - Indicates this is a unary data processing instruction, i.e.
408  // it doesn't have a Rn operand.
409  UnaryDP = 1 << 13,
410 
411  // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
412  // a 16-bit Thumb instruction if certain conditions are met.
413  Xform16Bit = 1 << 14,
414 
415  // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
416  // instruction. Used by the parser to determine whether to require the 'S'
417  // suffix on the mnemonic (when not in an IT block) or preclude it (when
418  // in an IT block).
420 
421  //===------------------------------------------------------------------===//
422  // Code domain.
429 
430  //===------------------------------------------------------------------===//
431  // Field shifts - such shifts are used to set field while generating
432  // machine instructions.
433  //
434  // FIXME: This list will need adjusting/fixing as the MC code emitter
435  // takes shape and the ARMCodeEmitter.cpp bits go away.
437 
458  };
459 
460 } // end namespace ARMII
461 
462 } // end namespace llvm;
463 
464 #endif
#define R4(n)
TOF
Target Operand Flag enum.
Definition: ARMBaseInfo.h:277
IndexMode
ARM Index Modes.
Definition: ARMBaseInfo.h:226
#define R2(n)
#define llvm_unreachable(msg)
static const char * InstSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:184
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)
Definition: ARMBaseInfo.h:68
static const char * IModToString(unsigned val)
Definition: ARMBaseInfo.h:110
#define R6(n)
static const char * MemBOptToString(unsigned val, bool HasV8)
Definition: ARMBaseInfo.h:141
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:234
static const char * IFlagsToString(unsigned val)
Definition: ARMBaseInfo.h:101
static bool isARMLowRegister(unsigned Reg)
Definition: ARMBaseInfo.h:209
static CondCodes getOppositeCondition(CondCodes CC)
Definition: ARMBaseInfo.h:47
static const char * AddrModeToString(AddrMode addrmode)
Definition: ARMBaseInfo.h:254