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SILowerControlFlow.cpp File Reference

This pass lowers the pseudo control flow instructions to real machine instructions. More...

#include "AMDGPU.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
Include dependency graph for SILowerControlFlow.cpp:

Go to the source code of this file.

Detailed Description

This pass lowers the pseudo control flow instructions to real machine instructions.

All control flow is handled using predicated instructions and a predicate stack. Each Scalar ALU controls the operations of 64 Vector ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs by writting to the 64-bit EXEC register (each bit corresponds to a single vector ALU). Typically, for predicates, a vector ALU will write to its bit of the VCC register (like EXEC VCC is 64-bits, one for each Vector ALU) and then the ScalarALU will AND the VCC register with the EXEC to update the predicates.

For example: VCC = V_CMP_GT_F32 VGPR1, VGPR2 SGPR0 = SI_IF VCC VGPR0 = V_ADD_F32 VGPR0, VGPR0 SGPR0 = SI_ELSE SGPR0 VGPR0 = V_SUB_F32 VGPR0, VGPR0 SI_END_CF SGPR0

becomes:

SGPR0 = S_AND_SAVEEXEC_B64 VCC // Save and update the exec mask SGPR0 = S_XOR_B64 SGPR0, EXEC // Clear live bits from saved exec mask S_CBRANCH_EXECZ label0 // This instruction is an optional // optimization which allows us to // branch if all the bits of // EXEC are zero. VGPR0 = V_ADD_F32 VGPR0, VGPR0 // Do the IF block of the branch

label0: SGPR0 = S_OR_SAVEEXEC_B64 EXEC // Restore the exec mask for the Then block EXEC = S_XOR_B64 SGPR0, EXEC // Clear live bits from saved exec mask S_BRANCH_EXECZ label1 // Use our branch optimization // instruction again. VGPR0 = V_SUB_F32 VGPR0, VGPR // Do the THEN block label1: EXEC = S_OR_B64 EXEC, SGPR0 // Re-enable saved exec mask bits

Definition in file SILowerControlFlow.cpp.