66 static const unsigned SkipThreshold = 12;
98 const char *getPassName()
const {
99 return "SI Lower control flow instructions";
109 return new SILowerControlFlowPass(tm);
115 unsigned NumInstr = 0;
118 MBB = *MBB->succ_begin()) {
121 NumInstr < SkipThreshold &&
I != E; ++
I) {
123 if (
I->isBundle() || !
I->isBundled())
124 if (++NumInstr >= SkipThreshold)
155 BuildMI(MBB, Insert, DL,
TII->get(AMDGPU::S_CBRANCH_EXECNZ))
160 BuildMI(MBB, Insert, DL,
TII->get(AMDGPU::EXP))
172 BuildMI(MBB, Insert, DL,
TII->get(AMDGPU::S_ENDPGM));
181 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_AND_SAVEEXEC_B64),
Reg)
185 .addReg(AMDGPU::EXEC)
200 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
203 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
204 .addReg(AMDGPU::EXEC)
219 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_OR_B64), Dst)
220 .addReg(AMDGPU::EXEC)
226 void SILowerControlFlowPass::IfBreak(
MachineInstr &MI) {
234 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_OR_B64), Dst)
241 void SILowerControlFlowPass::ElseBreak(
MachineInstr &MI) {
249 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_OR_B64), Dst)
261 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
262 .addReg(AMDGPU::EXEC)
265 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_CBRANCH_EXECNZ))
267 .addReg(AMDGPU::EXEC);
278 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
279 .addReg(AMDGPU::EXEC)
304 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
320 if (AMDGPU::SReg_32RegClass.contains(Idx)) {
321 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
328 assert(AMDGPU::SReg_64RegClass.contains(Save));
329 assert(AMDGPU::VReg_32RegClass.contains(Idx));
332 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_MOV_B64), Save)
333 .addReg(AMDGPU::EXEC);
336 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC)
340 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
341 .addReg(AMDGPU::VCC);
344 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
349 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
350 .addReg(AMDGPU::VCC);
356 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
357 .addReg(AMDGPU::EXEC)
361 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_CBRANCH_EXECNZ))
366 BuildMI(MBB, &MI, DL,
TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
372 void SILowerControlFlowPass::IndirectSrc(
MachineInstr &MI) {
380 unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0);
386 .addReg(SubReg + Off)
393 void SILowerControlFlowPass::IndirectDst(
MachineInstr &MI) {
401 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0);
415 bool SILowerControlFlowPass::runOnMachineFunction(
MachineFunction &MF) {
420 bool HaveKill =
false;
422 bool NeedWQM =
false;
430 I != MBB.
end(); I = Next) {
441 case AMDGPU::SI_ELSE:
445 case AMDGPU::SI_BREAK:
449 case AMDGPU::SI_IF_BREAK:
453 case AMDGPU::SI_ELSE_BREAK:
457 case AMDGPU::SI_LOOP:
462 case AMDGPU::SI_END_CF:
463 if (--Depth == 0 && HaveKill) {
470 case AMDGPU::SI_KILL:
478 case AMDGPU::S_BRANCH:
482 case AMDGPU::SI_INDIRECT_SRC:
486 case AMDGPU::SI_INDIRECT_DST_V1:
487 case AMDGPU::SI_INDIRECT_DST_V2:
488 case AMDGPU::SI_INDIRECT_DST_V4:
489 case AMDGPU::SI_INDIRECT_DST_V8:
490 case AMDGPU::SI_INDIRECT_DST_V16:
494 case AMDGPU::DS_READ_B32:
497 case AMDGPU::DS_WRITE_B32:
498 case AMDGPU::DS_ADD_U32_RTN:
502 case AMDGPU::V_INTERP_P1_F32:
503 case AMDGPU::V_INTERP_P2_F32:
504 case AMDGPU::V_INTERP_MOV_F32:
517 AMDGPU::M0).addImm(0xffffffff);
523 AMDGPU::EXEC).addReg(AMDGPU::EXEC);
const MachineFunction * getParent() const
MachineBasicBlock * getMBB() const
const HexagonInstrInfo * TII
NodeTy * getNextNode()
Get the next node, or 0 for the list tail.
ID
LLVM Calling Convention Representation.
const MachineInstrBuilder & addImm(int64_t Val) const
const MachineBasicBlock & front() const
FunctionPass * createSILowerControlFlowPass(TargetMachine &tm)
const MachineBasicBlock * getParent() const
bundle_iterator< MachineInstr, instr_iterator > iterator
const MachineOperand & getOperand(unsigned i) const
Instr is a loop (backwards branch).
ItTy next(ItTy it, Dist n)
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
succ_iterator succ_begin()
virtual const TargetInstrInfo * getInstrInfo() const
Interface definition for SIInstrInfo.
const TargetMachine & getTarget() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
virtual const TargetRegisterInfo * getRegisterInfo() const
iterator getFirstNonPHI()
unsigned getReg() const
getReg - Returns the register number.
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
const MachineBasicBlock & back() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
DebugLoc getDebugLoc() const