Information about the stack frame layout on the AMDGPU targets. More...

#include <AMDGPUFrameLowering.h>

Inheritance diagram for llvm::AMDGPUFrameLowering:

Collaboration diagram for llvm::AMDGPUFrameLowering:

Public Member Functions
	AMDGPUFrameLowering (StackDirection D, unsigned StackAl, int LAO, unsigned TransAl=1)

virtual	~AMDGPUFrameLowering ()

virtual unsigned	getStackWidth (const MachineFunction &MF) const

virtual int	getFrameIndexOffset (const MachineFunction &MF, int FI) const

virtual const SpillSlot *	getCalleeSavedSpillSlots (unsigned &NumEntries) const

virtual void	emitPrologue (MachineFunction &MF) const

virtual void	emitEpilogue (MachineFunction &MF, MachineBasicBlock &MBB) const

virtual bool	hasFP (const MachineFunction &MF) const

Public Member Functions inherited from llvm::TargetFrameLowering
	TargetFrameLowering (StackDirection D, unsigned StackAl, int LAO, unsigned TransAl=1, bool StackReal=true)

virtual	~TargetFrameLowering ()

StackDirection	getStackGrowthDirection () const

unsigned	getStackAlignment () const

unsigned	getTransientStackAlignment () const

bool	isStackRealignable () const

int	getOffsetOfLocalArea () const

virtual bool	isFPCloseToIncomingSP () const

virtual bool	targetHandlesStackFrameRounding () const

virtual void	adjustForSegmentedStacks (MachineFunction &MF) const

virtual void	adjustForHiPEPrologue (MachineFunction &MF) const

virtual bool	spillCalleeSavedRegisters (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const

virtual bool	restoreCalleeSavedRegisters (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const

virtual bool	hasReservedCallFrame (const MachineFunction &MF) const

virtual bool	canSimplifyCallFramePseudos (const MachineFunction &MF) const

virtual int	getFrameIndexReference (const MachineFunction &MF, int FI, unsigned &FrameReg) const

virtual void	processFunctionBeforeCalleeSavedScan (MachineFunction &MF, RegScavenger *RS=NULL) const

virtual void	processFunctionBeforeFrameFinalized (MachineFunction &MF, RegScavenger *RS=NULL) const

virtual void	eliminateCallFramePseudoInstr (MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const

Additional Inherited Members
Public Types inherited from llvm::TargetFrameLowering
enum	StackDirection { StackGrowsUp, StackGrowsDown }

Detailed Description

Information about the stack frame layout on the AMDGPU targets.

It holds the direction of the stack growth, the known stack alignment on entry to each function, and the offset to the locals area. See TargetFrameInfo for more comments.

Definition at line 28 of file AMDGPUFrameLowering.h.

Constructor & Destructor Documentation

AMDGPUFrameLowering::AMDGPUFrameLowering	(	StackDirection	D,
		unsigned	StackAl,
		int	LAO,
		unsigned	TransAl = `1`
	)

Definition at line 21 of file AMDGPUFrameLowering.cpp.

AMDGPUFrameLowering::~AMDGPUFrameLowering ( )

virtual

Definition at line 25 of file AMDGPUFrameLowering.cpp.

Member Function Documentation

void AMDGPUFrameLowering::emitEpilogue	(	MachineFunction &	MF,
		MachineBasicBlock &	MBB
	)		const

virtual

Implements llvm::TargetFrameLowering.

Definition at line 96 of file AMDGPUFrameLowering.cpp.

void AMDGPUFrameLowering::emitPrologue ( MachineFunction & MF ) const

virtual

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.

Implements llvm::TargetFrameLowering.

Definition at line 93 of file AMDGPUFrameLowering.cpp.

const TargetFrameLowering::SpillSlot * AMDGPUFrameLowering::getCalleeSavedSpillSlots ( unsigned & NumEntries ) const

virtual

getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry for each callee saved register that must be spilled to a particular stack location if it is spilled.

Each entry in this array contains a <register,offset> pair, indicating the fixed offset from the incoming stack pointer that each register should be spilled at. If a register is not listed here, the code generator is allowed to spill it anywhere it chooses.

Reimplemented from llvm::TargetFrameLowering.

Definition at line 88 of file AMDGPUFrameLowering.cpp.

int AMDGPUFrameLowering::getFrameIndexOffset	(	const MachineFunction &	MF,
		int	FI
	)		const

virtual

Returns: The number of registers allocated for FI.

Reimplemented from llvm::TargetFrameLowering.

Definition at line 74 of file AMDGPUFrameLowering.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineFrameInfo::getObjectIndexBegin(), llvm::MachineFrameInfo::getObjectSize(), and getStackWidth().

unsigned AMDGPUFrameLowering::getStackWidth ( const MachineFunction & MF ) const

virtual

Returns: The number of 32-bit sub-registers that are used when storing values to the stack.

Definition at line 27 of file AMDGPUFrameLowering.cpp.

Referenced by getFrameIndexOffset(), and llvm::R600InstrInfo::reserveIndirectRegisters().

bool AMDGPUFrameLowering::hasFP ( const MachineFunction & MF ) const

virtual

hasFP - Return true if the specified function should have a dedicated frame pointer register. For most targets this is true only if the function has variable sized allocas or if frame pointer elimination is disabled.

Implements llvm::TargetFrameLowering.

Definition at line 101 of file AMDGPUFrameLowering.cpp.

The documentation for this class was generated from the following files:

Public Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation