llvm::AMDGPUInstrInfo Member List

This is the complete list of members for llvm::AMDGPUInstrInfo, including all inherited members.

AMDGPUInstrInfo(TargetMachine &tm)	llvm::AMDGPUInstrInfo	explicit
buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const =0	llvm::AMDGPUInstrInfo	pure virtual
buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const =0	llvm::AMDGPUInstrInfo	pure virtual
buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const =0	llvm::AMDGPUInstrInfo	pure virtual
calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const =0	llvm::AMDGPUInstrInfo	pure virtual
canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops) const	llvm::AMDGPUInstrInfo
convertToISA(MachineInstr &MI, MachineFunction &MF, DebugLoc DL) const	llvm::AMDGPUInstrInfo	virtual
convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const	llvm::AMDGPUInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const =0	llvm::AMDGPUInstrInfo	pure virtual
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const	llvm::AMDGPUInstrInfo
expandPostRAPseudo(MachineBasicBlock::iterator MI) const	llvm::AMDGPUInstrInfo	virtual
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const	llvm::AMDGPUInstrInfo	protected
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const	llvm::AMDGPUInstrInfo	protected
getIEQOpcode() const =0	llvm::AMDGPUInstrInfo	pure virtual
getIndirectAddrRegClass() const =0	llvm::AMDGPUInstrInfo	pure virtual
getIndirectIndexBegin(const MachineFunction &MF) const	llvm::AMDGPUInstrInfo	protectedvirtual
getIndirectIndexEnd(const MachineFunction &MF) const	llvm::AMDGPUInstrInfo	protectedvirtual
getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const	llvm::AMDGPUInstrInfo
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=0) const	llvm::AMDGPUInstrInfo
getRegisterInfo() const =0	llvm::AMDGPUInstrInfo	pure virtual
hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const	llvm::AMDGPUInstrInfo
hasStoreFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const	llvm::AMDGPUInstrInfo
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const	llvm::AMDGPUInstrInfo
isAExtLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const	llvm::AMDGPUInstrInfo
isExtLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::AMDGPUInstrInfo
isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const	llvm::AMDGPUInstrInfo
isLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isMov(unsigned opcode) const =0	llvm::AMDGPUInstrInfo	pure virtual
isPredicable(MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isPredicated(const MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isRegisterLoad(const MachineInstr &MI) const	llvm::AMDGPUInstrInfo
isRegisterStore(const MachineInstr &MI) const	llvm::AMDGPUInstrInfo
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const	llvm::AMDGPUInstrInfo
isSExtLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::AMDGPUInstrInfo
isStoreFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const	llvm::AMDGPUInstrInfo
isStoreInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isSWSExtLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isTruncStoreInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isZExtLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::AMDGPUInstrInfo
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const	llvm::AMDGPUInstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const	llvm::AMDGPUInstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::AMDGPUInstrInfo
SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const	llvm::AMDGPUInstrInfo
TM	llvm::AMDGPUInstrInfo	protected
unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::AMDGPUInstrInfo
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const	llvm::AMDGPUInstrInfo