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llvm::AMDGPUInstrInfo Class Referenceabstract

#include <AMDGPUInstrInfo.h>

Inheritance diagram for llvm::AMDGPUInstrInfo:
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Collaboration diagram for llvm::AMDGPUInstrInfo:
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Public Member Functions

 AMDGPUInstrInfo (TargetMachine &tm)
 
virtual const AMDGPURegisterInfo & getRegisterInfo () const =0
 
bool isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
 
unsigned isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const
 
unsigned isLoadFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const
 
bool hasLoadFromStackSlot (const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
 
unsigned isStoreFromStackSlot (const MachineInstr *MI, int &FrameIndex) const
 
unsigned isStoreFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const
 
bool hasStoreFromStackSlot (const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const
 
MachineInstr * convertToThreeAddress (MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const
 
virtual void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const =0
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
 
virtual bool expandPostRAPseudo (MachineBasicBlock::iterator MI) const
 
bool canFoldMemoryOperand (const MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops) const
 
bool unfoldMemoryOperand (MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const
 
bool unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const
 
unsigned getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=0) const
 
bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
 
bool ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
 
bool isPredicated (const MachineInstr *MI) const
 
bool SubsumesPredicate (const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const
 
bool DefinesPredicate (MachineInstr *MI, std::vector< MachineOperand > &Pred) const
 
bool isPredicable (MachineInstr *MI) const
 
bool isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const
 
bool isLoadInst (llvm::MachineInstr *MI) const
 
bool isExtLoadInst (llvm::MachineInstr *MI) const
 
bool isSWSExtLoadInst (llvm::MachineInstr *MI) const
 
bool isSExtLoadInst (llvm::MachineInstr *MI) const
 
bool isZExtLoadInst (llvm::MachineInstr *MI) const
 
bool isAExtLoadInst (llvm::MachineInstr *MI) const
 
bool isStoreInst (llvm::MachineInstr *MI) const
 
bool isTruncStoreInst (llvm::MachineInstr *MI) const
 
bool isRegisterStore (const MachineInstr &MI) const
 
bool isRegisterLoad (const MachineInstr &MI) const
 
virtual unsigned getIEQOpcode () const =0
 
virtual bool isMov (unsigned opcode) const =0
 
virtual unsigned calculateIndirectAddress (unsigned RegIndex, unsigned Channel) const =0
 Calculate the "Indirect Address" for the given RegIndex and Channel. More...
 
virtual const TargetRegisterClass * getIndirectAddrRegClass () const =0
 
virtual MachineInstrBuilder buildIndirectWrite (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const =0
 Build instruction(s) for an indirect register write. More...
 
virtual MachineInstrBuilder buildIndirectRead (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const =0
 Build instruction(s) for an indirect register read. More...
 
virtual void convertToISA (MachineInstr &MI, MachineFunction &MF, DebugLoc DL) const
 Convert the AMDIL MachineInstr to a supported ISA MachineInstr. More...
 
virtual MachineInstr * buildMovInstr (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const =0
 Build a MOV instruction. More...
 
int getMaskedMIMGOp (uint16_t Opcode, unsigned Channels) const
 Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Channels. More...
 

Protected Member Functions

MachineInstr * foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const
 
MachineInstr * foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const
 
virtual int getIndirectIndexBegin (const MachineFunction &MF) const
 
virtual int getIndirectIndexEnd (const MachineFunction &MF) const
 

Protected Attributes

TargetMachine & TM
 

Detailed Description

Definition at line 41 of file AMDGPUInstrInfo.h.

Constructor & Destructor Documentation

AMDGPUInstrInfo::AMDGPUInstrInfo ( TargetMachine &  tm)
explicit

Definition at line 34 of file AMDGPUInstrInfo.cpp.

Member Function Documentation

virtual MachineInstrBuilder llvm::AMDGPUInstrInfo::buildIndirectRead ( MachineBasicBlock *  MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const
pure virtual

Build instruction(s) for an indirect register read.

Returns
The instruction that performs the indirect register read

Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.

Referenced by expandPostRAPseudo().

virtual MachineInstrBuilder llvm::AMDGPUInstrInfo::buildIndirectWrite ( MachineBasicBlock *  MBB,
MachineBasicBlock::iterator  I,
unsigned  ValueReg,
unsigned  Address,
unsigned  OffsetReg 
) const
pure virtual

Build instruction(s) for an indirect register write.

Returns
The instruction that performs the indirect register write

Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.

Referenced by expandPostRAPseudo().

virtual MachineInstr* llvm::AMDGPUInstrInfo::buildMovInstr ( MachineBasicBlock *  MBB,
MachineBasicBlock::iterator  I,
unsigned  DstReg,
unsigned  SrcReg 
) const
pure virtual

Build a MOV instruction.

Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.

Referenced by expandPostRAPseudo().

virtual unsigned llvm::AMDGPUInstrInfo::calculateIndirectAddress ( unsigned  RegIndex,
unsigned  Channel 
) const
pure virtual

Calculate the "Indirect Address" for the given RegIndex and Channel.

We model indirect addressing using a virtual address space that can be accesed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.

Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.

Referenced by expandPostRAPseudo().

bool AMDGPUInstrInfo::canFoldMemoryOperand ( const MachineInstr *  MI,
const SmallVectorImpl< unsigned > &  Ops 
) const

Definition at line 191 of file AMDGPUInstrInfo.cpp.

void AMDGPUInstrInfo::convertToISA ( MachineInstr &  MI,
MachineFunction &  MF,
DebugLoc  DL 
) const
virtual

Convert the AMDIL MachineInstr to a supported ISA MachineInstr.

Definition at line 331 of file AMDGPUInstrInfo.cpp.

References llvm::AMDGPURegisterInfo::getISARegClass(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::TargetRegisterInfo::isVirtualRegister(), MRI, and llvm::MachineRegisterInfo::setRegClass().

MachineInstr * AMDGPUInstrInfo::convertToThreeAddress ( MachineFunction::iterator &  MFI,
MachineBasicBlock::iterator &  MBBI,
LiveVariables *  LV 
) const

Definition at line 84 of file AMDGPUInstrInfo.cpp.

virtual void llvm::AMDGPUInstrInfo::copyPhysReg ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
DebugLoc  DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
pure virtual

Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.

bool AMDGPUInstrInfo::DefinesPredicate ( MachineInstr *  MI,
std::vector< MachineOperand > &  Pred 
) const

Definition at line 254 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::expandPostRAPseudo ( MachineBasicBlock::iterator  MI) const
virtual

Definition at line 125 of file AMDGPUInstrInfo.cpp.

References buildIndirectRead(), buildIndirectWrite(), buildMovInstr(), calculateIndirectAddress(), llvm::MachineBasicBlock::erase(), getIndirectAddrRegClass(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterClass::getRegister(), isRegisterLoad(), and isRegisterStore().

MachineInstr * AMDGPUInstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF,
MachineInstr *  MI,
const SmallVectorImpl< unsigned > &  Ops,
int  FrameIndex 
) const
protected

Definition at line 175 of file AMDGPUInstrInfo.cpp.

MachineInstr * AMDGPUInstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF,
MachineInstr *  MI,
const SmallVectorImpl< unsigned > &  Ops,
MachineInstr *  LoadMI 
) const
protected

Definition at line 183 of file AMDGPUInstrInfo.cpp.

virtual unsigned llvm::AMDGPUInstrInfo::getIEQOpcode ( ) const
pure virtual

Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.

virtual const TargetRegisterClass* llvm::AMDGPUInstrInfo::getIndirectAddrRegClass ( ) const
pure virtual
Returns
The register class to be used for loading and storing values from an "Indirect Address" .

Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.

Referenced by expandPostRAPseudo(), and getIndirectIndexBegin().

int AMDGPUInstrInfo::getIndirectIndexBegin ( const MachineFunction &  MF) const
protectedvirtual
Returns
the smallest register index that will be accessed by an indirect read or write or -1 if indirect addressing is not used by this program.

Definition at line 279 of file AMDGPUInstrInfo.cpp.

References llvm::TargetRegisterClass::contains(), llvm::MachineFunction::getFrameInfo(), getIndirectAddrRegClass(), llvm::MachineFrameInfo::getNumObjects(), llvm::TargetRegisterClass::getNumRegs(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getRegister(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::A64CC::LE, LI, llvm::MachineRegisterInfo::livein_begin(), llvm::MachineRegisterInfo::livein_empty(), llvm::MachineRegisterInfo::livein_end(), and MRI.

Referenced by llvm::SIInstrInfo::buildIndirectRead(), llvm::SIInstrInfo::buildIndirectWrite(), getIndirectIndexEnd(), llvm::SIInstrInfo::reserveIndirectRegisters(), and llvm::R600InstrInfo::reserveIndirectRegisters().

int AMDGPUInstrInfo::getIndirectIndexEnd ( const MachineFunction &  MF) const
protectedvirtual
Returns
the largest register index that will be accessed by an indirect read or write or -1 if indirect addressing is not used by this program.

Definition at line 314 of file AMDGPUInstrInfo.cpp.

References llvm::TargetFrameLowering::getFrameIndexOffset(), llvm::MachineFunction::getFrameInfo(), llvm::TargetMachine::getFrameLowering(), getIndirectIndexBegin(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineFrameInfo::hasVarSizedObjects(), and TM.

Referenced by llvm::SIInstrInfo::reserveIndirectRegisters(), and llvm::R600InstrInfo::reserveIndirectRegisters().

int AMDGPUInstrInfo::getMaskedMIMGOp ( uint16_t  Opcode,
unsigned  Channels 
) const

Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Channels.

Definition at line 352 of file AMDGPUInstrInfo.cpp.

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection().

unsigned AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold ( unsigned  Opc,
bool  UnfoldLoad,
bool  UnfoldStore,
unsigned *  LoadRegIndex = 0 
) const

Definition at line 213 of file AMDGPUInstrInfo.cpp.

const AMDGPURegisterInfo & AMDGPUInstrInfo::getRegisterInfo ( ) const
pure virtual

Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.

Definition at line 37 of file AMDGPUInstrInfo.cpp.

Referenced by convertToISA().

bool AMDGPUInstrInfo::hasLoadFromStackSlot ( const MachineInstr *  MI,
const MachineMemOperand *&  MMO,
int &  FrameIndex 
) const

Definition at line 60 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::hasStoreFromStackSlot ( const MachineInstr *  MI,
const MachineMemOperand *&  MMO,
int &  FrameIndex 
) const

Definition at line 76 of file AMDGPUInstrInfo.cpp.

void AMDGPUInstrInfo::insertNoop ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI 
) const

Definition at line 237 of file AMDGPUInstrInfo.cpp.

bool llvm::AMDGPUInstrInfo::isAExtLoadInst ( llvm::MachineInstr *  MI) const
bool AMDGPUInstrInfo::isCoalescableExtInstr ( const MachineInstr &  MI,
unsigned &  SrcReg,
unsigned &  DstReg,
unsigned &  SubIdx 
) const

Definition at line 41 of file AMDGPUInstrInfo.cpp.

bool llvm::AMDGPUInstrInfo::isExtLoadInst ( llvm::MachineInstr *  MI) const
unsigned AMDGPUInstrInfo::isLoadFromStackSlot ( const MachineInstr *  MI,
int &  FrameIndex 
) const

Definition at line 48 of file AMDGPUInstrInfo.cpp.

unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE ( const MachineInstr *  MI,
int &  FrameIndex 
) const

Definition at line 54 of file AMDGPUInstrInfo.cpp.

bool llvm::AMDGPUInstrInfo::isLoadInst ( llvm::MachineInstr *  MI) const
virtual bool llvm::AMDGPUInstrInfo::isMov ( unsigned  opcode) const
pure virtual

Implemented in llvm::R600InstrInfo, and llvm::SIInstrInfo.

bool AMDGPUInstrInfo::isPredicable ( MachineInstr *  MI) const

Definition at line 260 of file AMDGPUInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::isPredicable().

Referenced by llvm::R600InstrInfo::isPredicable().

bool AMDGPUInstrInfo::isPredicated ( const MachineInstr *  MI) const

Definition at line 242 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::isRegisterLoad ( const MachineInstr &  MI) const

Definition at line 275 of file AMDGPUInstrInfo.cpp.

References AMDGPU_FLAG_REGISTER_LOAD, and llvm::MachineInstr::getOpcode().

Referenced by expandPostRAPseudo().

bool AMDGPUInstrInfo::isRegisterStore ( const MachineInstr &  MI) const

Definition at line 271 of file AMDGPUInstrInfo.cpp.

References AMDGPU_FLAG_REGISTER_STORE, and llvm::MachineInstr::getOpcode().

Referenced by expandPostRAPseudo().

bool AMDGPUInstrInfo::isSafeToMoveRegClassDefs ( const TargetRegisterClass *  RC) const

Definition at line 266 of file AMDGPUInstrInfo.cpp.

bool llvm::AMDGPUInstrInfo::isSExtLoadInst ( llvm::MachineInstr *  MI) const
unsigned AMDGPUInstrInfo::isStoreFromStackSlot ( const MachineInstr *  MI,
int &  FrameIndex 
) const

Definition at line 66 of file AMDGPUInstrInfo.cpp.

unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE ( const MachineInstr *  MI,
int &  FrameIndex 
) const

Definition at line 71 of file AMDGPUInstrInfo.cpp.

bool llvm::AMDGPUInstrInfo::isStoreInst ( llvm::MachineInstr *  MI) const
bool llvm::AMDGPUInstrInfo::isSWSExtLoadInst ( llvm::MachineInstr *  MI) const
bool llvm::AMDGPUInstrInfo::isTruncStoreInst ( llvm::MachineInstr *  MI) const
bool llvm::AMDGPUInstrInfo::isZExtLoadInst ( llvm::MachineInstr *  MI) const
void AMDGPUInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI 
) const

Definition at line 117 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::ReverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const

Definition at line 232 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::shouldScheduleLoadsNear ( SDNode *  Load1,
SDNode *  Load2,
int64_t  Offset1,
int64_t  Offset2,
unsigned  NumLoads 
) const

Definition at line 220 of file AMDGPUInstrInfo.cpp.

void AMDGPUInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI 
) const

Definition at line 107 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::SubsumesPredicate ( const SmallVectorImpl< MachineOperand > &  Pred1,
const SmallVectorImpl< MachineOperand > &  Pred2 
) const

Definition at line 247 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::unfoldMemoryOperand ( MachineFunction &  MF,
MachineInstr *  MI,
unsigned  Reg,
bool  UnfoldLoad,
bool  UnfoldStore,
SmallVectorImpl< MachineInstr * > &  NewMIs 
) const

Definition at line 197 of file AMDGPUInstrInfo.cpp.

bool AMDGPUInstrInfo::unfoldMemoryOperand ( SelectionDAG &  DAG,
SDNode *  N,
SmallVectorImpl< SDNode * > &  NewNodes 
) const

Definition at line 206 of file AMDGPUInstrInfo.cpp.

Member Data Documentation

TargetMachine& llvm::AMDGPUInstrInfo::TM
protected

Definition at line 48 of file AMDGPUInstrInfo.h.

Referenced by llvm::R600InstrInfo::buildSlotOfVectorInstruction(), getIndirectIndexEnd(), and llvm::R600InstrInfo::reserveIndirectRegisters().

The documentation for this class was generated from the following files:

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