llvm::PPCInstrInfo Member List

This is the complete list of members for llvm::PPCInstrInfo, including all inherited members.

AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const	llvm::PPCInstrInfo	virtual
analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const	llvm::PPCInstrInfo	virtual
canInsertSelect(const MachineBasicBlock &, const SmallVectorImpl< MachineOperand > &Cond, unsigned, unsigned, int &, int &, int &) const	llvm::PPCInstrInfo	virtual
commuteInstruction(MachineInstr *MI, bool NewMI) const	llvm::PPCInstrInfo	virtual
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const	llvm::PPCInstrInfo	virtual
CreateTargetHazardRecognizer(const TargetMachine *TM, const ScheduleDAG *DAG) const	llvm::PPCInstrInfo
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const	llvm::PPCInstrInfo
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const	llvm::PPCInstrInfo	virtual
FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const	llvm::PPCInstrInfo	virtual
GetInstSizeInBytes(const MachineInstr *MI) const	llvm::PPCInstrInfo	virtual
getRegisterInfo() const	llvm::PPCInstrInfo	inlinevirtual
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const	llvm::PPCInstrInfo	virtual
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const	llvm::PPCInstrInfo	virtual
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, const SmallVectorImpl< MachineOperand > &Cond, unsigned TrueReg, unsigned FalseReg) const	llvm::PPCInstrInfo	virtual
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const	llvm::PPCInstrInfo
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::PPCInstrInfo
isPredicable(MachineInstr *MI) const	llvm::PPCInstrInfo	virtual
isPredicated(const MachineInstr *MI) const	llvm::PPCInstrInfo
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const	llvm::PPCInstrInfo	inlinevirtual
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const	llvm::PPCInstrInfo	inlinevirtual
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, const BranchProbability &Probability) const	llvm::PPCInstrInfo	virtual
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const	llvm::PPCInstrInfo	inlinevirtual
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::PPCInstrInfo
isUnpredicatedTerminator(const MachineInstr *MI) const	llvm::PPCInstrInfo	virtual
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::PPCInstrInfo	virtual
optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const	llvm::PPCInstrInfo	virtual
PPCInstrInfo(PPCTargetMachine &TM)	llvm::PPCInstrInfo	explicit
PredicateInstruction(MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const	llvm::PPCInstrInfo	virtual
RemoveBranch(MachineBasicBlock &MBB) const	llvm::PPCInstrInfo	virtual
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const	llvm::PPCInstrInfo	virtual
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::PPCInstrInfo	virtual
SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const	llvm::PPCInstrInfo	virtual