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llvm::TargetInstrInfo Member List

This is the complete list of members for llvm::TargetInstrInfo, including all inherited members.

AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const llvm::TargetInstrInfoinlinevirtual
analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const llvm::TargetInstrInfoinlinevirtual
analyzeSelect(const MachineInstr *MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const llvm::TargetInstrInfoinlinevirtual
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const llvm::TargetInstrInfoinlinevirtual
breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const llvm::TargetInstrInfoinlinevirtual
canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops) const llvm::TargetInstrInfovirtual
canInsertSelect(const MachineBasicBlock &MBB, const SmallVectorImpl< MachineOperand > &Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const llvm::TargetInstrInfoinlinevirtual
commuteInstruction(MachineInstr *MI, bool NewMI=false) const llvm::TargetInstrInfovirtual
computeDefOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI) const llvm::TargetInstrInfo
computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const llvm::TargetInstrInfo
convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const llvm::TargetInstrInfoinlinevirtual
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const llvm::TargetInstrInfoinlinevirtual
CreateTargetHazardRecognizer(const TargetMachine *TM, const ScheduleDAG *DAG) const llvm::TargetInstrInfovirtual
CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const llvm::TargetInstrInfovirtual
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const llvm::TargetInstrInfovirtual
CreateTargetScheduleState(const TargetMachine *, const ScheduleDAG *) const llvm::TargetInstrInfoinlinevirtual
defaultDefLatency(const MCSchedModel *SchedModel, const MachineInstr *DefMI) const llvm::TargetInstrInfo
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const llvm::TargetInstrInfoinlinevirtual
duplicate(MachineInstr *Orig, MachineFunction &MF) const llvm::TargetInstrInfovirtual
enableClusterLoads() const llvm::TargetInstrInfoinlinevirtual
expandPostRAPseudo(MachineBasicBlock::iterator MI) const llvm::TargetInstrInfoinlinevirtual
findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const llvm::TargetInstrInfovirtual
FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const llvm::TargetInstrInfoinlinevirtual
foldMemoryOperand(MachineBasicBlock::iterator MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const llvm::TargetInstrInfo
foldMemoryOperand(MachineBasicBlock::iterator MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const llvm::TargetInstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const llvm::TargetInstrInfoinlineprotectedvirtual
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const llvm::TargetInstrInfoinlineprotectedvirtual
get(unsigned Opcode) const llvm::MCInstrInfoinline
getCallFrameDestroyOpcode() const llvm::TargetInstrInfoinline
getCallFrameSetupOpcode() const llvm::TargetInstrInfoinline
getExecutionDomain(const MachineInstr *MI) const llvm::TargetInstrInfoinlinevirtual
getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const llvm::TargetInstrInfovirtual
getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=0) const llvm::TargetInstrInfovirtual
getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) const llvm::TargetInstrInfovirtual
getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const llvm::TargetInstrInfoinlinevirtual
getName(unsigned Opcode) const llvm::MCInstrInfoinline
getNoopForMachoTarget(MCInst &NopInst) const llvm::TargetInstrInfoinlinevirtual
getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr *MI) const llvm::TargetInstrInfovirtual
getNumOpcodes() const llvm::MCInstrInfoinline
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=0) const llvm::TargetInstrInfoinlinevirtual
getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const llvm::TargetInstrInfovirtual
getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const llvm::TargetInstrInfovirtual
getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const llvm::TargetInstrInfoinlinevirtual
getPredicationCost(const MachineInstr *MI) const llvm::TargetInstrInfovirtual
getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const llvm::TargetInstrInfo
getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const TargetMachine *TM) const llvm::TargetInstrInfovirtual
getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const llvm::TargetInstrInfoinlinevirtual
hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const llvm::TargetInstrInfoinlinevirtual
hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const llvm::TargetInstrInfovirtual
hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const llvm::TargetInstrInfovirtual
hasStoreToStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const llvm::TargetInstrInfovirtual
InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, unsigned NO)llvm::MCInstrInfoinline
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const llvm::TargetInstrInfoinlinevirtual
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const llvm::TargetInstrInfovirtual
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, const SmallVectorImpl< MachineOperand > &Cond, unsigned TrueReg, unsigned FalseReg) const llvm::TargetInstrInfoinlinevirtual
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const llvm::TargetInstrInfoinlinevirtual
isHighLatencyDef(int opc) const llvm::TargetInstrInfoinlinevirtual
isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const llvm::TargetInstrInfoinlinevirtual
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const llvm::TargetInstrInfoinlinevirtual
isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const llvm::TargetInstrInfoinlinevirtual
isPredicable(MachineInstr *MI) const llvm::TargetInstrInfoinlinevirtual
isPredicated(const MachineInstr *MI) const llvm::TargetInstrInfoinlinevirtual
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const llvm::TargetInstrInfoinlinevirtual
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const llvm::TargetInstrInfoinlinevirtual
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, const BranchProbability &Probability) const llvm::TargetInstrInfoinlinevirtual
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const llvm::TargetInstrInfoinlinevirtual
isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const llvm::TargetInstrInfoinlineprotectedvirtual
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const llvm::TargetInstrInfoinlinevirtual
isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const llvm::TargetInstrInfovirtual
isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, int &SrcFrameIndex) const llvm::TargetInstrInfoinlinevirtual
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const llvm::TargetInstrInfoinlinevirtual
isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const llvm::TargetInstrInfoinlinevirtual
isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=0) const llvm::TargetInstrInfoinline
isUnpredicatedTerminator(const MachineInstr *MI) const llvm::TargetInstrInfovirtual
isZeroCost(unsigned Opcode) const llvm::TargetInstrInfoinline
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const llvm::TargetInstrInfoinlinevirtual
optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const llvm::TargetInstrInfoinlinevirtual
optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const llvm::TargetInstrInfoinlinevirtual
optimizeSelect(MachineInstr *MI, bool PreferFalse=false) const llvm::TargetInstrInfoinlinevirtual
PredicateInstruction(MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const llvm::TargetInstrInfovirtual
produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI=0) const llvm::TargetInstrInfovirtual
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const llvm::TargetInstrInfovirtual
RemoveBranch(MachineBasicBlock &MBB) const llvm::TargetInstrInfoinlinevirtual
ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const llvm::TargetInstrInfovirtual
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const llvm::TargetInstrInfoinlinevirtual
setExecutionDomain(MachineInstr *MI, unsigned Domain) const llvm::TargetInstrInfoinlinevirtual
shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const llvm::TargetInstrInfoinlinevirtual
shouldScheduleAdjacent(MachineInstr *First, MachineInstr *Second) const llvm::TargetInstrInfoinlinevirtual
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const llvm::TargetInstrInfoinlinevirtual
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const llvm::TargetInstrInfoinlinevirtual
SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const llvm::TargetInstrInfoinlinevirtual
TargetInstrInfo(int CFSetupOpcode=-1, int CFDestroyOpcode=-1)llvm::TargetInstrInfoinline
unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const llvm::TargetInstrInfoinlinevirtual
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const llvm::TargetInstrInfoinlinevirtual
usePreRAHazardRecognizer() const llvm::TargetInstrInfo
verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const llvm::TargetInstrInfoinlinevirtual
~TargetInstrInfo()llvm::TargetInstrInfovirtual

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