llvm::TargetSubtargetInfo Member List

This is the complete list of members for llvm::TargetSubtargetInfo, including all inherited members.

adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const	llvm::TargetSubtargetInfo	inlinevirtual
ANTIDEP_ALL enum value	llvm::TargetSubtargetInfo
ANTIDEP_CRITICAL enum value	llvm::TargetSubtargetInfo
ANTIDEP_NONE enum value	llvm::TargetSubtargetInfo
AntiDepBreakMode enum name	llvm::TargetSubtargetInfo
enableMachineScheduler() const	llvm::TargetSubtargetInfo	virtual
enablePostRAScheduler(CodeGenOpt::Level OptLevel, AntiDepBreakMode &Mode, RegClassVector &CriticalPathRCs) const	llvm::TargetSubtargetInfo	virtual
getFeatureBits() const	llvm::MCSubtargetInfo	inline
getInstrItineraryForCPU(StringRef CPU) const	llvm::MCSubtargetInfo
getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const	llvm::MCSubtargetInfo	inline
getSchedModel() const	llvm::MCSubtargetInfo	inline
getSchedModelForCPU(StringRef CPU) const	llvm::MCSubtargetInfo
getTargetTriple() const	llvm::MCSubtargetInfo	inline
getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const	llvm::MCSubtargetInfo	inline
getWriteProcResBegin(const MCSchedClassDesc *SC) const	llvm::MCSubtargetInfo	inline
getWriteProcResEnd(const MCSchedClassDesc *SC) const	llvm::MCSubtargetInfo	inline
InitCPUSchedModel(StringRef CPU)	llvm::MCSubtargetInfo
initInstrItins(InstrItineraryData &InstrItins) const	llvm::MCSubtargetInfo
InitMCProcessorInfo(StringRef CPU, StringRef FS)	llvm::MCSubtargetInfo
InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, const SubtargetFeatureKV *PF, const SubtargetFeatureKV *PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP, unsigned NF, unsigned NP)	llvm::MCSubtargetInfo
overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const	llvm::TargetSubtargetInfo	inlinevirtual
RegClassVector typedef	llvm::TargetSubtargetInfo
resetSubtargetFeatures(const MachineFunction *MF)	llvm::TargetSubtargetInfo	inlinevirtual
resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const	llvm::TargetSubtargetInfo	inlinevirtual
TargetSubtargetInfo()	llvm::TargetSubtargetInfo	protected
ToggleFeature(uint64_t FB)	llvm::MCSubtargetInfo
ToggleFeature(StringRef FS)	llvm::MCSubtargetInfo
useAA() const	llvm::TargetSubtargetInfo	virtual
useMachineScheduler() const	llvm::TargetSubtargetInfo
~TargetSubtargetInfo()	llvm::TargetSubtargetInfo	virtual