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MipsDisassembler.cpp
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1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the Mips Disassembler.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Mips.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/MathExtras.h"
22 #include "llvm/Support/MemoryObject.h"
23 #include "llvm/Support/TargetRegistry.h"
24 
25 using namespace llvm;
26 
27 typedef MCDisassembler::DecodeStatus DecodeStatus;
28 
29 namespace {
30 
31 /// MipsDisassemblerBase - a disasembler class for Mips.
32 class MipsDisassemblerBase : public MCDisassembler {
33 public:
34  /// Constructor - Initializes the disassembler.
35  ///
36  MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
37  bool bigEndian) :
38  MCDisassembler(STI), RegInfo(Info),
39  IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
40 
41  virtual ~MipsDisassemblerBase() {}
42 
43  const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
44 
45  bool isN64() const { return IsN64; }
46 
47 private:
48  OwningPtr<const MCRegisterInfo> RegInfo;
49  bool IsN64;
50 protected:
51  bool isBigEndian;
52 };
53 
54 /// MipsDisassembler - a disasembler class for Mips32.
55 class MipsDisassembler : public MipsDisassemblerBase {
56  bool IsMicroMips;
57 public:
58  /// Constructor - Initializes the disassembler.
59  ///
60  MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
61  bool bigEndian) :
62  MipsDisassemblerBase(STI, Info, bigEndian) {
63  IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
64  }
65 
66  /// getInstruction - See MCDisassembler.
67  virtual DecodeStatus getInstruction(MCInst &instr,
68  uint64_t &size,
69  const MemoryObject &region,
70  uint64_t address,
71  raw_ostream &vStream,
72  raw_ostream &cStream) const;
73 };
74 
75 
76 /// Mips64Disassembler - a disasembler class for Mips64.
77 class Mips64Disassembler : public MipsDisassemblerBase {
78 public:
79  /// Constructor - Initializes the disassembler.
80  ///
81  Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
82  bool bigEndian) :
83  MipsDisassemblerBase(STI, Info, bigEndian) {}
84 
85  /// getInstruction - See MCDisassembler.
86  virtual DecodeStatus getInstruction(MCInst &instr,
87  uint64_t &size,
88  const MemoryObject &region,
89  uint64_t address,
90  raw_ostream &vStream,
91  raw_ostream &cStream) const;
92 };
93 
94 } // end anonymous namespace
95 
96 // Forward declare these because the autogenerated code will reference them.
97 // Definitions are further down.
98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
99  unsigned RegNo,
100  uint64_t Address,
101  const void *Decoder);
102 
103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
104  unsigned RegNo,
105  uint64_t Address,
106  const void *Decoder);
107 
108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
109  unsigned RegNo,
110  uint64_t Address,
111  const void *Decoder);
112 
113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
114  unsigned Insn,
115  uint64_t Address,
116  const void *Decoder);
117 
118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
119  unsigned RegNo,
120  uint64_t Address,
121  const void *Decoder);
122 
123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
124  unsigned RegNo,
125  uint64_t Address,
126  const void *Decoder);
127 
128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
129  unsigned RegNo,
130  uint64_t Address,
131  const void *Decoder);
132 
133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
134  unsigned RegNo,
135  uint64_t Address,
136  const void *Decoder);
137 
138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
139  unsigned RegNo,
140  uint64_t Address,
141  const void *Decoder);
142 
143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
144  unsigned RegNo,
145  uint64_t Address,
146  const void *Decoder);
147 
148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
149  unsigned Insn,
150  uint64_t Address,
151  const void *Decoder);
152 
153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
154  unsigned RegNo,
155  uint64_t Address,
156  const void *Decoder);
157 
158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
159  unsigned RegNo,
160  uint64_t Address,
161  const void *Decoder);
162 
163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
164  unsigned RegNo,
165  uint64_t Address,
166  const void *Decoder);
167 
168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
169  unsigned RegNo,
170  uint64_t Address,
171  const void *Decoder);
172 
173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
174  unsigned RegNo,
175  uint64_t Address,
176  const void *Decoder);
177 
178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
179  unsigned RegNo,
180  uint64_t Address,
181  const void *Decoder);
182 
183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
184  unsigned RegNo,
185  uint64_t Address,
186  const void *Decoder);
187 
188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
189  unsigned RegNo,
190  uint64_t Address,
191  const void *Decoder);
192 
193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
194  unsigned RegNo,
195  uint64_t Address,
196  const void *Decoder);
197 
198 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
199  unsigned Offset,
200  uint64_t Address,
201  const void *Decoder);
202 
203 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
204  unsigned Insn,
205  uint64_t Address,
206  const void *Decoder);
207 
208 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
209 // shifted left by 1 bit.
210 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
211  unsigned Offset,
212  uint64_t Address,
213  const void *Decoder);
214 
215 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
216 // shifted left by 1 bit.
217 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
218  unsigned Insn,
219  uint64_t Address,
220  const void *Decoder);
221 
222 static DecodeStatus DecodeMem(MCInst &Inst,
223  unsigned Insn,
224  uint64_t Address,
225  const void *Decoder);
226 
227 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
228  uint64_t Address, const void *Decoder);
229 
230 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
231  unsigned Insn,
232  uint64_t Address,
233  const void *Decoder);
234 
235 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
236  unsigned Insn,
237  uint64_t Address,
238  const void *Decoder);
239 
240 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
241  uint64_t Address,
242  const void *Decoder);
243 
244 static DecodeStatus DecodeSimm16(MCInst &Inst,
245  unsigned Insn,
246  uint64_t Address,
247  const void *Decoder);
248 
249 // Decode the immediate field of an LSA instruction which
250 // is off by one.
251 static DecodeStatus DecodeLSAImm(MCInst &Inst,
252  unsigned Insn,
253  uint64_t Address,
254  const void *Decoder);
255 
256 static DecodeStatus DecodeInsSize(MCInst &Inst,
257  unsigned Insn,
258  uint64_t Address,
259  const void *Decoder);
260 
261 static DecodeStatus DecodeExtSize(MCInst &Inst,
262  unsigned Insn,
263  uint64_t Address,
264  const void *Decoder);
265 
266 namespace llvm {
267 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
268  TheMips64elTarget;
269 }
270 
271 static MCDisassembler *createMipsDisassembler(
272  const Target &T,
273  const MCSubtargetInfo &STI) {
274  return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
275 }
276 
277 static MCDisassembler *createMipselDisassembler(
278  const Target &T,
279  const MCSubtargetInfo &STI) {
280  return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
281 }
282 
283 static MCDisassembler *createMips64Disassembler(
284  const Target &T,
285  const MCSubtargetInfo &STI) {
286  return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
287 }
288 
289 static MCDisassembler *createMips64elDisassembler(
290  const Target &T,
291  const MCSubtargetInfo &STI) {
292  return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
293 }
294 
295 extern "C" void LLVMInitializeMipsDisassembler() {
296  // Register the disassembler.
297  TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
298  createMipsDisassembler);
299  TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
300  createMipselDisassembler);
301  TargetRegistry::RegisterMCDisassembler(TheMips64Target,
302  createMips64Disassembler);
303  TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
304  createMips64elDisassembler);
305 }
306 
307 
308 #include "MipsGenDisassemblerTables.inc"
309 
310  /// readInstruction - read four bytes from the MemoryObject
311  /// and return 32 bit word sorted according to the given endianess
312 static DecodeStatus readInstruction32(const MemoryObject &region,
313  uint64_t address,
314  uint64_t &size,
315  uint32_t &insn,
316  bool isBigEndian,
317  bool IsMicroMips) {
318  uint8_t Bytes[4];
319 
320  // We want to read exactly 4 Bytes of data.
321  if (region.readBytes(address, 4, Bytes) == -1) {
322  size = 0;
323  return MCDisassembler::Fail;
324  }
325 
326  if (isBigEndian) {
327  // Encoded as a big-endian 32-bit word in the stream.
328  insn = (Bytes[3] << 0) |
329  (Bytes[2] << 8) |
330  (Bytes[1] << 16) |
331  (Bytes[0] << 24);
332  }
333  else {
334  // Encoded as a small-endian 32-bit word in the stream.
335  // Little-endian byte ordering:
336  // mips32r2: 4 | 3 | 2 | 1
337  // microMIPS: 2 | 1 | 4 | 3
338  if (IsMicroMips) {
339  insn = (Bytes[2] << 0) |
340  (Bytes[3] << 8) |
341  (Bytes[0] << 16) |
342  (Bytes[1] << 24);
343  } else {
344  insn = (Bytes[0] << 0) |
345  (Bytes[1] << 8) |
346  (Bytes[2] << 16) |
347  (Bytes[3] << 24);
348  }
349  }
350 
351  return MCDisassembler::Success;
352 }
353 
354 DecodeStatus
355 MipsDisassembler::getInstruction(MCInst &instr,
356  uint64_t &Size,
357  const MemoryObject &Region,
358  uint64_t Address,
359  raw_ostream &vStream,
360  raw_ostream &cStream) const {
361  uint32_t Insn;
362 
363  DecodeStatus Result = readInstruction32(Region, Address, Size,
364  Insn, isBigEndian, IsMicroMips);
365  if (Result == MCDisassembler::Fail)
366  return MCDisassembler::Fail;
367 
368  if (IsMicroMips) {
369  // Calling the auto-generated decoder function.
370  Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
371  this, STI);
372  if (Result != MCDisassembler::Fail) {
373  Size = 4;
374  return Result;
375  }
376  return MCDisassembler::Fail;
377  }
378 
379  // Calling the auto-generated decoder function.
380  Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
381  this, STI);
382  if (Result != MCDisassembler::Fail) {
383  Size = 4;
384  return Result;
385  }
386 
387  return MCDisassembler::Fail;
388 }
389 
390 DecodeStatus
391 Mips64Disassembler::getInstruction(MCInst &instr,
392  uint64_t &Size,
393  const MemoryObject &Region,
394  uint64_t Address,
395  raw_ostream &vStream,
396  raw_ostream &cStream) const {
397  uint32_t Insn;
398 
399  DecodeStatus Result = readInstruction32(Region, Address, Size,
400  Insn, isBigEndian, false);
401  if (Result == MCDisassembler::Fail)
402  return MCDisassembler::Fail;
403 
404  // Calling the auto-generated decoder function.
405  Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
406  this, STI);
407  if (Result != MCDisassembler::Fail) {
408  Size = 4;
409  return Result;
410  }
411  // If we fail to decode in Mips64 decoder space we can try in Mips32
412  Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
413  this, STI);
414  if (Result != MCDisassembler::Fail) {
415  Size = 4;
416  return Result;
417  }
418 
419  return MCDisassembler::Fail;
420 }
421 
422 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
423  const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
424  return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
425 }
426 
427 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
428  unsigned RegNo,
429  uint64_t Address,
430  const void *Decoder) {
431 
432  return MCDisassembler::Fail;
433 
434 }
435 
436 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
437  unsigned RegNo,
438  uint64_t Address,
439  const void *Decoder) {
440 
441  if (RegNo > 31)
442  return MCDisassembler::Fail;
443 
444  unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
445  Inst.addOperand(MCOperand::CreateReg(Reg));
446  return MCDisassembler::Success;
447 }
448 
449 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
450  unsigned RegNo,
451  uint64_t Address,
452  const void *Decoder) {
453  if (RegNo > 31)
454  return MCDisassembler::Fail;
455  unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
456  Inst.addOperand(MCOperand::CreateReg(Reg));
457  return MCDisassembler::Success;
458 }
459 
460 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
461  unsigned RegNo,
462  uint64_t Address,
463  const void *Decoder) {
464  if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
465  return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
466 
467  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
468 }
469 
470 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
471  unsigned RegNo,
472  uint64_t Address,
473  const void *Decoder) {
474  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
475 }
476 
477 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
478  unsigned RegNo,
479  uint64_t Address,
480  const void *Decoder) {
481  if (RegNo > 31)
482  return MCDisassembler::Fail;
483 
484  unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
485  Inst.addOperand(MCOperand::CreateReg(Reg));
486  return MCDisassembler::Success;
487 }
488 
489 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
490  unsigned RegNo,
491  uint64_t Address,
492  const void *Decoder) {
493  if (RegNo > 31)
494  return MCDisassembler::Fail;
495 
496  unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
497  Inst.addOperand(MCOperand::CreateReg(Reg));
498  return MCDisassembler::Success;
499 }
500 
501 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
502  unsigned RegNo,
503  uint64_t Address,
504  const void *Decoder) {
505  if (RegNo > 31)
506  return MCDisassembler::Fail;
507 
508  unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
509  Inst.addOperand(MCOperand::CreateReg(Reg));
510  return MCDisassembler::Success;
511 }
512 
513 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
514  unsigned RegNo,
515  uint64_t Address,
516  const void *Decoder) {
517  if (RegNo > 31)
518  return MCDisassembler::Fail;
519  unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
520  Inst.addOperand(MCOperand::CreateReg(Reg));
521  return MCDisassembler::Success;
522 }
523 
524 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
525  unsigned RegNo,
526  uint64_t Address,
527  const void *Decoder) {
528  if (RegNo > 7)
529  return MCDisassembler::Fail;
530  unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
531  Inst.addOperand(MCOperand::CreateReg(Reg));
532  return MCDisassembler::Success;
533 }
534 
535 static DecodeStatus DecodeMem(MCInst &Inst,
536  unsigned Insn,
537  uint64_t Address,
538  const void *Decoder) {
539  int Offset = SignExtend32<16>(Insn & 0xffff);
540  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
541  unsigned Base = fieldFromInstruction(Insn, 21, 5);
542 
543  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
544  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
545 
546  if(Inst.getOpcode() == Mips::SC){
547  Inst.addOperand(MCOperand::CreateReg(Reg));
548  }
549 
550  Inst.addOperand(MCOperand::CreateReg(Reg));
551  Inst.addOperand(MCOperand::CreateReg(Base));
552  Inst.addOperand(MCOperand::CreateImm(Offset));
553 
554  return MCDisassembler::Success;
555 }
556 
557 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
558  uint64_t Address, const void *Decoder) {
559  int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
560  unsigned Reg = fieldFromInstruction(Insn, 6, 5);
561  unsigned Base = fieldFromInstruction(Insn, 11, 5);
562 
563  Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
564  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
565 
566  Inst.addOperand(MCOperand::CreateReg(Reg));
567  Inst.addOperand(MCOperand::CreateReg(Base));
568  Inst.addOperand(MCOperand::CreateImm(Offset));
569 
570  return MCDisassembler::Success;
571 }
572 
573 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
574  unsigned Insn,
575  uint64_t Address,
576  const void *Decoder) {
577  int Offset = SignExtend32<12>(Insn & 0x0fff);
578  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
579  unsigned Base = fieldFromInstruction(Insn, 16, 5);
580 
581  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
582  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
583 
584  Inst.addOperand(MCOperand::CreateReg(Reg));
585  Inst.addOperand(MCOperand::CreateReg(Base));
586  Inst.addOperand(MCOperand::CreateImm(Offset));
587 
588  return MCDisassembler::Success;
589 }
590 
591 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
592  unsigned Insn,
593  uint64_t Address,
594  const void *Decoder) {
595  int Offset = SignExtend32<16>(Insn & 0xffff);
596  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
597  unsigned Base = fieldFromInstruction(Insn, 16, 5);
598 
599  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
600  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
601 
602  Inst.addOperand(MCOperand::CreateReg(Reg));
603  Inst.addOperand(MCOperand::CreateReg(Base));
604  Inst.addOperand(MCOperand::CreateImm(Offset));
605 
606  return MCDisassembler::Success;
607 }
608 
609 static DecodeStatus DecodeFMem(MCInst &Inst,
610  unsigned Insn,
611  uint64_t Address,
612  const void *Decoder) {
613  int Offset = SignExtend32<16>(Insn & 0xffff);
614  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
615  unsigned Base = fieldFromInstruction(Insn, 21, 5);
616 
617  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
618  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
619 
620  Inst.addOperand(MCOperand::CreateReg(Reg));
621  Inst.addOperand(MCOperand::CreateReg(Base));
622  Inst.addOperand(MCOperand::CreateImm(Offset));
623 
624  return MCDisassembler::Success;
625 }
626 
627 
628 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
629  unsigned RegNo,
630  uint64_t Address,
631  const void *Decoder) {
632  // Currently only hardware register 29 is supported.
633  if (RegNo != 29)
634  return MCDisassembler::Fail;
635  Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
636  return MCDisassembler::Success;
637 }
638 
639 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
640  unsigned RegNo,
641  uint64_t Address,
642  const void *Decoder) {
643  if (RegNo > 30 || RegNo %2)
644  return MCDisassembler::Fail;
645 
646  ;
647  unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
648  Inst.addOperand(MCOperand::CreateReg(Reg));
649  return MCDisassembler::Success;
650 }
651 
652 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
653  unsigned RegNo,
654  uint64_t Address,
655  const void *Decoder) {
656  if (RegNo >= 4)
657  return MCDisassembler::Fail;
658 
659  unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
660  Inst.addOperand(MCOperand::CreateReg(Reg));
661  return MCDisassembler::Success;
662 }
663 
664 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
665  unsigned RegNo,
666  uint64_t Address,
667  const void *Decoder) {
668  if (RegNo >= 4)
669  return MCDisassembler::Fail;
670 
671  unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
672  Inst.addOperand(MCOperand::CreateReg(Reg));
673  return MCDisassembler::Success;
674 }
675 
676 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
677  unsigned RegNo,
678  uint64_t Address,
679  const void *Decoder) {
680  if (RegNo >= 4)
681  return MCDisassembler::Fail;
682 
683  unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
684  Inst.addOperand(MCOperand::CreateReg(Reg));
685  return MCDisassembler::Success;
686 }
687 
688 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
689  unsigned RegNo,
690  uint64_t Address,
691  const void *Decoder) {
692  if (RegNo > 31)
693  return MCDisassembler::Fail;
694 
695  unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
696  Inst.addOperand(MCOperand::CreateReg(Reg));
697  return MCDisassembler::Success;
698 }
699 
700 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
701  unsigned RegNo,
702  uint64_t Address,
703  const void *Decoder) {
704  if (RegNo > 31)
705  return MCDisassembler::Fail;
706 
707  unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
708  Inst.addOperand(MCOperand::CreateReg(Reg));
709  return MCDisassembler::Success;
710 }
711 
712 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
713  unsigned RegNo,
714  uint64_t Address,
715  const void *Decoder) {
716  if (RegNo > 31)
717  return MCDisassembler::Fail;
718 
719  unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
720  Inst.addOperand(MCOperand::CreateReg(Reg));
721  return MCDisassembler::Success;
722 }
723 
724 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
725  unsigned RegNo,
726  uint64_t Address,
727  const void *Decoder) {
728  if (RegNo > 31)
729  return MCDisassembler::Fail;
730 
731  unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
732  Inst.addOperand(MCOperand::CreateReg(Reg));
733  return MCDisassembler::Success;
734 }
735 
736 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
737  unsigned RegNo,
738  uint64_t Address,
739  const void *Decoder) {
740  if (RegNo > 7)
741  return MCDisassembler::Fail;
742 
743  unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
744  Inst.addOperand(MCOperand::CreateReg(Reg));
745  return MCDisassembler::Success;
746 }
747 
748 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
749  unsigned Offset,
750  uint64_t Address,
751  const void *Decoder) {
752  unsigned BranchOffset = Offset & 0xffff;
753  BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
754  Inst.addOperand(MCOperand::CreateImm(BranchOffset));
755  return MCDisassembler::Success;
756 }
757 
758 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
759  unsigned Insn,
760  uint64_t Address,
761  const void *Decoder) {
762 
763  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
764  Inst.addOperand(MCOperand::CreateImm(JumpOffset));
765  return MCDisassembler::Success;
766 }
767 
768 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
769  unsigned Offset,
770  uint64_t Address,
771  const void *Decoder) {
772  unsigned BranchOffset = Offset & 0xffff;
773  BranchOffset = SignExtend32<18>(BranchOffset << 1);
774  Inst.addOperand(MCOperand::CreateImm(BranchOffset));
775  return MCDisassembler::Success;
776 }
777 
778 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
779  unsigned Insn,
780  uint64_t Address,
781  const void *Decoder) {
782  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
783  Inst.addOperand(MCOperand::CreateImm(JumpOffset));
784  return MCDisassembler::Success;
785 }
786 
787 static DecodeStatus DecodeSimm16(MCInst &Inst,
788  unsigned Insn,
789  uint64_t Address,
790  const void *Decoder) {
791  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
792  return MCDisassembler::Success;
793 }
794 
795 static DecodeStatus DecodeLSAImm(MCInst &Inst,
796  unsigned Insn,
797  uint64_t Address,
798  const void *Decoder) {
799  // We add one to the immediate field as it was encoded as 'imm - 1'.
800  Inst.addOperand(MCOperand::CreateImm(Insn + 1));
801  return MCDisassembler::Success;
802 }
803 
804 static DecodeStatus DecodeInsSize(MCInst &Inst,
805  unsigned Insn,
806  uint64_t Address,
807  const void *Decoder) {
808  // First we need to grab the pos(lsb) from MCInst.
809  int Pos = Inst.getOperand(2).getImm();
810  int Size = (int) Insn - Pos + 1;
811  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
812  return MCDisassembler::Success;
813 }
814 
815 static DecodeStatus DecodeExtSize(MCInst &Inst,
816  unsigned Insn,
817  uint64_t Address,
818  const void *Decoder) {
819  int Size = (int) Insn + 1;
820  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
821  return MCDisassembler::Success;
822 }
createMips64elDisassembler
static MCDisassembler * createMips64elDisassembler(const Target &T, const MCSubtargetInfo &STI)
Definition: MipsDisassembler.cpp:289
DecodeJumpTargetMM
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:778
DecodeSimm16
static DecodeStatus DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:787
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const MCRegisterDesc & get(unsigned RegNo) const
Provide a get method, equivalent to [], but more useful with a pointer to this object.
Definition: MCRegisterInfo.h:322
createMipselDisassembler
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI)
Definition: MipsDisassembler.cpp:277
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static MCOperand CreateReg(unsigned Reg)
Definition: MCInst.h:111
DecodeCPU16RegsRegisterClass
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:427
DecodeBranchTarget
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:748
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static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:436
DecodeInsSize
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:804
DecodeBranchTargetMM
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:768
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static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:639
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static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:524
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static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
Definition: TargetRegistry.h:727
readInstruction32
static DecodeStatus readInstruction32(const MemoryObject &region, uint64_t address, uint64_t &size, uint32_t &insn, bool isBigEndian, bool IsMicroMips)
Definition: MipsDisassembler.cpp:312
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static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:557
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static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:449
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virtual int readBytes(uint64_t address, uint64_t size, uint8_t *buf) const
Definition: MemoryObject.cpp:16
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Definition: MipsDisassembler.cpp:609
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Definition: MipsDisassembler.cpp:676
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static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:724
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static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:573
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Target TheMips64elTarget
Definition: MipsMCTargetDesc.h:34
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static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:628
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Target TheMips64Target
Definition: MipsMCTargetDesc.h:33
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static DecodeStatus DecodeExtSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:815
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A single entry single exit Region.
Definition: RegionInfo.h:202
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static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:477
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void LLVMInitializeMipsDisassembler()
Definition: MipsDisassembler.cpp:295
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static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:501
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static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:460
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Definition: MipsDisassembler.cpp:271
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uint64_t getFeatureBits() const
Definition: MCSubtargetInfo.h:67
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Definition: MipsDisassembler.cpp:283
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static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:688
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Definition: MipsDisassembler.cpp:535
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Definition: MipsDisassembler.cpp:652
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unsigned getOpcode() const
Definition: MCInst.h:158
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Definition: MipsDisassembler.cpp:422
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int64_t getImm() const
Definition: MCInst.h:74
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static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:489
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MCDisassembler::DecodeStatus DecodeStatus
Definition: MipsDisassembler.cpp:27
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Definition: MipsDisassembler.cpp:513
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static DecodeStatus DecodeLSAImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:795
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static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
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static MCOperand CreateImm(int64_t Val)
Definition: MCInst.h:117
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MCRegisterInfo * createMCRegInfo(StringRef Triple) const
Definition: TargetRegistry.h:314
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Definition: MipsMCTargetDesc.h:32
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Definition: MipsDisassembler.cpp:664
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Definition: MipsDisassembler.cpp:758
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Definition: raw_ostream.h:31
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void addOperand(const MCOperand &Op)
Definition: MCInst.h:167
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Definition: MipsDisassembler.cpp:736
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const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:163
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Definition: MipsMCTargetDesc.h:29
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Definition: MipsDisassembler.cpp:591
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Definition: X86DisassemblerDecoder.c:1712

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