29 Subtarget(TT, CPU, FS),
30 DL(
"e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
31 "i16:16:32-i32:32:32-i64:32:32-n32"),
33 FrameLowering(Subtarget),
47 return getTM<XCoreTargetMachine>();
50 virtual bool addPreISel();
51 virtual bool addInstSelector();
56 return new XCorePassConfig(
this, PM);
59 bool XCorePassConfig::addPreISel() {
64 bool XCorePassConfig::addInstSelector() {
void LLVMInitializeXCoreTarget()
ImmutablePass * createBasicTargetTransformInfoPass(const TargetMachine *TM)
Create a basic TargetTransformInfo analysis pass.
ModulePass * createXCoreLowerThreadLocalPass()
XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
FunctionPass * createXCoreISelDag(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel)
ImmutablePass * createXCoreTargetTransformInfoPass(const XCoreTargetMachine *TM)
virtual void addAnalysisPasses(PassManagerBase &PM)
Register analysis passes for this target with a pass manager.
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
static RegisterPass< NVPTXAllocaHoisting > X("alloca-hoisting","Hoisting alloca instructions in non-entry ""blocks to the entry block")