LLVM API Documentation
This is the complete list of members for llvm::R600InstrInfo, including all inherited members.
| addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const | llvm::R600InstrInfo | |
| ALU_VEC_012_SCL_210 enum value | llvm::R600InstrInfo | |
| ALU_VEC_021_SCL_122 enum value | llvm::R600InstrInfo | |
| ALU_VEC_102_SCL_221 enum value | llvm::R600InstrInfo | |
| ALU_VEC_120_SCL_212 enum value | llvm::R600InstrInfo | |
| ALU_VEC_201 enum value | llvm::R600InstrInfo | |
| ALU_VEC_210 enum value | llvm::R600InstrInfo | |
| AMDGPUInstrInfo(TargetMachine &tm) | llvm::AMDGPUInstrInfo | explicit |
| AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const | llvm::R600InstrInfo | |
| BankSwizzle enum name | llvm::R600InstrInfo | |
| buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const | llvm::R600InstrInfo | |
| buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const | llvm::R600InstrInfo | virtual |
| buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const | llvm::R600InstrInfo | virtual |
| buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const | llvm::R600InstrInfo | |
| buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const | llvm::R600InstrInfo | virtual |
| buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const | llvm::R600InstrInfo | |
| calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const | llvm::R600InstrInfo | virtual |
| canBeConsideredALU(const MachineInstr *MI) const | llvm::R600InstrInfo | |
| canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops) const | llvm::AMDGPUInstrInfo | |
| clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const | llvm::R600InstrInfo | |
| convertToISA(MachineInstr &MI, MachineFunction &MF, DebugLoc DL) const | llvm::AMDGPUInstrInfo | virtual |
| convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const | llvm::AMDGPUInstrInfo | |
| copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const | llvm::R600InstrInfo | virtual |
| CreateTargetScheduleState(const TargetMachine *TM, const ScheduleDAG *DAG) const | llvm::R600InstrInfo | |
| definesAddressRegister(MachineInstr *MI) const | llvm::R600InstrInfo | |
| DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const | llvm::R600InstrInfo | |
| expandPostRAPseudo(MachineBasicBlock::iterator MI) const | llvm::AMDGPUInstrInfo | virtual |
| FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const | llvm::R600InstrInfo | |
| fitsConstReadLimitations(const std::vector< MachineInstr * > &) const | llvm::R600InstrInfo | |
| fitsConstReadLimitations(const std::vector< unsigned > &) const | llvm::R600InstrInfo | |
| fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const | llvm::R600InstrInfo | |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const | llvm::AMDGPUInstrInfo | protected |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const | llvm::AMDGPUInstrInfo | protected |
| getFlagOp(MachineInstr *MI, unsigned SrcIdx=0, unsigned Flag=0) const | llvm::R600InstrInfo | |
| getIEQOpcode() const | llvm::R600InstrInfo | virtual |
| getIndirectAddrRegClass() const | llvm::R600InstrInfo | virtual |
| getIndirectIndexBegin(const MachineFunction &MF) const | llvm::AMDGPUInstrInfo | protectedvirtual |
| getIndirectIndexEnd(const MachineFunction &MF) const | llvm::AMDGPUInstrInfo | protectedvirtual |
| getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=0) const | llvm::R600InstrInfo | |
| getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) const | llvm::R600InstrInfo | inlinevirtual |
| getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const | llvm::AMDGPUInstrInfo | |
| getMaxAlusPerClause() const | llvm::R600InstrInfo | |
| getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=0) const | llvm::AMDGPUInstrInfo | |
| getOperandIdx(const MachineInstr &MI, unsigned Op) const | llvm::R600InstrInfo | |
| getOperandIdx(unsigned Opcode, unsigned Op) const | llvm::R600InstrInfo | |
| getPredicationCost(const MachineInstr *) const | llvm::R600InstrInfo | |
| getRegisterInfo() const | llvm::R600InstrInfo | virtual |
| getSelIdx(unsigned Opcode, unsigned SrcIdx) const | llvm::R600InstrInfo | |
| getSrcIdx(unsigned Opcode, unsigned SrcNum) const | llvm::R600InstrInfo | |
| getSrcs(MachineInstr *MI) const | llvm::R600InstrInfo | |
| hasFlagOperand(const MachineInstr &MI) const | llvm::R600InstrInfo | |
| hasInstrModifiers(unsigned Opcode) const | llvm::R600InstrInfo | |
| hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const | llvm::AMDGPUInstrInfo | |
| hasStoreFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const | llvm::AMDGPUInstrInfo | |
| InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const | llvm::R600InstrInfo | |
| insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const | llvm::AMDGPUInstrInfo | |
| isAExtLoadInst(llvm::MachineInstr *MI) const | llvm::AMDGPUInstrInfo | |
| isALUInstr(unsigned Opcode) const | llvm::R600InstrInfo | |
| isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const | llvm::AMDGPUInstrInfo | |
| isCubeOp(unsigned opcode) const | llvm::R600InstrInfo | |
| isExport(unsigned Opcode) const | llvm::R600InstrInfo | |
| isExtLoadInst(llvm::MachineInstr *MI) const | llvm::AMDGPUInstrInfo | |
| isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const | llvm::R600InstrInfo | |
| isLDSInstr(unsigned Opcode) const | llvm::R600InstrInfo | |
| isLDSNoRetInstr(unsigned Opcode) const | llvm::R600InstrInfo | |
| isLDSRetInstr(unsigned Opcode) const | llvm::R600InstrInfo | |
| isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const | llvm::R600InstrInfo | |
| isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const | llvm::R600InstrInfo | |
| isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const | llvm::AMDGPUInstrInfo | |
| isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const | llvm::AMDGPUInstrInfo | |
| isLoadInst(llvm::MachineInstr *MI) const | llvm::AMDGPUInstrInfo | |
| isMov(unsigned Opcode) const | llvm::R600InstrInfo | virtual |
| isPlaceHolderOpcode(unsigned opcode) const | llvm::R600InstrInfo | |
| isPredicable(MachineInstr *MI) const | llvm::R600InstrInfo | |
| isPredicated(const MachineInstr *MI) const | llvm::R600InstrInfo | |
| isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, const BranchProbability &Probability) const | llvm::R600InstrInfo | |
| isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, unsigned ExtraPredCycles, const BranchProbability &Probability) const | llvm::R600InstrInfo | |
| isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, const BranchProbability &Probability) const | llvm::R600InstrInfo | |
| isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const | llvm::R600InstrInfo | |
| isReductionOp(unsigned opcode) const | llvm::R600InstrInfo | |
| isRegisterLoad(const MachineInstr &MI) const | llvm::AMDGPUInstrInfo | |
| isRegisterStore(const MachineInstr &MI) const | llvm::AMDGPUInstrInfo | |
| isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const | llvm::AMDGPUInstrInfo | |
| isSExtLoadInst(llvm::MachineInstr *MI) const | llvm::AMDGPUInstrInfo | |
| isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const | llvm::AMDGPUInstrInfo | |
| isStoreFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const | llvm::AMDGPUInstrInfo | |
| isStoreInst(llvm::MachineInstr *MI) const | llvm::AMDGPUInstrInfo | |
| isSWSExtLoadInst(llvm::MachineInstr *MI) const | llvm::AMDGPUInstrInfo | |
| isTransOnly(unsigned Opcode) const | llvm::R600InstrInfo | |
| isTransOnly(const MachineInstr *MI) const | llvm::R600InstrInfo | |
| isTrig(const MachineInstr &MI) const | llvm::R600InstrInfo | |
| isTruncStoreInst(llvm::MachineInstr *MI) const | llvm::AMDGPUInstrInfo | |
| isVector(const MachineInstr &MI) const | llvm::R600InstrInfo | |
| isVectorOnly(unsigned Opcode) const | llvm::R600InstrInfo | |
| isVectorOnly(const MachineInstr *MI) const | llvm::R600InstrInfo | |
| isZExtLoadInst(llvm::MachineInstr *MI) const | llvm::AMDGPUInstrInfo | |
| loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const | llvm::AMDGPUInstrInfo | |
| mustBeLastInClause(unsigned Opcode) const | llvm::R600InstrInfo | |
| PredicateInstruction(MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const | llvm::R600InstrInfo | |
| R600InstrInfo(AMDGPUTargetMachine &tm) | llvm::R600InstrInfo | explicit |
| readsLDSSrcReg(const MachineInstr *MI) const | llvm::R600InstrInfo | |
| RemoveBranch(MachineBasicBlock &MBB) const | llvm::R600InstrInfo | |
| reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const | llvm::R600InstrInfo | |
| ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const | llvm::R600InstrInfo | |
| setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const | llvm::R600InstrInfo | |
| shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const | llvm::AMDGPUInstrInfo | |
| storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const | llvm::AMDGPUInstrInfo | |
| SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const | llvm::R600InstrInfo | |
| TM | llvm::AMDGPUInstrInfo | protected |
| unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const | llvm::AMDGPUInstrInfo | |
| unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const | llvm::AMDGPUInstrInfo | |
| usesAddressRegister(MachineInstr *MI) const | llvm::R600InstrInfo | |
| usesTextureCache(unsigned Opcode) const | llvm::R600InstrInfo | |
| usesTextureCache(const MachineInstr *MI) const | llvm::R600InstrInfo | |
| usesVertexCache(unsigned Opcode) const | llvm::R600InstrInfo | |
| usesVertexCache(const MachineInstr *MI) const | llvm::R600InstrInfo |
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