llvm::SIInstrInfo Member List

This is the complete list of members for llvm::SIInstrInfo, including all inherited members.

AMDGPUInstrInfo(TargetMachine &tm)	llvm::AMDGPUInstrInfo	explicit
buildIndirectRead(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const	llvm::SIInstrInfo	virtual
buildIndirectWrite(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const	llvm::SIInstrInfo	virtual
buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const	llvm::SIInstrInfo	virtual
calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const	llvm::SIInstrInfo	virtual
canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops) const	llvm::AMDGPUInstrInfo
canReadVGPR(const MachineInstr &MI, unsigned OpNo) const	llvm::SIInstrInfo
commuteInstruction(MachineInstr *MI, bool NewMI=false) const	llvm::SIInstrInfo	virtual
commuteOpcode(unsigned Opcode) const	llvm::SIInstrInfo
convertToISA(MachineInstr &MI, MachineFunction &MF, DebugLoc DL) const	llvm::AMDGPUInstrInfo	virtual
convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const	llvm::AMDGPUInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const	llvm::SIInstrInfo	virtual
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const	llvm::AMDGPUInstrInfo
expandPostRAPseudo(MachineBasicBlock::iterator MI) const	llvm::AMDGPUInstrInfo	virtual
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const	llvm::AMDGPUInstrInfo	protected
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const	llvm::AMDGPUInstrInfo	protected
getIEQOpcode() const	llvm::SIInstrInfo	inlinevirtual
getIndirectAddrRegClass() const	llvm::SIInstrInfo	virtual
getIndirectIndexBegin(const MachineFunction &MF) const	llvm::AMDGPUInstrInfo	protectedvirtual
getIndirectIndexEnd(const MachineFunction &MF) const	llvm::AMDGPUInstrInfo	protectedvirtual
getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const	llvm::AMDGPUInstrInfo
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=0) const	llvm::AMDGPUInstrInfo
getOpRegClass(const MachineInstr &MI, unsigned OpNo) const	llvm::SIInstrInfo
getRegisterInfo() const	llvm::SIInstrInfo	virtual
getVALUOp(const MachineInstr &MI)	llvm::SIInstrInfo	static
hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const	llvm::AMDGPUInstrInfo
hasStoreFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const	llvm::AMDGPUInstrInfo
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const	llvm::AMDGPUInstrInfo
isAExtLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const	llvm::AMDGPUInstrInfo
isExtLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isInlineConstant(const MachineOperand &MO) const	llvm::SIInstrInfo
isLiteralConstant(const MachineOperand &MO) const	llvm::SIInstrInfo
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::AMDGPUInstrInfo
isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const	llvm::AMDGPUInstrInfo
isLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isMIMG(uint16_t Opcode) const	llvm::SIInstrInfo
isMov(unsigned Opcode) const	llvm::SIInstrInfo	virtual
isPredicable(MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isPredicated(const MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isRegisterLoad(const MachineInstr &MI) const	llvm::AMDGPUInstrInfo
isRegisterStore(const MachineInstr &MI) const	llvm::AMDGPUInstrInfo
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const	llvm::SIInstrInfo	virtual
isSALUInstr(const MachineInstr &MI) const	llvm::SIInstrInfo
isSALUOpSupportedOnVALU(const MachineInstr &MI) const	llvm::SIInstrInfo
isSExtLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isSMRD(uint16_t Opcode) const	llvm::SIInstrInfo
isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::AMDGPUInstrInfo
isStoreFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const	llvm::AMDGPUInstrInfo
isStoreInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isSWSExtLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isTruncStoreInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
isVOP1(uint16_t Opcode) const	llvm::SIInstrInfo
isVOP2(uint16_t Opcode) const	llvm::SIInstrInfo
isVOP3(uint16_t Opcode) const	llvm::SIInstrInfo
isVOPC(uint16_t Opcode) const	llvm::SIInstrInfo
isZExtLoadInst(llvm::MachineInstr *MI) const	llvm::AMDGPUInstrInfo
legalizeOperands(MachineInstr *MI) const	llvm::SIInstrInfo
legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const	llvm::SIInstrInfo
LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I, unsigned SavReg, unsigned IndexReg) const	llvm::SIInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::AMDGPUInstrInfo
moveToVALU(MachineInstr &MI) const	llvm::SIInstrInfo
reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const	llvm::SIInstrInfo
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const	llvm::AMDGPUInstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const	llvm::AMDGPUInstrInfo
SIInstrInfo(AMDGPUTargetMachine &tm)	llvm::SIInstrInfo	explicit
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::AMDGPUInstrInfo
SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const	llvm::AMDGPUInstrInfo
TM	llvm::AMDGPUInstrInfo	protected
unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::AMDGPUInstrInfo
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const	llvm::AMDGPUInstrInfo
verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const	llvm::SIInstrInfo	virtual