llvm::Thumb1InstrInfo Member List

This is the complete list of members for llvm::Thumb1InstrInfo, including all inherited members.

AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const	llvm::ARMBaseInstrInfo
AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const	llvm::ARMBaseInstrInfo	virtual
analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const	llvm::ARMBaseInstrInfo	virtual
analyzeSelect(const MachineInstr *MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const	llvm::ARMBaseInstrInfo	virtual
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const	llvm::ARMBaseInstrInfo	virtual
ARMBaseInstrInfo(const ARMSubtarget &STI)	llvm::ARMBaseInstrInfo	explicitprotected
breakPartialRegDependency(MachineBasicBlock::iterator, unsigned, const TargetRegisterInfo *TRI) const	llvm::ARMBaseInstrInfo
canCauseFpMLxStall(unsigned Opcode) const	llvm::ARMBaseInstrInfo	inline
commuteInstruction(MachineInstr *, bool=false) const	llvm::ARMBaseInstrInfo
convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const	llvm::ARMBaseInstrInfo	virtual
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const	llvm::Thumb1InstrInfo	virtual
CreateTargetHazardRecognizer(const TargetMachine *TM, const ScheduleDAG *DAG) const	llvm::ARMBaseInstrInfo
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const	llvm::ARMBaseInstrInfo
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const	llvm::ARMBaseInstrInfo	virtual
duplicate(MachineInstr *Orig, MachineFunction &MF) const	llvm::ARMBaseInstrInfo
expandPostRAPseudo(MachineBasicBlock::iterator MI) const	llvm::ARMBaseInstrInfo	virtual
FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const	llvm::ARMBaseInstrInfo	virtual
getExecutionDomain(const MachineInstr *MI) const	llvm::ARMBaseInstrInfo
GetInstSizeInBytes(const MachineInstr *MI) const	llvm::ARMBaseInstrInfo	virtual
getNoopForMachoTarget(MCInst &NopInst) const	llvm::Thumb1InstrInfo
getNumLDMAddresses(const MachineInstr *MI) const	llvm::ARMBaseInstrInfo
getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr *MI) const	llvm::ARMBaseInstrInfo	virtual
getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const	llvm::ARMBaseInstrInfo	virtual
getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const	llvm::ARMBaseInstrInfo	virtual
getPartialRegUpdateClearance(const MachineInstr *, unsigned, const TargetRegisterInfo *) const	llvm::ARMBaseInstrInfo
getPredicate(const MachineInstr *MI) const	llvm::ARMBaseInstrInfo	inline
getRegisterInfo() const	llvm::Thumb1InstrInfo	inlinevirtual
getSubtarget() const	llvm::ARMBaseInstrInfo	inline
getUnindexedOpcode(unsigned Opc) const	llvm::Thumb1InstrInfo	virtual
hasNOP() const	llvm::ARMBaseInstrInfo
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const	llvm::ARMBaseInstrInfo	virtual
isFpMLxInstruction(unsigned Opcode) const	llvm::ARMBaseInstrInfo	inline
isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const	llvm::ARMBaseInstrInfo
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::ARMBaseInstrInfo	virtual
isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const	llvm::ARMBaseInstrInfo	virtual
isPredicable(MachineInstr *MI) const	llvm::ARMBaseInstrInfo	virtual
isPredicated(const MachineInstr *MI) const	llvm::ARMBaseInstrInfo
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const	llvm::ARMBaseInstrInfo	inlinevirtual
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const	llvm::ARMBaseInstrInfo	virtual
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, const BranchProbability &Probability) const	llvm::ARMBaseInstrInfo	virtual
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const	llvm::ARMBaseInstrInfo	virtual
isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const	llvm::ARMBaseInstrInfo	virtual
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::ARMBaseInstrInfo	virtual
isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const	llvm::ARMBaseInstrInfo	virtual
isSwiftFastImmShift(const MachineInstr *MI) const	llvm::ARMBaseInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::Thumb1InstrInfo	virtual
optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const	llvm::ARMBaseInstrInfo	virtual
optimizeSelect(MachineInstr *MI, bool) const	llvm::ARMBaseInstrInfo	virtual
PredicateInstruction(MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const	llvm::ARMBaseInstrInfo	virtual
produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI) const	llvm::ARMBaseInstrInfo	virtual
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const	llvm::ARMBaseInstrInfo	virtual
RemoveBranch(MachineBasicBlock &MBB) const	llvm::ARMBaseInstrInfo	virtual
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const	llvm::ARMBaseInstrInfo	virtual
setExecutionDomain(MachineInstr *MI, unsigned Domain) const	llvm::ARMBaseInstrInfo
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const	llvm::ARMBaseInstrInfo	virtual
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::Thumb1InstrInfo	virtual
SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const	llvm::ARMBaseInstrInfo	virtual
Thumb1InstrInfo(const ARMSubtarget &STI)	llvm::Thumb1InstrInfo	explicit