#include <Thumb1InstrInfo.h>

Inheritance diagram for llvm::Thumb1InstrInfo:

Collaboration diagram for llvm::Thumb1InstrInfo:

Public Member Functions
	Thumb1InstrInfo (const ARMSubtarget &STI)

void	getNoopForMachoTarget (MCInst &NopInst) const
	getNoopForMachoTarget - Return the noop instruction to use for a noop. More...

unsigned	getUnindexedOpcode (unsigned Opc) const

const Thumb1RegisterInfo &	getRegisterInfo () const

void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const

void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI) const

void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI) const

Public Member Functions inherited from llvm::ARMBaseInstrInfo
bool	hasNOP () const

virtual MachineInstr *	convertToThreeAddress (MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const

const ARMSubtarget &	getSubtarget () const

ScheduleHazardRecognizer *	CreateTargetHazardRecognizer (const TargetMachine TM, const ScheduleDAG DAG) const

ScheduleHazardRecognizer *	CreateTargetPostRAHazardRecognizer (const InstrItineraryData II, const ScheduleDAG DAG) const

virtual bool	AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const

virtual unsigned	RemoveBranch (MachineBasicBlock &MBB) const

virtual unsigned	InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const

virtual bool	ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const

bool	isPredicated (const MachineInstr *MI) const

ARMCC::CondCodes	getPredicate (const MachineInstr *MI) const

virtual bool	PredicateInstruction (MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const

virtual bool	SubsumesPredicate (const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const

virtual bool	DefinesPredicate (MachineInstr *MI, std::vector< MachineOperand > &Pred) const

virtual bool	isPredicable (MachineInstr *MI) const

virtual unsigned	GetInstSizeInBytes (const MachineInstr *MI) const

virtual unsigned	isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const

virtual unsigned	isStoreToStackSlot (const MachineInstr *MI, int &FrameIndex) const

virtual unsigned	isLoadFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const

virtual unsigned	isStoreToStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const

virtual bool	expandPostRAPseudo (MachineBasicBlock::iterator MI) const

virtual void	reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const

MachineInstr *	duplicate (MachineInstr *Orig, MachineFunction &MF) const

MachineInstr *	commuteInstruction (MachineInstr *, bool=false) const
	commuteInstruction - Handle commutable instructions. More...

const MachineInstrBuilder &	AddDReg (MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const

virtual bool	produceSameValue (const MachineInstr MI0, const MachineInstr MI1, const MachineRegisterInfo *MRI) const

virtual bool	areLoadsFromSameBasePtr (SDNode Load1, SDNode Load2, int64_t &Offset1, int64_t &Offset2) const

virtual bool	shouldScheduleLoadsNear (SDNode Load1, SDNode Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const

virtual bool	isSchedulingBoundary (const MachineInstr MI, const MachineBasicBlock MBB, const MachineFunction &MF) const

virtual bool	isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const

virtual bool	isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, const BranchProbability &Probability) const

virtual bool	isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const

virtual bool	isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const

virtual bool	analyzeCompare (const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const

virtual bool	optimizeCompareInstr (MachineInstr CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo MRI) const

virtual bool	analyzeSelect (const MachineInstr *MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const

virtual MachineInstr *	optimizeSelect (MachineInstr *MI, bool) const

virtual bool	FoldImmediate (MachineInstr UseMI, MachineInstr DefMI, unsigned Reg, MachineRegisterInfo *MRI) const

virtual unsigned	getNumMicroOps (const InstrItineraryData ItinData, const MachineInstr MI) const

virtual int	getOperandLatency (const InstrItineraryData ItinData, const MachineInstr DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const

virtual int	getOperandLatency (const InstrItineraryData ItinData, SDNode DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const

std::pair< uint16_t, uint16_t >	getExecutionDomain (const MachineInstr *MI) const
	VFP/NEON execution domains. More...

void	setExecutionDomain (MachineInstr *MI, unsigned Domain) const

unsigned	getPartialRegUpdateClearance (const MachineInstr , unsigned, const TargetRegisterInfo ) const

void	breakPartialRegDependency (MachineBasicBlock::iterator, unsigned, const TargetRegisterInfo *TRI) const

unsigned	getNumLDMAddresses (const MachineInstr *MI) const
	Get the number of addresses by LDM or VLDM or zero for unknown. More...

bool	isFpMLxInstruction (unsigned Opcode) const

bool	isFpMLxInstruction (unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const

bool	canCauseFpMLxStall (unsigned Opcode) const

bool	isSwiftFastImmShift (const MachineInstr *MI) const

Additional Inherited Members
Protected Member Functions inherited from llvm::ARMBaseInstrInfo
	ARMBaseInstrInfo (const ARMSubtarget &STI)

Detailed Description

Definition at line 24 of file Thumb1InstrInfo.h.

Constructor & Destructor Documentation

Thumb1InstrInfo::Thumb1InstrInfo ( const ARMSubtarget & STI )

explicit

Definition at line 24 of file Thumb1InstrInfo.cpp.

Member Function Documentation

void Thumb1InstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		DebugLoc	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		bool	KillSrc
	)		const

virtual

Reimplemented from llvm::ARMBaseInstrInfo.

Definition at line 41 of file Thumb1InstrInfo.cpp.

References llvm::AddDefaultPred(), llvm::BuildMI(), and llvm::getKillRegState().

void Thumb1InstrInfo::getNoopForMachoTarget ( MCInst & NopInst ) const

getNoopForMachoTarget - Return the noop instruction to use for a noop.

Definition at line 29 of file Thumb1InstrInfo.cpp.

References llvm::MCInst::addOperand(), llvm::ARMCC::AL, llvm::MCOperand::CreateImm(), llvm::MCOperand::CreateReg(), and llvm::MCInst::setOpcode().

const Thumb1RegisterInfo& llvm::Thumb1InstrInfo::getRegisterInfo ( ) const

inlinevirtual

getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Implements llvm::ARMBaseInstrInfo.

Definition at line 40 of file Thumb1InstrInfo.h.

unsigned Thumb1InstrInfo::getUnindexedOpcode ( unsigned Opc ) const

virtual

Implements llvm::ARMBaseInstrInfo.

Definition at line 37 of file Thumb1InstrInfo.cpp.

void Thumb1InstrInfo::loadRegFromStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		unsigned	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const

virtual

Reimplemented from llvm::ARMBaseInstrInfo.

Definition at line 80 of file Thumb1InstrInfo.cpp.

References llvm::AddDefaultPred(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::isARMLowRegister(), llvm::TargetRegisterInfo::isPhysicalRegister(), and llvm::MachineMemOperand::MOLoad.

void Thumb1InstrInfo::storeRegToStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		unsigned	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const

virtual

Reimplemented from llvm::ARMBaseInstrInfo.

Definition at line 52 of file Thumb1InstrInfo.cpp.

References llvm::AddDefaultPred(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::isARMLowRegister(), llvm::TargetRegisterInfo::isPhysicalRegister(), and llvm::MachineMemOperand::MOStore.

The documentation for this class was generated from the following files:

Public Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation