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llvm::ARMBaseInstrInfo Class Referenceabstract

#include <ARMBaseInstrInfo.h>

Inheritance diagram for llvm::ARMBaseInstrInfo:
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Collaboration diagram for llvm::ARMBaseInstrInfo:
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Public Member Functions

bool hasNOP () const
 
virtual unsigned getUnindexedOpcode (unsigned Opc) const =0
 
virtual MachineInstrconvertToThreeAddress (MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const
 
virtual const ARMBaseRegisterInfogetRegisterInfo () const =0
 
const ARMSubtargetgetSubtarget () const
 
ScheduleHazardRecognizerCreateTargetHazardRecognizer (const TargetMachine *TM, const ScheduleDAG *DAG) const
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const
 
virtual bool AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
 
virtual unsigned RemoveBranch (MachineBasicBlock &MBB) const
 
virtual unsigned InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const
 
virtual bool ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const
 
bool isPredicated (const MachineInstr *MI) const
 
ARMCC::CondCodes getPredicate (const MachineInstr *MI) const
 
virtual bool PredicateInstruction (MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const
 
virtual bool SubsumesPredicate (const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const
 
virtual bool DefinesPredicate (MachineInstr *MI, std::vector< MachineOperand > &Pred) const
 
virtual bool isPredicable (MachineInstr *MI) const
 
virtual unsigned GetInstSizeInBytes (const MachineInstr *MI) const
 
virtual unsigned isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const
 
virtual unsigned isStoreToStackSlot (const MachineInstr *MI, int &FrameIndex) const
 
virtual unsigned isLoadFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const
 
virtual unsigned isStoreToStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const
 
virtual void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
 
virtual void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
 
virtual void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
 
virtual bool expandPostRAPseudo (MachineBasicBlock::iterator MI) const
 
virtual void reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const
 
MachineInstrduplicate (MachineInstr *Orig, MachineFunction &MF) const
 
MachineInstrcommuteInstruction (MachineInstr *, bool=false) const
 commuteInstruction - Handle commutable instructions. More...
 
const MachineInstrBuilderAddDReg (MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
 
virtual bool produceSameValue (const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI) const
 
virtual bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
 
virtual bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
 
virtual bool isSchedulingBoundary (const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
 
virtual bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const
 
virtual bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, const BranchProbability &Probability) const
 
virtual bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const
 
virtual bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
 
virtual bool analyzeCompare (const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const
 
virtual bool optimizeCompareInstr (MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const
 
virtual bool analyzeSelect (const MachineInstr *MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
 
virtual MachineInstroptimizeSelect (MachineInstr *MI, bool) const
 
virtual bool FoldImmediate (MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const
 
virtual unsigned getNumMicroOps (const InstrItineraryData *ItinData, const MachineInstr *MI) const
 
virtual int getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const
 
virtual int getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
 
std::pair< uint16_t, uint16_t > getExecutionDomain (const MachineInstr *MI) const
 VFP/NEON execution domains. More...
 
void setExecutionDomain (MachineInstr *MI, unsigned Domain) const
 
unsigned getPartialRegUpdateClearance (const MachineInstr *, unsigned, const TargetRegisterInfo *) const
 
void breakPartialRegDependency (MachineBasicBlock::iterator, unsigned, const TargetRegisterInfo *TRI) const
 
unsigned getNumLDMAddresses (const MachineInstr *MI) const
 Get the number of addresses by LDM or VLDM or zero for unknown. More...
 
bool isFpMLxInstruction (unsigned Opcode) const
 
bool isFpMLxInstruction (unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const
 
bool canCauseFpMLxStall (unsigned Opcode) const
 
bool isSwiftFastImmShift (const MachineInstr *MI) const
 

Protected Member Functions

 ARMBaseInstrInfo (const ARMSubtarget &STI)
 

Detailed Description

Definition at line 30 of file ARMBaseInstrInfo.h.

Constructor & Destructor Documentation

ARMBaseInstrInfo::ARMBaseInstrInfo ( const ARMSubtarget STI)
explicitprotected

Member Function Documentation

const MachineInstrBuilder & ARMBaseInstrInfo::AddDReg ( MachineInstrBuilder MIB,
unsigned  Reg,
unsigned  SubIdx,
unsigned  State,
const TargetRegisterInfo TRI 
) const
bool ARMBaseInstrInfo::AnalyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify = false 
) const
virtual
bool ARMBaseInstrInfo::analyzeCompare ( const MachineInstr MI,
unsigned SrcReg,
unsigned SrcReg2,
int &  CmpMask,
int &  CmpValue 
) const
virtual

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. Return true if the comparison instruction can be analyzed.

Definition at line 2102 of file ARMBaseInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

bool ARMBaseInstrInfo::analyzeSelect ( const MachineInstr MI,
SmallVectorImpl< MachineOperand > &  Cond,
unsigned TrueOp,
unsigned FalseOp,
bool Optimizable 
) const
virtual
bool ARMBaseInstrInfo::areLoadsFromSameBasePtr ( SDNode Load1,
SDNode Load2,
int64_t &  Offset1,
int64_t &  Offset2 
) const
virtual

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 1413 of file ARMBaseInstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::isMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().

void ARMBaseInstrInfo::breakPartialRegDependency ( MachineBasicBlock::iterator  MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
bool llvm::ARMBaseInstrInfo::canCauseFpMLxStall ( unsigned  Opcode) const
inline

canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.

Definition at line 314 of file ARMBaseInstrInfo.h.

References llvm::SmallSet< T, N, C >::count().

Referenced by llvm::ARMHazardRecognizer::getHazardType().

MachineInstr * ARMBaseInstrInfo::commuteInstruction ( MachineInstr MI,
bool  NewMI = false 
) const
MachineInstr * ARMBaseInstrInfo::convertToThreeAddress ( MachineFunction::iterator MFI,
MachineBasicBlock::iterator MBBI,
LiveVariables LV 
) const
virtual

Definition at line 122 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMII::AddrMode2, llvm::ARMII::AddrMode3, llvm::ARMII::AddrModeMask, llvm::LiveVariables::addVirtualRegisterDead(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::BuildMI(), EnableARM3Addr, llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getSORegOpc(), getUnindexedOpcode(), llvm::LiveVariables::getVarInfo(), llvm::ARMII::IndexModeMask, llvm::ARMII::IndexModePost, llvm::ARMII::IndexModePre, llvm::ARMII::IndexModeShift, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::LiveVariables::VarInfo::Kills, llvm_unreachable, llvm::MachineInstr::mayStore(), llvm::A64CC::MI, llvm::MachineInstr::readsRegister(), llvm::LiveVariables::VarInfo::removeKill(), llvm::MachineOperand::setIsDead(), llvm::ARM_AM::sub, and llvm::MCInstrDesc::TSFlags.

void ARMBaseInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
DebugLoc  DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
virtual
ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetHazardRecognizer ( const TargetMachine TM,
const ScheduleDAG DAG 
) const
ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAG DAG 
) const
bool ARMBaseInstrInfo::DefinesPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred 
) const
virtual
MachineInstr * ARMBaseInstrInfo::duplicate ( MachineInstr Orig,
MachineFunction MF 
) const
bool ARMBaseInstrInfo::expandPostRAPseudo ( MachineBasicBlock::iterator  MI) const
virtual
bool ARMBaseInstrInfo::FoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
unsigned  Reg,
MachineRegisterInfo MRI 
) const
virtual
std::pair< uint16_t, uint16_t > ARMBaseInstrInfo::getExecutionDomain ( const MachineInstr MI) const
unsigned ARMBaseInstrInfo::GetInstSizeInBytes ( const MachineInstr MI) const
virtual
unsigned ARMBaseInstrInfo::getNumLDMAddresses ( const MachineInstr MI) const

Get the number of addresses by LDM or VLDM or zero for unknown.

Definition at line 2784 of file ARMBaseInstrInfo.cpp.

References I, llvm::MachineInstr::memoperands_begin(), and llvm::MachineInstr::memoperands_end().

unsigned ARMBaseInstrInfo::getNumMicroOps ( const InstrItineraryData ItinData,
const MachineInstr MI 
) const
virtual
int ARMBaseInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
const MachineInstr DefMI,
unsigned  DefIdx,
const MachineInstr UseMI,
unsigned  UseIdx 
) const
virtual
int ARMBaseInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
SDNode DefNode,
unsigned  DefIdx,
SDNode UseNode,
unsigned  UseIdx 
) const
virtual
unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance ( const MachineInstr MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
ARMCC::CondCodes llvm::ARMBaseInstrInfo::getPredicate ( const MachineInstr MI) const
inline
virtual const ARMBaseRegisterInfo& llvm::ARMBaseInstrInfo::getRegisterInfo ( ) const
pure virtual
const ARMSubtarget& llvm::ARMBaseInstrInfo::getSubtarget ( ) const
inline

Definition at line 50 of file ARMBaseInstrInfo.h.

Referenced by llvm::ARMHazardRecognizer::getHazardType(), and isPredicable().

virtual unsigned llvm::ARMBaseInstrInfo::getUnindexedOpcode ( unsigned  Opc) const
pure virtual
bool ARMBaseInstrInfo::hasNOP ( ) const

Definition at line 4295 of file ARMBaseInstrInfo.cpp.

Referenced by llvm::ARMInstrInfo::getNoopForMachoTarget().

unsigned ARMBaseInstrInfo::InsertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
const SmallVectorImpl< MachineOperand > &  Cond,
DebugLoc  DL 
) const
virtual
bool llvm::ARMBaseInstrInfo::isFpMLxInstruction ( unsigned  Opcode) const
inline

isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.

Definition at line 300 of file ARMBaseInstrInfo.h.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::count().

Referenced by llvm::ARMHazardRecognizer::getHazardType().

bool ARMBaseInstrInfo::isFpMLxInstruction ( unsigned  Opcode,
unsigned MulOpc,
unsigned AddSubOpc,
bool NegAcc,
bool HasLane 
) const

isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to. Return true for 'HasLane' for the MLX instructions with an extra lane operand.

Definition at line 3868 of file ARMBaseInstrInfo.cpp.

References ARM_MLxEntry::AddSubOpc, ARM_MLxTable, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::find(), ARM_MLxEntry::HasLane, ARM_MLxEntry::MulOpc, and ARM_MLxEntry::NegAcc.

unsigned ARMBaseInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
virtual
unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE ( const MachineInstr MI,
int &  FrameIndex 
) const
virtual

Definition at line 1159 of file ARMBaseInstrInfo.cpp.

References llvm::NVPTXISD::Dummy, and llvm::MachineInstr::mayLoad().

bool ARMBaseInstrInfo::isPredicable ( MachineInstr MI) const
virtual
bool ARMBaseInstrInfo::isPredicated ( const MachineInstr MI) const
virtual bool llvm::ARMBaseInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
const BranchProbability Probability 
) const
inlinevirtual

Definition at line 180 of file ARMBaseInstrInfo.h.

bool ARMBaseInstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
const BranchProbability Probability 
) const
virtual
bool ARMBaseInstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumT,
unsigned  ExtraT,
MachineBasicBlock FMBB,
unsigned  NumF,
unsigned  ExtraF,
const BranchProbability Probability 
) const
virtual
bool ARMBaseInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock TMBB,
MachineBasicBlock FMBB 
) const
virtual

Definition at line 1608 of file ARMBaseInstrInfo.cpp.

References llvm::ARMSubtarget::isSwift().

bool ARMBaseInstrInfo::isSchedulingBoundary ( const MachineInstr MI,
const MachineBasicBlock MBB,
const MachineFunction MF 
) const
virtual
unsigned ARMBaseInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
virtual
unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE ( const MachineInstr MI,
int &  FrameIndex 
) const
virtual

Definition at line 968 of file ARMBaseInstrInfo.cpp.

References llvm::NVPTXISD::Dummy, and llvm::MachineInstr::mayStore().

bool ARMBaseInstrInfo::isSwiftFastImmShift ( const MachineInstr MI) const

Returns true if the instruction has a shift by immediate that can be executed in one cycle less.

Definition at line 4299 of file ARMBaseInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::ARM_AM::getSORegOffset(), llvm::ARM_AM::getSORegShOp(), llvm::ARM_AM::lsl, and llvm::ARM_AM::lsr.

void ARMBaseInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
virtual
bool ARMBaseInstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
unsigned  SrcReg,
unsigned  SrcReg2,
int  CmpMask,
int  CmpValue,
const MachineRegisterInfo MRI 
) const
virtual

optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register; Remove a redundant Compare instruction if an earlier instruction can set the flags in the same way as Compare. E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the condition code of instructions which use the flags.

Definition at line 2216 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::ARMCC::GE, llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::ARMCC::GT, I, llvm::MachineOperand::isDef(), isPredicated(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), isSuitableForMask(), llvm::ARMCC::LE, llvm::ARMCC::LT, llvm::A64CC::MI, llvm::MachineInstr::modifiesRegister(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::readsRegister(), llvm::MachineOperand::setIsDef(), llvm::MachineOperand::setReg(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), llvm::MachineRegisterInfo::use_begin(), llvm::MachineRegisterInfo::use_end(), llvm::ARMCC::VC, and llvm::ARMCC::VS.

MachineInstr * ARMBaseInstrInfo::optimizeSelect ( MachineInstr MI,
bool  PreferFalse 
) const
virtual
bool ARMBaseInstrInfo::PredicateInstruction ( MachineInstr MI,
const SmallVectorImpl< MachineOperand > &  Pred 
) const
virtual
bool ARMBaseInstrInfo::produceSameValue ( const MachineInstr MI0,
const MachineInstr MI1,
const MachineRegisterInfo MRI 
) const
virtual
void ARMBaseInstrInfo::reMaterialize ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
unsigned  SubIdx,
const MachineInstr Orig,
const TargetRegisterInfo TRI 
) const
virtual
unsigned ARMBaseInstrInfo::RemoveBranch ( MachineBasicBlock MBB) const
virtual
bool ARMBaseInstrInfo::ReverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
virtual

Definition at line 431 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::getOppositeCondition().

void ARMBaseInstrInfo::setExecutionDomain ( MachineInstr MI,
unsigned  Domain 
) const
bool ARMBaseInstrInfo::shouldScheduleLoadsNear ( SDNode Load1,
SDNode Load2,
int64_t  Offset1,
int64_t  Offset2,
unsigned  NumLoads 
) const
virtual

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 1494 of file ARMBaseInstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().

void ARMBaseInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
virtual
bool ARMBaseInstrInfo::SubsumesPredicate ( const SmallVectorImpl< MachineOperand > &  Pred1,
const SmallVectorImpl< MachineOperand > &  Pred2 
) const
virtual

The documentation for this class was generated from the following files: