LLVM API Documentation
#include <ARMBaseInstrInfo.h>
Protected Member Functions | |
ARMBaseInstrInfo (const ARMSubtarget &STI) | |
Definition at line 30 of file ARMBaseInstrInfo.h.
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Definition at line 90 of file ARMBaseInstrInfo.cpp.
References ARM_MLxTable, llvm::array_lengthof(), llvm::SmallSet< T, N, C >::insert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::insert(), and ARM_MLxEntry::MLxOpc.
const MachineInstrBuilder & ARMBaseInstrInfo::AddDReg | ( | MachineInstrBuilder & | MIB, |
unsigned | Reg, | ||
unsigned | SubIdx, | ||
unsigned | State, | ||
const TargetRegisterInfo * | TRI | ||
) | const |
Definition at line 772 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MCRegisterInfo::getSubReg(), and llvm::TargetRegisterInfo::isPhysicalRegister().
Referenced by llvm::Thumb2InstrInfo::loadRegFromStackSlot(), loadRegFromStackSlot(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), and storeRegToStackSlot().
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Definition at line 272 of file ARMBaseInstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::SmallVectorImpl< T >::clear(), llvm::SmallVectorBase::empty(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::isJumpTableBranchOpcode(), isPredicated(), llvm::isUncondBranchOpcode(), llvm::next(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. Return true if the comparison instruction can be analyzed.
Definition at line 2102 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
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Definition at line 1704 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.
FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.
Definition at line 1413 of file ARMBaseInstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::isMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().
void ARMBaseInstrInfo::breakPartialRegDependency | ( | MachineBasicBlock::iterator | MI, |
unsigned | OpNum, | ||
const TargetRegisterInfo * | TRI | ||
) | const |
Definition at line 4261 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addRegisterKilled(), llvm::BuildMI(), llvm::MachineOperand::getReg(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MCRegisterInfo::isSuperRegister(), and llvm::A64CC::MI.
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.
Definition at line 314 of file ARMBaseInstrInfo.h.
References llvm::SmallSet< T, N, C >::count().
Referenced by llvm::ARMHazardRecognizer::getHazardType().
MachineInstr * ARMBaseInstrInfo::commuteInstruction | ( | MachineInstr * | MI, |
bool | NewMI = false |
||
) | const |
commuteInstruction - Handle commutable instructions.
Definition at line 1644 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::TargetInstrInfo::commuteInstruction(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::getInstrPredicate(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), and llvm::A64CC::MI.
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Definition at line 122 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMII::AddrMode2, llvm::ARMII::AddrMode3, llvm::ARMII::AddrModeMask, llvm::LiveVariables::addVirtualRegisterDead(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::BuildMI(), EnableARM3Addr, llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getSORegOpc(), getUnindexedOpcode(), llvm::LiveVariables::getVarInfo(), llvm::ARMII::IndexModeMask, llvm::ARMII::IndexModePost, llvm::ARMII::IndexModePre, llvm::ARMII::IndexModeShift, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::LiveVariables::VarInfo::Kills, llvm_unreachable, llvm::MachineInstr::mayStore(), llvm::A64CC::MI, llvm::MachineInstr::readsRegister(), llvm::LiveVariables::VarInfo::removeKill(), llvm::MachineOperand::setIsDead(), llvm::ARM_AM::sub, and llvm::MCInstrDesc::TSFlags.
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Reimplemented in llvm::Thumb2InstrInfo, and llvm::Thumb1InstrInfo.
Definition at line 650 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultCC(), llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::BuildMI(), llvm::SmallSet< T, N, C >::count(), llvm::getKillRegState(), getRegisterInfo(), llvm::MCRegisterInfo::getSubReg(), llvm::SmallSet< T, N, C >::insert(), llvm::ARMSubtarget::isThumb2(), and llvm::TargetRegisterInfo::regsOverlap().
Referenced by llvm::Thumb2InstrInfo::copyPhysReg().
ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetHazardRecognizer | ( | const TargetMachine * | TM, |
const ScheduleDAG * | DAG | ||
) | const |
Definition at line 104 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetHazardRecognizer(), and llvm::TargetMachine::getInstrItineraryData().
ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer | ( | const InstrItineraryData * | II, |
const ScheduleDAG * | DAG | ||
) | const |
Definition at line 114 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMSubtarget::hasVFP2(), and llvm::ARMSubtarget::isThumb2().
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Definition at line 502 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::clobbersPhysReg(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isRegMask().
MachineInstr * ARMBaseInstrInfo::duplicate | ( | MachineInstr * | Orig, |
MachineFunction & | MF | ||
) | const |
Definition at line 1305 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::duplicate(), duplicateCPV(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::A64CC::MI, llvm::MachineOperand::setImm(), and llvm::MachineOperand::setIndex().
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Definition at line 1165 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::dbgs(), DEBUG, llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getRegisterInfo(), llvm::RegState::Implicit, llvm::ARMSubtarget::isCortexA15(), llvm::A64CC::MI, and WidenVMOVS.
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FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.
Definition at line 2423 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultCC(), llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::ARM_AM::getSOImmTwoPartFirst(), llvm::ARM_AM::getSOImmTwoPartSecond(), llvm::ARM_AM::getT2SOImmTwoPartFirst(), llvm::ARM_AM::getT2SOImmTwoPartSecond(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MCInstrDesc::hasOptionalDef(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::ARM_AM::isSOImmTwoPartVal(), llvm::ARM_AM::isT2SOImmTwoPartVal(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setReg().
std::pair< uint16_t, uint16_t > ARMBaseInstrInfo::getExecutionDomain | ( | const MachineInstr * | MI | ) | const |
VFP/NEON execution domains.
Definition at line 3903 of file ARMBaseInstrInfo.cpp.
References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::ARMII::DomainNEONA8, llvm::ARMII::DomainVFP, ExeGeneric, ExeNEON, ExeVFP, llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::ARMSubtarget::isCortexA8(), llvm::ARMSubtarget::isCortexA9(), isPredicated(), and llvm::MCInstrDesc::TSFlags.
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GetInstSize - Returns the size of the specified MachineInstr.
GetInstSize - Return the size of the specified MachineInstr.
Definition at line 550 of file ARMBaseInstrInfo.cpp.
References llvm::TargetOpcode::BUNDLE, llvm::TargetOpcode::DBG_VALUE, llvm::TargetOpcode::EH_LABEL, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineFunction::getJumpTableInfo(), llvm::MachineJumpTableInfo::getJumpTables(), llvm::TargetMachine::getMCAsmInfo(), getNumJTEntries(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MCInstrDesc::getSize(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), llvm::TargetOpcode::IMPLICIT_DEF, llvm::ISD::INLINEASM, llvm::MachineInstr::isLabel(), llvm::MachineInstr::isPredicable(), llvm::TargetOpcode::KILL, and llvm::TargetOpcode::PROLOG_LABEL.
Referenced by GetFunctionSizeInBytes().
unsigned ARMBaseInstrInfo::getNumLDMAddresses | ( | const MachineInstr * | MI | ) | const |
Get the number of addresses by LDM or VLDM or zero for unknown.
Definition at line 2784 of file ARMBaseInstrInfo.cpp.
References I, llvm::MachineInstr::memoperands_begin(), and llvm::MachineInstr::memoperands_end().
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Definition at line 2794 of file ARMBaseInstrInfo.cpp.
References llvm::tgtok::Class, llvm::MachineInstr::getDesc(), llvm::InstrItineraryData::getNumMicroOps(), getNumMicroOpsSwiftLdSt(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::getSchedClass(), llvm::MachineInstr::hasOneMemOperand(), llvm::ARMSubtarget::isCortexA8(), llvm::InstrItineraryData::isEmpty(), llvm::ARMSubtarget::isLikeA9(), llvm::ARMSubtarget::isSwift(), llvm_unreachable, llvm::MCInstrDesc::mayLoad(), llvm::MCInstrDesc::mayStore(), and llvm::MachineInstr::memoperands_begin().
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Definition at line 3431 of file ARMBaseInstrInfo.cpp.
References adjustDefLatency(), llvm::ARMISD::FMSTAT, llvm::Function::getAttributes(), getBundledDefMI(), getBundledUseMI(), llvm::MachineInstr::getDesc(), llvm::MachineFunction::getFunction(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isBundle(), llvm::MachineInstr::isCopyLike(), llvm::InstrItineraryData::isEmpty(), llvm::MachineOperand::isImplicit(), llvm::MachineInstr::isImplicitDef(), llvm::MachineInstr::isInsertSubreg(), llvm::ARMSubtarget::isLikeA9(), llvm::MachineInstr::isRegSequence(), llvm::ARMSubtarget::isThumb2(), llvm::MachineInstr::memoperands_begin(), and llvm::Attribute::OptimizeForSize.
Referenced by getOperandLatency().
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Definition at line 3522 of file ARMBaseInstrInfo.cpp.
References llvm::dyn_cast(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getOpcode(), llvm::SDNode::getOperand(), llvm::InstrItineraryData::getOperandCycle(), getOperandLatency(), llvm::MCInstrDesc::getSchedClass(), llvm::ARMSubtarget::isCortexA8(), llvm::InstrItineraryData::isEmpty(), llvm::ARMSubtarget::isLikeA9(), llvm::SDNode::isMachineOpcode(), llvm::ARMSubtarget::isSwift(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, llvm::MCInstrDesc::mayLoad(), llvm::MachineSDNode::memoperands_begin(), llvm::MachineSDNode::memoperands_empty(), and llvm::MCInstrDesc::Opcode.
unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance | ( | const MachineInstr * | MI, |
unsigned | OpNum, | ||
const TargetRegisterInfo * | TRI | ||
) | const |
Definition at line 4199 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::definesRegister(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::ARMSubtarget::isCortexA15(), llvm::ARMSubtarget::isSwift(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineOperand::readsReg(), llvm::MachineInstr::readsVirtualRegister(), and SwiftPartialUpdateClearance.
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Definition at line 77 of file ARMBaseInstrInfo.h.
References llvm::ARMCC::AL, llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineOperand::getImm(), and llvm::MachineInstr::getOperand().
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Definition at line 50 of file ARMBaseInstrInfo.h.
Referenced by llvm::ARMHazardRecognizer::getHazardType(), and isPredicable().
Implemented in llvm::ARMInstrInfo, llvm::Thumb2InstrInfo, and llvm::Thumb1InstrInfo.
Referenced by convertToThreeAddress().
bool ARMBaseInstrInfo::hasNOP | ( | ) | const |
Definition at line 4295 of file ARMBaseInstrInfo.cpp.
Referenced by llvm::ARMInstrInfo::getNoopForMachoTarget().
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Definition at line 392 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::SmallVectorBase::empty(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::ARMFunctionInfo::isThumbFunction(), and llvm::SmallVectorTemplateCommon< T >::size().
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
Definition at line 300 of file ARMBaseInstrInfo.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::count().
Referenced by llvm::ARMHazardRecognizer::getHazardType().
bool ARMBaseInstrInfo::isFpMLxInstruction | ( | unsigned | Opcode, |
unsigned & | MulOpc, | ||
unsigned & | AddSubOpc, | ||
bool & | NegAcc, | ||
bool & | HasLane | ||
) | const |
isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to. Return true for 'HasLane' for the MLX instructions with an extra lane operand.
Definition at line 3868 of file ARMBaseInstrInfo.cpp.
References ARM_MLxEntry::AddSubOpc, ARM_MLxTable, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::find(), ARM_MLxEntry::HasLane, ARM_MLxEntry::MulOpc, and ARM_MLxEntry::NegAcc.
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Definition at line 1111 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
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Definition at line 1159 of file ARMBaseInstrInfo.cpp.
References llvm::NVPTXISD::Dummy, and llvm::MachineInstr::mayLoad().
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isPredicable - Return true if the specified instruction can be predicated. By default, this returns true for every instruction with a PredicateOperand.
Definition at line 520 of file ARMBaseInstrInfo.cpp.
References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::MachineInstr::getDesc(), llvm::MachineFunction::getInfo(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), getSubtarget(), llvm::MachineInstr::isPredicable(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::isV8EligibleForIT(), llvm::ARMSubtarget::restrictIT(), and llvm::MCInstrDesc::TSFlags.
bool ARMBaseInstrInfo::isPredicated | ( | const MachineInstr * | MI | ) | const |
Definition at line 437 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), I, llvm::MachineBasicBlock::instr_end(), llvm::MachineInstr::isBundle(), and llvm::A64CC::MI.
Referenced by AnalyzeBranch(), getExecutionDomain(), optimizeCompareInstr(), and setExecutionDomain().
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Definition at line 180 of file ARMBaseInstrInfo.h.
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Definition at line 1568 of file ARMBaseInstrInfo.cpp.
References llvm::BranchProbability::getDenominator(), llvm::ARMSubtarget::getMispredictionPenalty(), and llvm::BranchProbability::getNumerator().
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Definition at line 1584 of file ARMBaseInstrInfo.cpp.
References llvm::BranchProbability::getDenominator(), llvm::ARMSubtarget::getMispredictionPenalty(), and llvm::BranchProbability::getNumerator().
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Definition at line 1608 of file ARMBaseInstrInfo.cpp.
References llvm::ARMSubtarget::isSwift().
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Definition at line 1524 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::definesRegister(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::isCall(), llvm::MachineInstr::isDebugValue(), llvm::MachineInstr::isLabel(), llvm::MachineInstr::isTerminator(), and llvm::A64CC::MI.
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Definition at line 920 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
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Definition at line 968 of file ARMBaseInstrInfo.cpp.
References llvm::NVPTXISD::Dummy, and llvm::MachineInstr::mayStore().
bool ARMBaseInstrInfo::isSwiftFastImmShift | ( | const MachineInstr * | MI | ) | const |
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Definition at line 4299 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::ARM_AM::getSORegOffset(), llvm::ARM_AM::getSORegShOp(), llvm::ARM_AM::lsl, and llvm::ARM_AM::lsr.
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Reimplemented in llvm::Thumb2InstrInfo, and llvm::Thumb1InstrInfo.
Definition at line 975 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align(), llvm::BuildMI(), llvm::RegState::DefineNoRead, llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::TargetRegisterClass::getSize(), llvm::ARMSubtarget::hasV5TEOps(), llvm::RegState::ImplicitDefine, llvm::TargetRegisterInfo::isPhysicalRegister(), llvm_unreachable, and llvm::MachineMemOperand::MOLoad.
Referenced by llvm::Thumb2InstrInfo::loadRegFromStackSlot().
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optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register; Remove a redundant Compare instruction if an earlier instruction can set the flags in the same way as Compare. E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the condition code of instructions which use the flags.
Definition at line 2216 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::ARMCC::GE, llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::ARMCC::GT, I, llvm::MachineOperand::isDef(), isPredicated(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), isSuitableForMask(), llvm::ARMCC::LE, llvm::ARMCC::LT, llvm::A64CC::MI, llvm::MachineInstr::modifiesRegister(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::readsRegister(), llvm::MachineOperand::setIsDef(), llvm::MachineOperand::setReg(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), llvm::MachineRegisterInfo::use_begin(), llvm::MachineRegisterInfo::use_end(), llvm::ARMCC::VC, and llvm::ARMCC::VS.
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Definition at line 1725 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultCC(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), canFoldIntoMOVCC(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::hasOptionalDef(), llvm::A64CC::MI, MRI, llvm::MachineOperand::setImplicit(), and llvm::MachineInstr::tieOperands().
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Definition at line 454 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::findFirstPredOperandIdx(), llvm::getMatchingCondBranchOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::isUncondBranchOpcode(), llvm::A64CC::MI, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().
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Definition at line 1320 of file ARMBaseInstrInfo.cpp.
References llvm::MachineConstantPoolEntry::ConstVal, llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstants(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ARMConstantPoolValue::hasSameValue(), llvm::MachineInstr::IgnoreVRegDefs, llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::isIdenticalTo(), llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineConstantPoolEntry::MachineCPVal, and llvm::MachineConstantPoolEntry::Val.
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Definition at line 1277 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), duplicateCPV(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::insert(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), llvm::MachineInstr::setMemRefs(), and llvm::MachineInstr::substituteRegister().
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Definition at line 363 of file ARMBaseInstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), I, llvm::isCondBranchOpcode(), and llvm::isUncondBranchOpcode().
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Definition at line 431 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::getOppositeCondition().
void ARMBaseInstrInfo::setExecutionDomain | ( | MachineInstr * | MI, |
unsigned | Domain | ||
) | const |
Definition at line 3993 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, ExeNEON, getCorrespondingDRegAndLane(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), getImplicitSPRUseForDPRUse(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::getUndefRegState(), llvm::RegState::Implicit, isPredicated(), llvm_unreachable, llvm::A64CC::MI, llvm::MachineInstr::readsRegister(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.
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shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.
Definition at line 1494 of file ARMBaseInstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().
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Reimplemented in llvm::Thumb2InstrInfo, and llvm::Thumb1InstrInfo.
Definition at line 784 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::TargetRegisterClass::getSize(), llvm::ARMSubtarget::hasV5TEOps(), llvm_unreachable, and llvm::MachineMemOperand::MOStore.
Referenced by llvm::Thumb2InstrInfo::storeRegToStackSlot().
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Definition at line 476 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, and llvm::SmallVectorTemplateCommon< T >::size().