Although this Makefile works, it is not very flexible.
A Makefile may contain macros that contain some common definitions.
Figure 8: A Makefile with macros.
Figure 8 shows a Makefile that starts with some
macro definitions.
A macro can be expanded by surrounding its name with parenthesis
or curly brackets
and prepending a dollar sign.
Note that $$ expands to a literal dollar sign.
CC is commonly used to denote the name of the C compiler.
If its definition is omitted, the default cc is used instead.
CFLAGS is used to express the compiler options; it defaults to
an empty string.