Figure 9: Pattern substitution in macro expansions.
The Makefile in figure 9 shows how we can use pattern substitution to
replace patterns in a list of identifiers. We changed the definition of
OBJECTS to replace all trailing .c in $(SOURCES)
by .o. Note also the use of
comments, which start with a hash and extend to the end of the line.
A pattern can also be substituted in targets and dependencies.
This is very useful to specify how a source file can be compiled to an object
file.
All source files are compiled in a similar way, so we write a
pattern rule for generating a .o file from a .c file.
Figure 10: The use of pattern rules.
Figure 10 shows how we can use such a pattern rule.
This rule states how we can make a .o file from its corresponding
.c file.
The macro is used to denote the current dependency.
Analogous, @ denotes the current target.
Note that the dependencies at the end of the Makefile remain.
Make still needs to know when it must update a target.
In this example we explicitely gave the pattern rule for %.o: %.c,
but we do not need to do so.
Generation of an object file from a source file is so common, that make
knows how to do it.
If we omit the whole rule, make uses a slightly different but
functionally equivalent built-in default (suffix) rule.
However, defining the rule explicitly never hurts.