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NVPTXISelDAGToDAG.h
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1 //===-- NVPTXISelDAGToDAG.h - A dag to dag inst selector for NVPTX --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines an instruction selector for the NVPTX target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "nvptx-isel"
15 
16 #include "NVPTX.h"
17 #include "NVPTXISelLowering.h"
18 #include "NVPTXRegisterInfo.h"
19 #include "NVPTXTargetMachine.h"
21 #include "llvm/IR/Intrinsics.h"
22 #include "llvm/Support/Compiler.h"
23 using namespace llvm;
24 
25 namespace {
26 
27 class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
28 
29  // If true, generate corresponding FPCONTRACT. This is
30  // language dependent (i.e. CUDA and OpenCL works differently).
31  bool doFMAF64;
32  bool doFMAF32;
33  bool doFMAF64AGG;
34  bool doFMAF32AGG;
35  bool allowFMA;
36 
37  // If true, generate mul.wide from sext and mul
38  bool doMulWide;
39 
40  int getDivF32Level() const;
41  bool usePrecSqrtF32() const;
42  bool useF32FTZ() const;
43 
44 public:
45  explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
46  CodeGenOpt::Level OptLevel);
47 
48  // Pass Name
49  virtual const char *getPassName() const {
50  return "NVPTX DAG->DAG Pattern Instruction Selection";
51  }
52 
53  const NVPTXSubtarget &Subtarget;
54 
55  virtual bool SelectInlineAsmMemoryOperand(
56  const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps);
57 private:
58 // Include the pieces autogenerated from the target description.
59 #include "NVPTXGenDAGISel.inc"
60 
61  SDNode *Select(SDNode *N);
62  SDNode *SelectLoad(SDNode *N);
63  SDNode *SelectLoadVector(SDNode *N);
64  SDNode *SelectLDGLDUVector(SDNode *N);
65  SDNode *SelectStore(SDNode *N);
66  SDNode *SelectStoreVector(SDNode *N);
67  SDNode *SelectLoadParam(SDNode *N);
68  SDNode *SelectStoreRetval(SDNode *N);
69  SDNode *SelectStoreParam(SDNode *N);
70 
71  inline SDValue getI32Imm(unsigned Imm) {
72  return CurDAG->getTargetConstant(Imm, MVT::i32);
73  }
74 
75  // Match direct address complex pattern.
76  bool SelectDirectAddr(SDValue N, SDValue &Address);
77 
78  bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
79  SDValue &Offset, MVT mvt);
80  bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
81  SDValue &Offset);
82  bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
83  SDValue &Offset);
84 
85  bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
86  SDValue &Offset, MVT mvt);
87  bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
88  SDValue &Offset);
89  bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
90  SDValue &Offset);
91 
92  bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
93 
94  bool UndefOrImm(SDValue Op, SDValue N, SDValue &Retval);
95 
96 };
97 }
#define LLVM_LIBRARY_VISIBILITY
Definition: Compiler.h:173
#define N