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llvm::SITargetLowering Member List

This is the complete list of members for llvm::SITargetLowering, including all inherited members.

addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)llvm::TargetLoweringBaseinlineprotected
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
addRegisterClass(MVT VT, const TargetRegisterClass *RC)llvm::TargetLoweringBaseinlineprotected
AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const llvm::SITargetLoweringvirtual
allowsUnalignedMemoryAccesses(EVT VT, bool *IsFast) const llvm::SITargetLoweringvirtual
allowTruncateForTailCall(Type *, Type *) const llvm::TargetLoweringBaseinlinevirtual
AMDGPUTargetLowering(TargetMachine &TM)llvm::AMDGPUTargetLowering
AnalyzeFormalArguments(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const llvm::AMDGPUTargetLoweringprotected
analyzeImmediate(const SDNode *N) const llvm::SITargetLowering
ArgListTy typedefllvm::TargetLowering
AsmOperandInfoVector typedefllvm::TargetLowering
BooleanContent enum namellvm::TargetLoweringBase
BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const llvm::TargetLowering
BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const llvm::TargetLowering
BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const llvm::TargetLowering
C_Memory enum valuellvm::TargetLowering
C_Other enum valuellvm::TargetLowering
C_Register enum valuellvm::TargetLowering
C_RegisterClass enum valuellvm::TargetLowering
C_Unknown enum valuellvm::TargetLowering
CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const llvm::TargetLoweringinlinevirtual
canOpTrap(unsigned Op, EVT VT) const llvm::TargetLoweringBasevirtual
clearOperationActions()llvm::TargetLoweringBaseinlineprotected
clearRegisterClasses()llvm::TargetLoweringBaseinlineprotected
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=0) const llvm::TargetLoweringvirtual
computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const llvm::AMDGPUTargetLoweringvirtual
ComputeNumSignBitsForTargetNode(SDValue Op, unsigned Depth=0) const llvm::TargetLoweringvirtual
computeRegisterProperties()llvm::TargetLoweringBaseprotected
ConstraintType enum namellvm::TargetLowering
ConstraintWeight enum namellvm::TargetLowering
createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const llvm::TargetLoweringinlinevirtual
CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const llvm::SITargetLoweringvirtual
Custom enum valuellvm::TargetLoweringBase
CW_Best enum valuellvm::TargetLowering
CW_Better enum valuellvm::TargetLowering
CW_Constant enum valuellvm::TargetLowering
CW_Default enum valuellvm::TargetLowering
CW_Good enum valuellvm::TargetLowering
CW_Invalid enum valuellvm::TargetLowering
CW_Memory enum valuellvm::TargetLowering
CW_Okay enum valuellvm::TargetLowering
CW_Register enum valuellvm::TargetLowering
CW_SpecificReg enum valuellvm::TargetLowering
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const llvm::SITargetLoweringvirtual
Expand enum valuellvm::TargetLoweringBase
ExpandInlineAsm(CallInst *) const llvm::TargetLoweringinlinevirtual
findRepresentativeClass(MVT VT) const llvm::TargetLoweringBaseprotectedvirtual
GetAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const llvm::TargetLoweringBaseinlinevirtual
getBooleanContents(bool isVec) const llvm::TargetLoweringBaseinline
getBypassSlowDivWidths() const llvm::TargetLoweringBaseinline
getByValTypeAlignment(Type *Ty) const llvm::TargetLoweringBasevirtual
getCmpLibcallCC(RTLIB::Libcall Call) const llvm::TargetLoweringBaseinline
getCmpLibcallReturnType() const llvm::TargetLoweringBasevirtual
getCondCodeAction(ISD::CondCode CC, MVT VT) const llvm::TargetLoweringBaseinline
getConstraintType(const std::string &Constraint) const llvm::TargetLoweringvirtual
getDataLayout() const llvm::TargetLoweringBaseinline
getExceptionPointerRegister() const llvm::TargetLoweringBaseinline
getExceptionSelectorRegister() const llvm::TargetLoweringBaseinline
getExtendForContent(BooleanContent Content)llvm::TargetLoweringBaseinlinestatic
getIndexedLoadAction(unsigned IdxMode, MVT VT) const llvm::TargetLoweringBaseinline
getIndexedStoreAction(unsigned IdxMode, MVT VT) const llvm::TargetLoweringBaseinline
getInsertFencesForAtomic() const llvm::TargetLoweringBaseinline
getJumpBufAlignment() const llvm::TargetLoweringBaseinline
getJumpBufSize() const llvm::TargetLoweringBaseinline
getJumpTableEncoding() const llvm::TargetLoweringvirtual
getLibcallCallingConv(RTLIB::Libcall Call) const llvm::TargetLoweringBaseinline
getLibcallName(RTLIB::Libcall Call) const llvm::TargetLoweringBaseinline
getLoadExtAction(unsigned ExtType, MVT VT) const llvm::TargetLoweringBaseinline
getMaximalGlobalOffset() const llvm::TargetLoweringBaseinlinevirtual
getMaxStoresPerMemcpy(bool OptSize) const llvm::TargetLoweringBaseinline
getMaxStoresPerMemmove(bool OptSize) const llvm::TargetLoweringBaseinline
getMaxStoresPerMemset(bool OptSize) const llvm::TargetLoweringBaseinline
getMinFunctionAlignment() const llvm::TargetLoweringBaseinline
getMinimumJumpTableEntries() const llvm::TargetLoweringBaseinline
getMinStackArgumentAlignment() const llvm::TargetLoweringBaseinline
getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const llvm::TargetLoweringvirtual
getNumRegisters(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getObjFileLowering() const llvm::TargetLoweringBaseinline
getOperationAction(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const llvm::TargetLoweringBaseinlinevirtual
getOriginalFunctionArgs(SelectionDAG &DAG, const Function *F, const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< ISD::InputArg > &OrigIns) const llvm::AMDGPUTargetLoweringprotected
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const llvm::TargetLoweringvirtual
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const llvm::TargetLoweringvirtual
getPointerSizeInBits(uint32_t AS=0) const llvm::TargetLoweringBase
getPointerTy(uint32_t=0) const llvm::TargetLoweringBasevirtual
getPointerTypeSizeInBits(Type *Ty) const llvm::TargetLoweringBase
getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const llvm::TargetLoweringinlinevirtual
getPrefFunctionAlignment() const llvm::TargetLoweringBaseinline
getPrefLoopAlignment() const llvm::TargetLoweringBaseinline
getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const llvm::TargetLoweringinlinevirtual
getRegClassFor(MVT VT) const llvm::TargetLoweringBaseinlinevirtual
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const llvm::TargetLoweringvirtual
getRegisterType(MVT VT) const llvm::TargetLoweringBaseinline
getRegisterType(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getRepRegClassCostFor(MVT VT) const llvm::TargetLoweringBaseinlinevirtual
getRepRegClassFor(MVT VT) const llvm::TargetLoweringBaseinlinevirtual
getScalarShiftAmountTy(EVT VT) const llvm::SITargetLoweringvirtual
getScalingFactorCost(const AddrMode &AM, Type *Ty) const llvm::TargetLoweringBaseinlinevirtual
getSchedulingPreference() const llvm::TargetLoweringBaseinline
getSchedulingPreference(SDNode *) const llvm::TargetLoweringBaseinlinevirtual
getScratchRegisters(CallingConv::ID CC) const llvm::TargetLoweringinlinevirtual
getSetCCResultType(LLVMContext &Context, EVT VT) const llvm::SITargetLoweringvirtual
getShiftAmountTy(EVT LHSTy) const llvm::TargetLoweringBase
getSimpleValueType(Type *Ty, bool AllowUnknown=false) const llvm::TargetLoweringBaseinline
getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const llvm::TargetLoweringvirtual
getStackCookieLocation(unsigned &, unsigned &) const llvm::TargetLoweringBaseinlinevirtual
getStackPointerRegisterToSaveRestore() const llvm::TargetLoweringBaseinline
getTargetMachine() const llvm::TargetLoweringBaseinline
getTargetNodeName(unsigned Opcode) const llvm::AMDGPUTargetLoweringvirtual
getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const llvm::AMDGPUTargetLoweringvirtual
getTruncStoreAction(MVT ValVT, MVT MemVT) const llvm::TargetLoweringBaseinline
getTypeAction(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getTypeAction(MVT VT) const llvm::TargetLoweringBaseinline
getTypeConversion(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getTypeForExtArgOrReturn(MVT VT, ISD::NodeType) const llvm::TargetLoweringinlinevirtual
getTypeLegalizationCost(Type *Ty) const llvm::TargetLoweringBase
getTypeToExpandTo(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getTypeToPromoteTo(unsigned Op, MVT VT) const llvm::TargetLoweringBaseinline
getTypeToTransformTo(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getValueType(Type *Ty, bool AllowUnknown=false) const llvm::TargetLoweringBaseinline
getValueTypeActions() const llvm::TargetLoweringBaseinline
getVectorIdxTy() const llvm::AMDGPUTargetLoweringvirtual
getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const llvm::TargetLoweringBase
HandleByVal(CCState *, unsigned &, unsigned) const llvm::TargetLoweringinlinevirtual
hasPairedLoad(Type *, unsigned &) const llvm::TargetLoweringBaseinlinevirtual
hasPairedLoad(EVT, unsigned &) const llvm::TargetLoweringBaseinlinevirtual
hasTargetDAGCombine(ISD::NodeType NT) const llvm::TargetLoweringBaseinline
initActions()llvm::TargetLoweringBaseprotected
InstructionOpcodeToISD(unsigned Opcode) const llvm::TargetLoweringBase
isBigEndian() const llvm::TargetLoweringBaseinline
isCondCodeLegal(ISD::CondCode CC, MVT VT) const llvm::TargetLoweringBaseinline
IsDesirableToPromoteOp(SDValue, EVT &) const llvm::TargetLoweringinlinevirtual
isDesirableToTransformToIntegerOp(unsigned, EVT) const llvm::TargetLoweringinlinevirtual
isFAbsFree(EVT VT) const llvm::AMDGPUTargetLoweringvirtual
isFMAFasterThanFMulAndFAdd(EVT VT) const llvm::SITargetLoweringvirtual
isFNegFree(EVT VT) const llvm::AMDGPUTargetLoweringvirtual
isFPImmLegal(const APFloat &Imm, EVT VT) const llvm::AMDGPUTargetLoweringvirtual
isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const llvm::TargetLoweringvirtual
isHWFalseValue(SDValue Op) const llvm::AMDGPUTargetLoweringprotected
isHWTrueValue(SDValue Op) const llvm::AMDGPUTargetLoweringprotected
isIndexedLoadLegal(unsigned IdxMode, EVT VT) const llvm::TargetLoweringBaseinline
isIndexedStoreLegal(unsigned IdxMode, EVT VT) const llvm::TargetLoweringBaseinline
isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const llvm::TargetLowering
isIntDivCheap() const llvm::TargetLoweringBaseinline
isJumpExpensive() const llvm::TargetLoweringBaseinline
isLegalAddImmediate(int64_t) const llvm::TargetLoweringBaseinlinevirtual
isLegalAddressingMode(const AddrMode &AM, Type *Ty) const llvm::TargetLoweringBasevirtual
isLegalICmpImmediate(int64_t) const llvm::TargetLoweringBaseinlinevirtual
isLegalRC(const TargetRegisterClass *RC) const llvm::TargetLoweringBaseprotected
isLittleEndian() const llvm::TargetLoweringBaseinline
isLoadBitCastBeneficial(EVT, EVT) const LLVM_OVERRIDEllvm::AMDGPUTargetLoweringvirtual
isLoadExtLegal(unsigned ExtType, EVT VT) const llvm::TargetLoweringBaseinline
isNarrowingProfitable(EVT, EVT) const llvm::TargetLoweringBaseinlinevirtual
isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const llvm::TargetLoweringBaseinlinevirtual
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const llvm::TargetLoweringvirtual
isOperationExpand(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isOperationLegal(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isOperationLegalOrCustom(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isOperationLegalOrPromote(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isPow2DivCheap() const llvm::TargetLoweringBaseinline
isPredictableSelectExpensive() const llvm::TargetLoweringBaseinline
isSafeMemOpType(MVT) const llvm::TargetLoweringBaseinlinevirtual
isSelectExpensive() const llvm::TargetLoweringBaseinline
isSelectSupported(SelectSupportKind) const llvm::TargetLoweringBaseinlinevirtual
isShuffleMaskLegal(const SmallVectorImpl< int > &, EVT) const llvm::TargetLoweringBaseinlinevirtual
isSlowDivBypassed() const llvm::TargetLoweringBaseinline
isTruncateFree(Type *, Type *) const llvm::TargetLoweringBaseinlinevirtual
isTruncateFree(EVT, EVT) const llvm::TargetLoweringBaseinlinevirtual
isTruncStoreLegal(EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
isTypeDesirableForOp(unsigned, EVT VT) const llvm::TargetLoweringinlinevirtual
isTypeLegal(EVT VT) const llvm::TargetLoweringBaseinline
isUsedByReturnOnly(SDNode *, SDValue &) const llvm::TargetLoweringinlinevirtual
isVectorClearMaskLegal(const SmallVectorImpl< int > &, EVT) const llvm::TargetLoweringBaseinlinevirtual
isZExtFree(Type *, Type *) const llvm::TargetLoweringBaseinlinevirtual
isZExtFree(EVT, EVT) const llvm::TargetLoweringBaseinlinevirtual
isZExtFree(SDValue Val, EVT VT2) const llvm::TargetLoweringBaseinlinevirtual
Legal enum valuellvm::TargetLoweringBase
LegalizeAction enum namellvm::TargetLoweringBase
LegalizeKind typedefllvm::TargetLoweringBase
LegalizeTypeAction enum namellvm::TargetLoweringBase
LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const llvm::TargetLoweringvirtual
LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const llvm::AMDGPUTargetLoweringinlinevirtual
LowerCallTo(CallLoweringInfo &CLI) const llvm::TargetLowering
LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const llvm::TargetLoweringinlinevirtual
LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const llvm::SITargetLoweringvirtual
LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLowering
LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLowering
LowerMinMax(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLowering
LowerOperation(SDValue Op, SelectionDAG &DAG) const llvm::SITargetLoweringvirtual
LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const llvm::TargetLoweringvirtual
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringvirtual
LowerXConstraint(EVT ConstraintVT) const llvm::TargetLoweringvirtual
makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const llvm::TargetLowering
MaxStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemmovellvm::TargetLoweringBaseprotected
MaxStoresPerMemmoveOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemsetllvm::TargetLoweringBaseprotected
MaxStoresPerMemsetOptSizellvm::TargetLoweringBaseprotected
mayBeEmittedAsTailCall(CallInst *) const llvm::TargetLoweringinlinevirtual
ParseConstraints(ImmutableCallSite CS) const llvm::TargetLoweringvirtual
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::SITargetLoweringvirtual
PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const llvm::SITargetLoweringvirtual
PredictableSelectIsExpensivellvm::TargetLoweringBaseprotected
Promote enum valuellvm::TargetLoweringBase
ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const llvm::TargetLoweringinlinevirtual
resetOperationActions()llvm::TargetLoweringBaseinlinevirtual
ScalarCondVectorVal enum valuellvm::TargetLoweringBase
ScalarValSelect enum valuellvm::TargetLoweringBase
SelectSupportKind enum namellvm::TargetLoweringBase
setBooleanContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setBooleanVectorContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)llvm::TargetLoweringBaseinline
setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setExceptionPointerRegister(unsigned R)llvm::TargetLoweringBaseinlineprotected
setExceptionSelectorRegister(unsigned R)llvm::TargetLoweringBaseinlineprotected
setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setInsertFencesForAtomic(bool fence)llvm::TargetLoweringBaseinlineprotected
setIntDivIsCheap(bool isCheap=true)llvm::TargetLoweringBaseinlineprotected
setJumpBufAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setJumpBufSize(unsigned Size)llvm::TargetLoweringBaseinlineprotected
setJumpIsExpensive(bool isExpensive=true)llvm::TargetLoweringBaseinlineprotected
setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)llvm::TargetLoweringBaseinline
setLibcallName(RTLIB::Libcall Call, const char *Name)llvm::TargetLoweringBaseinline
setLoadExtAction(unsigned ExtType, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setMinFunctionAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setMinimumJumpTableEntries(int Val)llvm::TargetLoweringBaseinlineprotected
setMinStackArgumentAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setPow2DivIsCheap(bool isCheap=true)llvm::TargetLoweringBaseinlineprotected
setPrefFunctionAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setPrefLoopAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setSchedulingPreference(Sched::Preference Pref)llvm::TargetLoweringBaseinlineprotected
setSelectIsExpensive(bool isExpensive=true)llvm::TargetLoweringBaseinlineprotected
setStackPointerRegisterToSaveRestore(unsigned R)llvm::TargetLoweringBaseinlineprotected
setSupportJumpTables(bool Val)llvm::TargetLoweringBaseinlineprotected
setTargetDAGCombine(ISD::NodeType NT)llvm::TargetLoweringBaseinlineprotected
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setUseUnderscoreLongJmp(bool Val)llvm::TargetLoweringBaseinlineprotected
setUseUnderscoreSetJmp(bool Val)llvm::TargetLoweringBaseinlineprotected
ShouldShrinkFPConstant(EVT VT) const llvm::AMDGPUTargetLoweringvirtual
shouldSplitVectorElementType(EVT VT) const llvm::SITargetLoweringvirtual
SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const llvm::TargetLowering
SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const llvm::TargetLowering
SITargetLowering(TargetMachine &tm)llvm::SITargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const llvm::TargetLowering
SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
SplitVectorStore(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
supportJumpTables() const llvm::TargetLoweringBaseinline
TargetLowering(const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)llvm::TargetLoweringexplicit
TargetLoweringBase(const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)llvm::TargetLoweringBaseexplicit
TypeExpandFloat enum valuellvm::TargetLoweringBase
TypeExpandInteger enum valuellvm::TargetLoweringBase
TypeLegal enum valuellvm::TargetLoweringBase
TypePromoteInteger enum valuellvm::TargetLoweringBase
TypeScalarizeVector enum valuellvm::TargetLoweringBase
TypeSoftenFloat enum valuellvm::TargetLoweringBase
TypeSplitVector enum valuellvm::TargetLoweringBase
TypeWidenVector enum valuellvm::TargetLoweringBase
UndefinedBooleanContent enum valuellvm::TargetLoweringBase
usesUnderscoreLongJmp() const llvm::TargetLoweringBaseinline
usesUnderscoreSetJmp() const llvm::TargetLoweringBaseinline
VectorMaskSelect enum valuellvm::TargetLoweringBase
ZeroOrNegativeOneBooleanContent enum valuellvm::TargetLoweringBase
ZeroOrOneBooleanContent enum valuellvm::TargetLoweringBase
~TargetLoweringBase()llvm::TargetLoweringBasevirtual

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