#include <AMDGPUISelLowering.h>

Inheritance diagram for llvm::AMDGPUTargetLowering:

Collaboration diagram for llvm::AMDGPUTargetLowering:

Public Member Functions
	AMDGPUTargetLowering (TargetMachine &TM)

virtual bool	isFAbsFree (EVT VT) const

virtual bool	isFNegFree (EVT VT) const

virtual MVT	getVectorIdxTy () const

virtual bool	isLoadBitCastBeneficial (EVT, EVT) const LLVM_OVERRIDE

virtual SDValue	LowerReturn (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc DL, SelectionDAG &DAG) const

virtual SDValue	LowerCall (CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const

virtual SDValue	LowerOperation (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerIntrinsicIABS (SDValue Op, SelectionDAG &DAG) const
	IABS(a) = SMAX(sub(0, a), a) More...

SDValue	LowerIntrinsicLRP (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerMinMax (SDValue Op, SelectionDAG &DAG) const
	Generate Min/Max node. More...

virtual const char *	getTargetNodeName (unsigned Opcode) const
	This method returns the name of a target specific DAG node. More...

virtual SDNode *	PostISelFolding (MachineSDNode *N, SelectionDAG &DAG) const

virtual void	computeMaskedBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const
	Determine which of the bits specified in `Mask` are known to be either zero or one and return them in the `KnownZero` and `KnownOne` bitsets. More...

virtual bool	getTgtMemIntrinsic (IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const

bool	isFPImmLegal (const APFloat &Imm, EVT VT) const
	We want to mark f32/f64 floating point values as legal. More...

bool	ShouldShrinkFPConstant (EVT VT) const
	We don't want to shrink f64/f32 constants. More...

Public Member Functions inherited from llvm::TargetLowering
	TargetLowering (const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)
	NOTE: The constructor takes ownership of TLOF. More...

virtual bool	getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const

virtual bool	getPostIndexedAddressParts (SDNode , SDNode , SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const

virtual unsigned	getJumpTableEncoding () const

virtual const MCExpr *	LowerCustomJumpTableEntry (const MachineJumpTableInfo , const MachineBasicBlock , unsigned, MCContext &) const

virtual SDValue	getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
	Returns relocation base for the given PIC jumptable. More...

virtual const MCExpr *	getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const

virtual bool	isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const

bool	isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const

void	softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const

std::pair< SDValue, SDValue >	makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
	Returns a pair of (return value, chain). More...

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const

virtual unsigned	ComputeNumSignBitsForTargetNode (SDValue Op, unsigned Depth=0) const

SDValue	SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const

virtual bool	isGAPlusOffset (SDNode N, const GlobalValue &GA, int64_t &Offset) const

virtual SDValue	PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const

virtual bool	isTypeDesirableForOp (unsigned, EVT VT) const

virtual bool	isDesirableToTransformToIntegerOp (unsigned, EVT) const

virtual bool	IsDesirableToPromoteOp (SDValue, EVT &) const

virtual SDValue	LowerFormalArguments (SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, SDLoc, SelectionDAG &, SmallVectorImpl< SDValue > &) const

std::pair< SDValue, SDValue >	LowerCallTo (CallLoweringInfo &CLI) const

virtual void	HandleByVal (CCState *, unsigned &, unsigned) const
	Target-specific cleanup for formal ByVal parameters. More...

virtual bool	CanLowerReturn (CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const

virtual bool	isUsedByReturnOnly (SDNode *, SDValue &) const

virtual bool	mayBeEmittedAsTailCall (CallInst *) const

virtual MVT	getTypeForExtArgOrReturn (MVT VT, ISD::NodeType) const

virtual const uint16_t *	getScratchRegisters (CallingConv::ID CC) const

virtual void	LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const

virtual void	ReplaceNodeResults (SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const

virtual FastISel *	createFastISel (FunctionLoweringInfo &, const TargetLibraryInfo *) const

virtual bool	ExpandInlineAsm (CallInst *) const

virtual AsmOperandInfoVector	ParseConstraints (ImmutableCallSite CS) const

virtual ConstraintWeight	getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const

virtual ConstraintWeight	getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const

virtual void	ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=0) const

virtual ConstraintType	getConstraintType (const std::string &Constraint) const
	Given a constraint, return the type of constraint it is for this target. More...

virtual std::pair< unsigned, const TargetRegisterClass * >	getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const

virtual const char *	LowerXConstraint (EVT ConstraintVT) const

virtual void	LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const

SDValue	BuildExactSDIV (SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const
	Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant. More...

SDValue	BuildSDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode > *Created) const
	Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...

SDValue	BuildUDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode > *Created) const
	Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...

virtual MachineBasicBlock *	EmitInstrWithCustomInserter (MachineInstr MI, MachineBasicBlock MBB) const

virtual void	AdjustInstrPostInstrSelection (MachineInstr MI, SDNode Node) const

Public Member Functions inherited from llvm::TargetLoweringBase
	TargetLoweringBase (const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)
	NOTE: The constructor takes ownership of TLOF. More...

virtual	~TargetLoweringBase ()

const TargetMachine &	getTargetMachine () const

const DataLayout *	getDataLayout () const

const TargetLoweringObjectFile &	getObjFileLowering () const

bool	isBigEndian () const

bool	isLittleEndian () const

virtual MVT	getPointerTy (uint32_t=0) const

unsigned	getPointerSizeInBits (uint32_t AS=0) const

unsigned	getPointerTypeSizeInBits (Type *Ty) const

virtual MVT	getScalarShiftAmountTy (EVT LHSTy) const

EVT	getShiftAmountTy (EVT LHSTy) const

bool	isSelectExpensive () const
	Return true if the select operation is expensive for this target. More...

virtual bool	isSelectSupported (SelectSupportKind) const

virtual bool	shouldSplitVectorElementType (EVT) const

bool	isIntDivCheap () const

bool	isSlowDivBypassed () const
	Returns true if target has indicated at least one type should be bypassed. More...

const DenseMap< unsigned int, unsigned int > &	getBypassSlowDivWidths () const

bool	isPow2DivCheap () const
	Return true if pow2 div is cheaper than a chain of srl/add/sra. More...

bool	isJumpExpensive () const

bool	isPredictableSelectExpensive () const

virtual EVT	getSetCCResultType (LLVMContext &Context, EVT VT) const

virtual MVT::SimpleValueType	getCmpLibcallReturnType () const

BooleanContent	getBooleanContents (bool isVec) const

Sched::Preference	getSchedulingPreference () const
	Return target scheduling preference. More...

virtual Sched::Preference	getSchedulingPreference (SDNode *) const

virtual const TargetRegisterClass *	getRegClassFor (MVT VT) const

virtual const TargetRegisterClass *	getRepRegClassFor (MVT VT) const

virtual uint8_t	getRepRegClassCostFor (MVT VT) const

bool	isTypeLegal (EVT VT) const

const ValueTypeActionImpl &	getValueTypeActions () const

LegalizeTypeAction	getTypeAction (LLVMContext &Context, EVT VT) const

LegalizeTypeAction	getTypeAction (MVT VT) const

EVT	getTypeToTransformTo (LLVMContext &Context, EVT VT) const

EVT	getTypeToExpandTo (LLVMContext &Context, EVT VT) const

unsigned	getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const

virtual bool	isShuffleMaskLegal (const SmallVectorImpl< int > &, EVT) const

virtual bool	canOpTrap (unsigned Op, EVT VT) const

virtual bool	isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const

LegalizeAction	getOperationAction (unsigned Op, EVT VT) const

bool	isOperationLegalOrCustom (unsigned Op, EVT VT) const

bool	isOperationLegalOrPromote (unsigned Op, EVT VT) const

bool	isOperationExpand (unsigned Op, EVT VT) const

bool	isOperationLegal (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target. More...

LegalizeAction	getLoadExtAction (unsigned ExtType, MVT VT) const

bool	isLoadExtLegal (unsigned ExtType, EVT VT) const
	Return true if the specified load with extension is legal on this target. More...

LegalizeAction	getTruncStoreAction (MVT ValVT, MVT MemVT) const

bool	isTruncStoreLegal (EVT ValVT, EVT MemVT) const

LegalizeAction	getIndexedLoadAction (unsigned IdxMode, MVT VT) const

bool	isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getIndexedStoreAction (unsigned IdxMode, MVT VT) const

bool	isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getCondCodeAction (ISD::CondCode CC, MVT VT) const

bool	isCondCodeLegal (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal on this target. More...

MVT	getTypeToPromoteTo (unsigned Op, MVT VT) const

EVT	getValueType (Type *Ty, bool AllowUnknown=false) const

MVT	getSimpleValueType (Type *Ty, bool AllowUnknown=false) const
	Return the MVT corresponding to this LLVM type. See getValueType. More...

virtual unsigned	getByValTypeAlignment (Type *Ty) const

MVT	getRegisterType (MVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

MVT	getRegisterType (LLVMContext &Context, EVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

unsigned	getNumRegisters (LLVMContext &Context, EVT VT) const

bool	hasTargetDAGCombine (ISD::NodeType NT) const

unsigned	getMaxStoresPerMemset (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memset. More...

unsigned	getMaxStoresPerMemcpy (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memcpy. More...

unsigned	getMaxStoresPerMemmove (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memmove. More...

virtual bool	allowsUnalignedMemoryAccesses (EVT, bool *=0) const
	Determine if the target supports unaligned memory accesses. More...

virtual EVT	getOptimalMemOpType (uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const

virtual bool	isSafeMemOpType (MVT) const

bool	usesUnderscoreSetJmp () const
	Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...

bool	usesUnderscoreLongJmp () const
	Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...

bool	supportJumpTables () const
	Return whether the target can generate code for jump tables. More...

int	getMinimumJumpTableEntries () const

unsigned	getStackPointerRegisterToSaveRestore () const

unsigned	getExceptionPointerRegister () const

unsigned	getExceptionSelectorRegister () const

unsigned	getJumpBufSize () const

unsigned	getJumpBufAlignment () const

unsigned	getMinStackArgumentAlignment () const
	Return the minimum stack alignment of an argument. More...

unsigned	getMinFunctionAlignment () const
	Return the minimum function alignment. More...

unsigned	getPrefFunctionAlignment () const
	Return the preferred function alignment. More...

unsigned	getPrefLoopAlignment () const
	Return the preferred loop alignment. More...

bool	getInsertFencesForAtomic () const

virtual bool	getStackCookieLocation (unsigned &, unsigned &) const

virtual unsigned	getMaximalGlobalOffset () const

virtual bool	isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
	Returns true if a cast between SrcAS and DestAS is a noop. More...

virtual void	resetOperationActions ()
	Reset the operation actions based on target options. More...

virtual bool	GetAddrModeArguments (IntrinsicInst , SmallVectorImpl< Value > &, Type *&) const

virtual bool	isLegalAddressingMode (const AddrMode &AM, Type *Ty) const

virtual int	getScalingFactorCost (const AddrMode &AM, Type *Ty) const
	Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...

virtual bool	isLegalICmpImmediate (int64_t) const

virtual bool	isLegalAddImmediate (int64_t) const

virtual bool	isTruncateFree (Type , Type ) const

virtual bool	allowTruncateForTailCall (Type , Type ) const

virtual bool	isTruncateFree (EVT, EVT) const

virtual bool	isZExtFree (Type , Type ) const

virtual bool	isZExtFree (EVT, EVT) const

virtual bool	hasPairedLoad (Type *, unsigned &) const

virtual bool	hasPairedLoad (EVT, unsigned &) const

virtual bool	isZExtFree (SDValue Val, EVT VT2) const

virtual bool	isFMAFasterThanFMulAndFAdd (EVT) const

virtual bool	isNarrowingProfitable (EVT, EVT) const

void	setLibcallName (RTLIB::Libcall Call, const char *Name)
	Rename the default libcall routine name for the specified libcall. More...

const char *	getLibcallName (RTLIB::Libcall Call) const
	Get the libcall routine name for the specified libcall. More...

void	setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)

ISD::CondCode	getCmpLibcallCC (RTLIB::Libcall Call) const

void	setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
	Set the CallingConv that should be used for the specified libcall. More...

CallingConv::ID	getLibcallCallingConv (RTLIB::Libcall Call) const
	Get the CallingConv that should be used for the specified libcall. More...

LegalizeKind	getTypeConversion (LLVMContext &Context, EVT VT) const

int	InstructionOpcodeToISD (unsigned Opcode) const
	Get the ISD node that corresponds to the Instruction class opcode. More...

std::pair< unsigned, MVT >	getTypeLegalizationCost (Type *Ty) const
	Estimate the cost of type-legalization and the legalized type. More...

Protected Member Functions
virtual SDValue	CreateLiveInRegister (SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
	Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction. More...

SDValue	LowerGlobalAddress (AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const

SDValue	SplitVectorLoad (const SDValue &Op, SelectionDAG &DAG) const
	Split a vector load into multiple scalar loads. More...

SDValue	SplitVectorStore (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerSTORE (SDValue Op, SelectionDAG &DAG) const

bool	isHWTrueValue (SDValue Op) const

bool	isHWFalseValue (SDValue Op) const

void	getOriginalFunctionArgs (SelectionDAG &DAG, const Function *F, const SmallVectorImpl< ISD::InputArg > &Ins, SmallVectorImpl< ISD::InputArg > &OrigIns) const

void	AnalyzeFormalArguments (CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const

Protected Member Functions inherited from llvm::TargetLoweringBase
void	initActions ()
	Initialize all of the actions to default values. More...

void	setBooleanContents (BooleanContent Ty)

void	setBooleanVectorContents (BooleanContent Ty)

void	setSchedulingPreference (Sched::Preference Pref)
	Specify the target scheduling preference. More...

void	setUseUnderscoreSetJmp (bool Val)

void	setUseUnderscoreLongJmp (bool Val)

void	setSupportJumpTables (bool Val)
	Indicate whether the target can generate code for jump tables. More...

void	setMinimumJumpTableEntries (int Val)

void	setStackPointerRegisterToSaveRestore (unsigned R)

void	setExceptionPointerRegister (unsigned R)

void	setExceptionSelectorRegister (unsigned R)

void	setSelectIsExpensive (bool isExpensive=true)

void	setJumpIsExpensive (bool isExpensive=true)

void	setIntDivIsCheap (bool isCheap=true)

void	addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
	Tells the code generator which bitwidths to bypass. More...

void	setPow2DivIsCheap (bool isCheap=true)

void	addRegisterClass (MVT VT, const TargetRegisterClass *RC)

void	clearRegisterClasses ()
	Remove all register classes. More...

void	clearOperationActions ()
	Remove all operation actions. More...

virtual std::pair< const TargetRegisterClass *, uint8_t >	findRepresentativeClass (MVT VT) const

void	computeRegisterProperties ()

void	setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)

void	setLoadExtAction (unsigned ExtType, MVT VT, LegalizeAction Action)

void	setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)

void	setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)

void	setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)

void	setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)

void	AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)

void	setTargetDAGCombine (ISD::NodeType NT)

void	setJumpBufSize (unsigned Size)
	Set the target's required jmp_buf buffer size (in bytes); default is 200. More...

void	setJumpBufAlignment (unsigned Align)

void	setMinFunctionAlignment (unsigned Align)
	Set the target's minimum function alignment (in log2(bytes)) More...

void	setPrefFunctionAlignment (unsigned Align)

void	setPrefLoopAlignment (unsigned Align)

void	setMinStackArgumentAlignment (unsigned Align)
	Set the minimum stack alignment of an argument (in log2(bytes)). More...

void	setInsertFencesForAtomic (bool fence)

bool	isLegalRC (const TargetRegisterClass *RC) const

Additional Inherited Members
Public Types inherited from llvm::TargetLowering
enum	ConstraintType { C_Register, C_RegisterClass, C_Memory, C_Other, C_Unknown }

enum	ConstraintWeight { CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2, CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better, CW_Constant = CW_Best, CW_Default = CW_Okay }

typedef std::vector< ArgListEntry >	ArgListTy

typedef std::vector < AsmOperandInfo >	AsmOperandInfoVector

Public Types inherited from llvm::TargetLoweringBase
enum	LegalizeAction { Legal, Promote, Expand, Custom }

enum	LegalizeTypeAction { TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat, TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector }

enum	BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
	Enum that describes how the target represents true/false values. More...

enum	SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
	Enum that describes what type of support for selects the target has. More...

typedef std::pair < LegalizeTypeAction, EVT >	LegalizeKind

Static Public Member Functions inherited from llvm::TargetLoweringBase
static ISD::NodeType	getExtendForContent (BooleanContent Content)

Protected Attributes inherited from llvm::TargetLoweringBase
unsigned	MaxStoresPerMemset
	Specify maximum number of store instructions per memset call. More...

unsigned	MaxStoresPerMemsetOptSize

unsigned	MaxStoresPerMemcpy
	Specify maximum bytes of store instructions per memcpy call. More...

unsigned	MaxStoresPerMemcpyOptSize

unsigned	MaxStoresPerMemmove
	Specify maximum bytes of store instructions per memmove call. More...

unsigned	MaxStoresPerMemmoveOptSize

bool	PredictableSelectIsExpensive

Detailed Description

Definition at line 26 of file AMDGPUISelLowering.h.

Constructor & Destructor Documentation

AMDGPUTargetLowering::AMDGPUTargetLowering ( TargetMachine & TM )

Definition at line 43 of file AMDGPUISelLowering.cpp.

Member Function Documentation

void AMDGPUTargetLowering::AnalyzeFormalArguments	(	CCState &	State,
		const SmallVectorImpl< ISD::InputArg > &	Ins
	)		const

protected

Definition at line 230 of file AMDGPUISelLowering.cpp.

References llvm::CCState::AnalyzeFormalArguments().

Referenced by llvm::R600TargetLowering::LowerFormalArguments(), and llvm::SITargetLowering::LowerFormalArguments().

void AMDGPUTargetLowering::computeMaskedBitsForTargetNode	(	const SDValue	Op,
		APInt &	KnownZero,
		APInt &	KnownOne,
		const SelectionDAG &	DAG,
		unsigned	Depth = `0`
	)		const

virtual

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero and KnownOne bitsets.

Reimplemented from llvm::TargetLowering.

Definition at line 252 of file AMDILISelLowering.cpp.

References llvm::SelectionDAG::ComputeMaskedBits(), llvm::APInt::getBitWidth(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::ISD::SELECT_CC.

SDValue AMDGPUTargetLowering::CreateLiveInRegister	(	SelectionDAG &	DAG,
		const TargetRegisterClass *	RC,
		unsigned	Reg,
		EVT	VT
	)		const

protectedvirtual

Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.

Returns: a RegisterSDNode representing Reg.

Reimplemented in llvm::SITargetLowering.

Definition at line 783 of file AMDGPUISelLowering.cpp.

References llvm::MachineRegisterInfo::addLiveIn(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineRegisterInfo::getLiveInVirtReg(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getRegister(), llvm::MachineRegisterInfo::isLiveIn(), and MRI.

Referenced by llvm::SITargetLowering::CreateLiveInRegister(), and llvm::R600TargetLowering::LowerOperation().

void AMDGPUTargetLowering::getOriginalFunctionArgs	(	SelectionDAG &	DAG,
		const Function *	F,
		const SmallVectorImpl< ISD::InputArg > &	Ins,
		SmallVectorImpl< ISD::InputArg > &	OrigIns
	)		const

protected

The SelectionDAGBuilder will automatically promote function arguments with illegal types. However, this does not work for the AMDGPU targets since the function arguments are stored in memory as these illegal types. In order to handle this properly we need to get the origianl types sizes from the LLVM IR Function and fixup the ISD:InputArg values before passing them to AnalyzeFormalArguments()

Definition at line 731 of file AMDGPUISelLowering.cpp.

References llvm::EVT::isVector(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by llvm::R600TargetLowering::LowerFormalArguments(), and llvm::SITargetLowering::LowerFormalArguments().

const char * AMDGPUTargetLowering::getTargetNodeName ( unsigned Opcode ) const

virtual

This method returns the name of a target specific DAG node.

Reimplemented from llvm::TargetLowering.

Definition at line 800 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUISD::BRANCH_COND, llvm::ARMISD::CALL, llvm::AMDGPUISD::CONST_ADDRESS, llvm::AMDGPUISD::DIV_INF, llvm::AMDGPUISD::DWORDADDR, llvm::AMDGPUISD::EXPORT, llvm::ARMISD::FMAX, llvm::ARMISD::FMIN, llvm::AMDGPUISD::FRACT, llvm::AMDGPUISD::LOAD_CONSTANT, llvm::AMDGPUISD::LOAD_INPUT, NODE_NAME_CASE, llvm::AMDGPUISD::REGISTER_LOAD, llvm::AMDGPUISD::REGISTER_STORE, llvm::ARMISD::RET_FLAG, llvm::AMDGPUISD::SAMPLE, llvm::AMDGPUISD::SAMPLEB, llvm::AMDGPUISD::SAMPLED, llvm::AMDGPUISD::SAMPLEL, llvm::AMDGPUISD::SMAX, llvm::AMDGPUISD::SMIN, llvm::AMDGPUISD::STORE_MSKOR, llvm::AMDGPUISD::TBUFFER_STORE_FORMAT, llvm::AMDGPUISD::UMAX, llvm::AMDGPUISD::UMIN, llvm::AMDGPUISD::UMUL, and llvm::AMDGPUISD::URECIP.

bool AMDGPUTargetLowering::getTgtMemIntrinsic	(	IntrinsicInfo &	,
		const CallInst &	,
		unsigned
	)		const

virtual

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 220 of file AMDILISelLowering.cpp.

MVT AMDGPUTargetLowering::getVectorIdxTy ( ) const

virtual

Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR

Reimplemented from llvm::TargetLoweringBase.

Definition at line 195 of file AMDGPUISelLowering.cpp.

References llvm::MVT::i32.

bool AMDGPUTargetLowering::isFAbsFree ( EVT VT ) const

virtual

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 216 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f32, and llvm::EVT::isFloatingPoint().

bool AMDGPUTargetLowering::isFNegFree ( EVT VT ) const

virtual

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 221 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f32, and llvm::EVT::isFloatingPoint().

bool AMDGPUTargetLowering::isFPImmLegal	(	const APFloat &	Imm,
		EVT	VT
	)		const

virtual

We want to mark f32/f64 floating point values as legal.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 227 of file AMDILISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), and llvm::MVT::SimpleTy.

bool AMDGPUTargetLowering::isHWFalseValue ( SDValue Op ) const

protected

Definition at line 773 of file AMDGPUISelLowering.cpp.

References llvm::CallingConv::C.

Referenced by llvm::R600TargetLowering::PerformDAGCombine().

bool AMDGPUTargetLowering::isHWTrueValue ( SDValue Op ) const

protected

Definition at line 763 of file AMDGPUISelLowering.cpp.

References llvm::CallingConv::C.

Referenced by llvm::R600TargetLowering::PerformDAGCombine().

bool AMDGPUTargetLowering::isLoadBitCastBeneficial	(	EVT	,
		EVT
	)		const

virtual

isLoadBitCastBeneficial() - Return true if the following transform is beneficial. fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 199 of file AMDGPUISelLowering.cpp.

References llvm::EVT::getScalarType(), and llvm::EVT::getSizeInBits().

virtual SDValue llvm::AMDGPUTargetLowering::LowerCall	(	CallLoweringInfo &	,
		SmallVectorImpl< SDValue > &
	)		const

inlinevirtual

This hook must be implemented to lower calls into the the specified DAG. The outgoing arguments to the call are described by the Outs array, and the values to be returned by the call are described by the Ins array. The implementation should fill in the InVals array with legal-type return values from the call, and return the resulting token chain value.

Reimplemented from llvm::TargetLowering.

Definition at line 86 of file AMDGPUISelLowering.h.

References llvm::TargetLowering::CallLoweringInfo::Callee, llvm::SDValue::dump(), and llvm_unreachable.

SDValue AMDGPUTargetLowering::LowerGlobalAddress	(	AMDGPUMachineFunction *	MFI,
		SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 274 of file AMDGPUISelLowering.cpp.

References G, llvm::GlobalAddressSDNode::getAddressSpace(), llvm::SelectionDAG::getConstant(), llvm::TargetMachine::getDataLayout(), llvm::GlobalAddressSDNode::getGlobal(), llvm::GlobalAddressSDNode::getOffset(), llvm::TargetLoweringBase::getPointerTy(), llvm::TargetLoweringBase::getTargetMachine(), llvm::DataLayout::getTypeAllocSize(), llvm::AMDGPUMachineFunction::LDSSize, AMDGPUAS::LOCAL_ADDRESS, llvm::AMDGPUMachineFunction::LocalMemoryObjects, and TD.

Referenced by llvm::R600TargetLowering::LowerOperation(), and llvm::SITargetLowering::LowerOperation().

SDValue AMDGPUTargetLowering::LowerIntrinsicIABS	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

IABS(a) = SMAX(sub(0, a), a)

Definition at line 398 of file AMDGPUISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::AMDGPUISD::SMAX, and llvm::ISD::SUB.

SDValue AMDGPUTargetLowering::LowerIntrinsicLRP	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

Linear Interpolation LRP(a, b, c) = muladd(a, b, (1 - a) * c)

Definition at line 411 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f32, llvm::ISD::FADD, llvm::ISD::FMUL, llvm::ISD::FSUB, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), and llvm::SDValue::getValueType().

SDValue AMDGPUTargetLowering::LowerMinMax	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

SDValue AMDGPUTargetLowering::LowerOperation	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

virtual

This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Reimplemented from llvm::TargetLowering.

Reimplemented in llvm::SITargetLowering, and llvm::R600TargetLowering.

Definition at line 250 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BRCOND, llvm::ISD::CONCAT_VECTORS, llvm::SDNode::dump(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FrameIndex, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SDIV, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SREM, llvm::ISD::UDIVREM, and llvm::ISD::UINT_TO_FP.

Referenced by llvm::R600TargetLowering::LowerOperation(), and llvm::SITargetLowering::LowerOperation().

SDValue AMDGPUTargetLowering::LowerReturn	(	SDValue	,
		CallingConv::ID	,
		bool	,
		const SmallVectorImpl< ISD::OutputArg > &	,
		const SmallVectorImpl< SDValue > &	,
		SDLoc	,
		SelectionDAG &
	)		const

virtual

This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG. The implementation should return the resulting token chain value.

Reimplemented from llvm::TargetLowering.

Definition at line 236 of file AMDGPUISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::MVT::Other, and llvm::AMDGPUISD::RET_FLAG.