#include <TargetLowering.h>

Inheritance diagram for llvm::TargetLowering:

Collaboration diagram for llvm::TargetLowering:

Classes
struct	ArgListEntry

struct	AsmOperandInfo
	This contains information for each constraint that we are lowering. More...

struct	CallLoweringInfo

struct	DAGCombinerInfo

struct	TargetLoweringOpt

Public Types
enum	ConstraintType { C_Register, C_RegisterClass, C_Memory, C_Other, C_Unknown }

enum	ConstraintWeight { CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2, CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better, CW_Constant = CW_Best, CW_Default = CW_Okay }

typedef std::vector< ArgListEntry >	ArgListTy

typedef std::vector < AsmOperandInfo >	AsmOperandInfoVector

Public Types inherited from llvm::TargetLoweringBase
enum	LegalizeAction { Legal, Promote, Expand, Custom }

enum	LegalizeTypeAction { TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat, TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector }

enum	BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
	Enum that describes how the target represents true/false values. More...

enum	SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
	Enum that describes what type of support for selects the target has. More...

typedef std::pair < LegalizeTypeAction, EVT >	LegalizeKind

Public Member Functions
	TargetLowering (const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)
	NOTE: The constructor takes ownership of TLOF. More...

virtual bool	getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const

virtual bool	getPostIndexedAddressParts (SDNode , SDNode , SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const

virtual unsigned	getJumpTableEncoding () const

virtual const MCExpr *	LowerCustomJumpTableEntry (const MachineJumpTableInfo , const MachineBasicBlock , unsigned, MCContext &) const

virtual SDValue	getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
	Returns relocation base for the given PIC jumptable. More...

virtual const MCExpr *	getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const

virtual bool	isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const

bool	isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const

void	softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const

std::pair< SDValue, SDValue >	makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
	Returns a pair of (return value, chain). More...

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const

virtual void	computeMaskedBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const

virtual unsigned	ComputeNumSignBitsForTargetNode (SDValue Op, unsigned Depth=0) const

SDValue	SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const

virtual bool	isGAPlusOffset (SDNode N, const GlobalValue &GA, int64_t &Offset) const

virtual SDValue	PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const

virtual bool	isTypeDesirableForOp (unsigned, EVT VT) const

virtual bool	isDesirableToTransformToIntegerOp (unsigned, EVT) const

virtual bool	IsDesirableToPromoteOp (SDValue, EVT &) const

virtual SDValue	LowerFormalArguments (SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, SDLoc, SelectionDAG &, SmallVectorImpl< SDValue > &) const

std::pair< SDValue, SDValue >	LowerCallTo (CallLoweringInfo &CLI) const

virtual SDValue	LowerCall (CallLoweringInfo &, SmallVectorImpl< SDValue > &) const

virtual void	HandleByVal (CCState *, unsigned &, unsigned) const
	Target-specific cleanup for formal ByVal parameters. More...

virtual bool	CanLowerReturn (CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const

virtual SDValue	LowerReturn (SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, SDLoc, SelectionDAG &) const

virtual bool	isUsedByReturnOnly (SDNode *, SDValue &) const

virtual bool	mayBeEmittedAsTailCall (CallInst *) const

virtual MVT	getTypeForExtArgOrReturn (MVT VT, ISD::NodeType) const

virtual const uint16_t *	getScratchRegisters (CallingConv::ID CC) const

virtual void	LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const

virtual SDValue	LowerOperation (SDValue Op, SelectionDAG &DAG) const

virtual void	ReplaceNodeResults (SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const

virtual const char *	getTargetNodeName (unsigned Opcode) const
	This method returns the name of a target specific DAG node. More...

virtual FastISel *	createFastISel (FunctionLoweringInfo &, const TargetLibraryInfo *) const

virtual bool	ExpandInlineAsm (CallInst *) const

virtual AsmOperandInfoVector	ParseConstraints (ImmutableCallSite CS) const

virtual ConstraintWeight	getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const

virtual ConstraintWeight	getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const

virtual void	ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=0) const

virtual ConstraintType	getConstraintType (const std::string &Constraint) const
	Given a constraint, return the type of constraint it is for this target. More...

virtual std::pair< unsigned, const TargetRegisterClass * >	getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const

virtual const char *	LowerXConstraint (EVT ConstraintVT) const

virtual void	LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const

SDValue	BuildExactSDIV (SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const
	Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant. More...

SDValue	BuildSDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode > *Created) const
	Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...

SDValue	BuildUDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode > *Created) const
	Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...

virtual MachineBasicBlock *	EmitInstrWithCustomInserter (MachineInstr MI, MachineBasicBlock MBB) const

virtual void	AdjustInstrPostInstrSelection (MachineInstr MI, SDNode Node) const

Public Member Functions inherited from llvm::TargetLoweringBase
	TargetLoweringBase (const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)
	NOTE: The constructor takes ownership of TLOF. More...

virtual	~TargetLoweringBase ()

const TargetMachine &	getTargetMachine () const

const DataLayout *	getDataLayout () const

const TargetLoweringObjectFile &	getObjFileLowering () const

bool	isBigEndian () const

bool	isLittleEndian () const

virtual MVT	getPointerTy (uint32_t=0) const

unsigned	getPointerSizeInBits (uint32_t AS=0) const

unsigned	getPointerTypeSizeInBits (Type *Ty) const

virtual MVT	getScalarShiftAmountTy (EVT LHSTy) const

EVT	getShiftAmountTy (EVT LHSTy) const

virtual MVT	getVectorIdxTy () const

bool	isSelectExpensive () const
	Return true if the select operation is expensive for this target. More...

virtual bool	isSelectSupported (SelectSupportKind) const

virtual bool	shouldSplitVectorElementType (EVT) const

bool	isIntDivCheap () const

bool	isSlowDivBypassed () const
	Returns true if target has indicated at least one type should be bypassed. More...

const DenseMap< unsigned int, unsigned int > &	getBypassSlowDivWidths () const

bool	isPow2DivCheap () const
	Return true if pow2 div is cheaper than a chain of srl/add/sra. More...

bool	isJumpExpensive () const

bool	isPredictableSelectExpensive () const

virtual bool	isLoadBitCastBeneficial (EVT, EVT) const

virtual EVT	getSetCCResultType (LLVMContext &Context, EVT VT) const

virtual MVT::SimpleValueType	getCmpLibcallReturnType () const

BooleanContent	getBooleanContents (bool isVec) const

Sched::Preference	getSchedulingPreference () const
	Return target scheduling preference. More...

virtual Sched::Preference	getSchedulingPreference (SDNode *) const

virtual const TargetRegisterClass *	getRegClassFor (MVT VT) const

virtual const TargetRegisterClass *	getRepRegClassFor (MVT VT) const

virtual uint8_t	getRepRegClassCostFor (MVT VT) const

bool	isTypeLegal (EVT VT) const

const ValueTypeActionImpl &	getValueTypeActions () const

LegalizeTypeAction	getTypeAction (LLVMContext &Context, EVT VT) const

LegalizeTypeAction	getTypeAction (MVT VT) const

EVT	getTypeToTransformTo (LLVMContext &Context, EVT VT) const

EVT	getTypeToExpandTo (LLVMContext &Context, EVT VT) const

unsigned	getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const

virtual bool	getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, unsigned) const

virtual bool	isFPImmLegal (const APFloat &, EVT) const

virtual bool	isShuffleMaskLegal (const SmallVectorImpl< int > &, EVT) const

virtual bool	canOpTrap (unsigned Op, EVT VT) const

virtual bool	isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const

LegalizeAction	getOperationAction (unsigned Op, EVT VT) const

bool	isOperationLegalOrCustom (unsigned Op, EVT VT) const

bool	isOperationLegalOrPromote (unsigned Op, EVT VT) const

bool	isOperationExpand (unsigned Op, EVT VT) const

bool	isOperationLegal (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target. More...

LegalizeAction	getLoadExtAction (unsigned ExtType, MVT VT) const

bool	isLoadExtLegal (unsigned ExtType, EVT VT) const
	Return true if the specified load with extension is legal on this target. More...

LegalizeAction	getTruncStoreAction (MVT ValVT, MVT MemVT) const

bool	isTruncStoreLegal (EVT ValVT, EVT MemVT) const

LegalizeAction	getIndexedLoadAction (unsigned IdxMode, MVT VT) const

bool	isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getIndexedStoreAction (unsigned IdxMode, MVT VT) const

bool	isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getCondCodeAction (ISD::CondCode CC, MVT VT) const

bool	isCondCodeLegal (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal on this target. More...

MVT	getTypeToPromoteTo (unsigned Op, MVT VT) const

EVT	getValueType (Type *Ty, bool AllowUnknown=false) const

MVT	getSimpleValueType (Type *Ty, bool AllowUnknown=false) const
	Return the MVT corresponding to this LLVM type. See getValueType. More...

virtual unsigned	getByValTypeAlignment (Type *Ty) const

MVT	getRegisterType (MVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

MVT	getRegisterType (LLVMContext &Context, EVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

unsigned	getNumRegisters (LLVMContext &Context, EVT VT) const

virtual bool	ShouldShrinkFPConstant (EVT) const

bool	hasTargetDAGCombine (ISD::NodeType NT) const

unsigned	getMaxStoresPerMemset (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memset. More...

unsigned	getMaxStoresPerMemcpy (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memcpy. More...

unsigned	getMaxStoresPerMemmove (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memmove. More...

virtual bool	allowsUnalignedMemoryAccesses (EVT, bool *=0) const
	Determine if the target supports unaligned memory accesses. More...

virtual EVT	getOptimalMemOpType (uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const

virtual bool	isSafeMemOpType (MVT) const

bool	usesUnderscoreSetJmp () const
	Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...

bool	usesUnderscoreLongJmp () const
	Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...

bool	supportJumpTables () const
	Return whether the target can generate code for jump tables. More...

int	getMinimumJumpTableEntries () const

unsigned	getStackPointerRegisterToSaveRestore () const

unsigned	getExceptionPointerRegister () const

unsigned	getExceptionSelectorRegister () const

unsigned	getJumpBufSize () const

unsigned	getJumpBufAlignment () const

unsigned	getMinStackArgumentAlignment () const
	Return the minimum stack alignment of an argument. More...

unsigned	getMinFunctionAlignment () const
	Return the minimum function alignment. More...

unsigned	getPrefFunctionAlignment () const
	Return the preferred function alignment. More...

unsigned	getPrefLoopAlignment () const
	Return the preferred loop alignment. More...

bool	getInsertFencesForAtomic () const

virtual bool	getStackCookieLocation (unsigned &, unsigned &) const

virtual unsigned	getMaximalGlobalOffset () const

virtual bool	isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
	Returns true if a cast between SrcAS and DestAS is a noop. More...

virtual void	resetOperationActions ()
	Reset the operation actions based on target options. More...

virtual bool	GetAddrModeArguments (IntrinsicInst , SmallVectorImpl< Value > &, Type *&) const

virtual bool	isLegalAddressingMode (const AddrMode &AM, Type *Ty) const

virtual int	getScalingFactorCost (const AddrMode &AM, Type *Ty) const
	Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...

virtual bool	isLegalICmpImmediate (int64_t) const

virtual bool	isLegalAddImmediate (int64_t) const

virtual bool	isTruncateFree (Type , Type ) const

virtual bool	allowTruncateForTailCall (Type , Type ) const

virtual bool	isTruncateFree (EVT, EVT) const

virtual bool	isZExtFree (Type , Type ) const

virtual bool	isZExtFree (EVT, EVT) const

virtual bool	hasPairedLoad (Type *, unsigned &) const

virtual bool	hasPairedLoad (EVT, unsigned &) const

virtual bool	isZExtFree (SDValue Val, EVT VT2) const

virtual bool	isFNegFree (EVT VT) const

virtual bool	isFAbsFree (EVT VT) const

virtual bool	isFMAFasterThanFMulAndFAdd (EVT) const

virtual bool	isNarrowingProfitable (EVT, EVT) const

void	setLibcallName (RTLIB::Libcall Call, const char *Name)
	Rename the default libcall routine name for the specified libcall. More...

const char *	getLibcallName (RTLIB::Libcall Call) const
	Get the libcall routine name for the specified libcall. More...

void	setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)

ISD::CondCode	getCmpLibcallCC (RTLIB::Libcall Call) const

void	setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
	Set the CallingConv that should be used for the specified libcall. More...

CallingConv::ID	getLibcallCallingConv (RTLIB::Libcall Call) const
	Get the CallingConv that should be used for the specified libcall. More...

LegalizeKind	getTypeConversion (LLVMContext &Context, EVT VT) const

int	InstructionOpcodeToISD (unsigned Opcode) const
	Get the ISD node that corresponds to the Instruction class opcode. More...

std::pair< unsigned, MVT >	getTypeLegalizationCost (Type *Ty) const
	Estimate the cost of type-legalization and the legalized type. More...

Additional Inherited Members
Static Public Member Functions inherited from llvm::TargetLoweringBase
static ISD::NodeType	getExtendForContent (BooleanContent Content)

Protected Member Functions inherited from llvm::TargetLoweringBase
void	initActions ()
	Initialize all of the actions to default values. More...

void	setBooleanContents (BooleanContent Ty)

void	setBooleanVectorContents (BooleanContent Ty)

void	setSchedulingPreference (Sched::Preference Pref)
	Specify the target scheduling preference. More...

void	setUseUnderscoreSetJmp (bool Val)

void	setUseUnderscoreLongJmp (bool Val)

void	setSupportJumpTables (bool Val)
	Indicate whether the target can generate code for jump tables. More...

void	setMinimumJumpTableEntries (int Val)

void	setStackPointerRegisterToSaveRestore (unsigned R)

void	setExceptionPointerRegister (unsigned R)

void	setExceptionSelectorRegister (unsigned R)

void	setSelectIsExpensive (bool isExpensive=true)

void	setJumpIsExpensive (bool isExpensive=true)

void	setIntDivIsCheap (bool isCheap=true)

void	addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
	Tells the code generator which bitwidths to bypass. More...

void	setPow2DivIsCheap (bool isCheap=true)

void	addRegisterClass (MVT VT, const TargetRegisterClass *RC)

void	clearRegisterClasses ()
	Remove all register classes. More...

void	clearOperationActions ()
	Remove all operation actions. More...

virtual std::pair< const TargetRegisterClass *, uint8_t >	findRepresentativeClass (MVT VT) const

void	computeRegisterProperties ()

void	setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)

void	setLoadExtAction (unsigned ExtType, MVT VT, LegalizeAction Action)

void	setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)

void	setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)

void	setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)

void	setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)

void	AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)

void	setTargetDAGCombine (ISD::NodeType NT)

void	setJumpBufSize (unsigned Size)
	Set the target's required jmp_buf buffer size (in bytes); default is 200. More...

void	setJumpBufAlignment (unsigned Align)

void	setMinFunctionAlignment (unsigned Align)
	Set the target's minimum function alignment (in log2(bytes)) More...

void	setPrefFunctionAlignment (unsigned Align)

void	setPrefLoopAlignment (unsigned Align)

void	setMinStackArgumentAlignment (unsigned Align)
	Set the minimum stack alignment of an argument (in log2(bytes)). More...

void	setInsertFencesForAtomic (bool fence)

bool	isLegalRC (const TargetRegisterClass *RC) const

Protected Attributes inherited from llvm::TargetLoweringBase
unsigned	MaxStoresPerMemset
	Specify maximum number of store instructions per memset call. More...

unsigned	MaxStoresPerMemsetOptSize

unsigned	MaxStoresPerMemcpy
	Specify maximum bytes of store instructions per memcpy call. More...

unsigned	MaxStoresPerMemcpyOptSize

unsigned	MaxStoresPerMemmove
	Specify maximum bytes of store instructions per memmove call. More...

unsigned	MaxStoresPerMemmoveOptSize

bool	PredictableSelectIsExpensive

Detailed Description

This class defines information used to lower LLVM code to legal SelectionDAG operators that the target instruction selector can accept natively.

This class also defines callbacks that targets must implement to lower target-specific constructs to SelectionDAG operators.

Definition at line 1695 of file TargetLowering.h.

Member Typedef Documentation

typedef std::vector<ArgListEntry> llvm::TargetLowering::ArgListTy

Definition at line 1943 of file TargetLowering.h.

typedef std::vector<AsmOperandInfo> llvm::TargetLowering::AsmOperandInfoVector

Definition at line 2210 of file TargetLowering.h.

Member Enumeration Documentation

enum llvm::TargetLowering::ConstraintType

Enumerator
C_Register
C_RegisterClass
C_Memory
C_Other
C_Unknown

Definition at line 2142 of file TargetLowering.h.

enum llvm::TargetLowering::ConstraintWeight

Enumerator
CW_Invalid
CW_Okay
CW_Good
CW_Better
CW_Best
CW_SpecificReg
CW_Register
CW_Memory
CW_Constant
CW_Default

Definition at line 2150 of file TargetLowering.h.

Constructor & Destructor Documentation

TargetLowering::TargetLowering	(	const TargetMachine &	TM,
		const TargetLoweringObjectFile *	TLOF
	)

explicit

NOTE: The constructor takes ownership of TLOF.

Definition at line 37 of file TargetLowering.cpp.

Member Function Documentation

void TargetLowering::AdjustInstrPostInstrSelection	(	MachineInstr *	MI,
		SDNode *	Node
	)		const

virtual

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. These instructions must be adjusted after instruction selection by target hooks. e.g. To fill in optional defs for ARM 's' setting instructions.

Reimplemented in llvm::ARMTargetLowering, and llvm::SITargetLowering.

Definition at line 306 of file SelectionDAGISel.cpp.

References llvm::MachineInstr::hasPostISelHook().

SDValue TargetLowering::BuildExactSDIV	(	SDValue	Op1,
		SDValue	Op2,
		SDLoc	dl,
		SelectionDAG &	DAG
	)		const

Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant.

Definition at line 2512 of file TargetLowering.cpp.

References llvm::CallingConv::C, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::SDValue::getValueType(), llvm::ISD::MUL, and llvm::ISD::SRA.

SDValue TargetLowering::BuildSDIV	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	IsAfterLegalization,
		std::vector< SDNode * > *	Created
	)		const

Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html

Definition at line 2541 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::APInt::isNegative(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::APInt::isStrictlyPositive(), llvm::TargetLoweringBase::isTypeLegal(), llvm::APInt::ms::m, llvm::APInt::magic(), llvm::ISD::MULHS, llvm::APInt::ms::s, llvm::ISD::SMUL_LOHI, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::SUB.

SDValue TargetLowering::BuildUDIV	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	IsAfterLegalization,
		std::vector< SDNode * > *	Created
	)		const

Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html

Definition at line 2601 of file TargetLowering.cpp.

References llvm::APInt::mu::a, llvm::ISD::ADD, llvm::APInt::countTrailingZeros(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isTypeLegal(), llvm::APInt::lshr(), llvm::APInt::mu::m, llvm::APInt::magicu(), llvm::ISD::MULHU, llvm::APInt::mu::s, llvm::ISD::SRL, llvm::ISD::SUB, and llvm::ISD::UMUL_LOHI.

virtual bool llvm::TargetLowering::CanLowerReturn	(	CallingConv::ID	,
		MachineFunction &	,
		bool	,
		const SmallVectorImpl< ISD::OutputArg > &	,
		LLVMContext &
	)		const

inlinevirtual

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers. If false is returned, an sret-demotion is performed.

Definition at line 2026 of file TargetLowering.h.

Referenced by llvm::SelectionDAGBuilder::LowerCallTo(), and llvm::FunctionLoweringInfo::set().

void TargetLowering::ComputeConstraintToUse	(	AsmOperandInfo &	OpInfo,
		SDValue	Op,
		SelectionDAG *	DAG = `0`
	)		const

virtual

Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand being passed in is available, it can be passed in as Op, otherwise an empty SDValue can be passed.

ComputeConstraintToUse - Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.

Definition at line 2477 of file TargetLowering.cpp.

References llvm::TargetLowering::AsmOperandInfo::CallOperandVal, ChooseConstraint(), llvm::InlineAsm::ConstraintInfo::Codes, llvm::TargetLowering::AsmOperandInfo::ConstraintCode, llvm::TargetLowering::AsmOperandInfo::ConstraintType, llvm::TargetLowering::AsmOperandInfo::ConstraintVT, getConstraintType(), and LowerXConstraint().

void TargetLowering::computeMaskedBitsForTargetNode	(	const SDValue	Op,
		APInt &	KnownZero,
		APInt &	KnownOne,
		const SelectionDAG &	DAG,
		unsigned	Depth = `0`
	)		const

virtual

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AMDGPUTargetLowering, and llvm::SparcTargetLowering.

Definition at line 1057 of file TargetLowering.cpp.

References llvm::ISD::BUILTIN_OP_END, llvm::APInt::getBitWidth(), llvm::SDValue::getOpcode(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, and llvm::ISD::INTRINSIC_WO_CHAIN.

Referenced by llvm::SelectionDAG::ComputeMaskedBits().

unsigned TargetLowering::ComputeNumSignBitsForTargetNode	(	SDValue	Op,
		unsigned	Depth = `0`
	)		const

virtual

This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

ComputeNumSignBitsForTargetNode - This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1074 of file TargetLowering.cpp.

References llvm::ISD::BUILTIN_OP_END, llvm::SDValue::getOpcode(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, and llvm::ISD::INTRINSIC_WO_CHAIN.

Referenced by llvm::SelectionDAG::ComputeNumSignBits().

virtual FastISel* llvm::TargetLowering::createFastISel	(	FunctionLoweringInfo &	,
		const TargetLibraryInfo *
	)		const

inlinevirtual

This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 2125 of file TargetLowering.h.

MachineBasicBlock * TargetLowering::EmitInstrWithCustomInserter	(	MachineInstr *	MI,
		MachineBasicBlock *	MBB
	)		const

virtual

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::MipsTargetLowering, llvm::SystemZTargetLowering, llvm::HexagonTargetLowering, llvm::MSP430TargetLowering, llvm::XCoreTargetLowering, llvm::SparcTargetLowering, llvm::SITargetLowering, llvm::MipsSETargetLowering, llvm::Mips16TargetLowering, and llvm::R600TargetLowering.

Definition at line 296 of file SelectionDAGISel.cpp.

References llvm::dbgs(), and llvm_unreachable.

Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), and INITIALIZE_PASS().

virtual bool llvm::TargetLowering::ExpandInlineAsm ( CallInst * ) const

inlinevirtual

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 2138 of file TargetLowering.h.

TargetLowering::ConstraintType TargetLowering::getConstraintType ( const std::string & Constraint ) const

virtual

Given a constraint, return the type of constraint it is for this target.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::NVPTXTargetLowering, llvm::MSP430TargetLowering, and llvm::SparcTargetLowering.

Definition at line 1943 of file TargetLowering.cpp.

References C_Memory, C_Other, C_Register, C_RegisterClass, and C_Unknown.

Referenced by ChooseConstraint(), ComputeConstraintToUse(), llvm::SparcTargetLowering::getConstraintType(), llvm::MSP430TargetLowering::getConstraintType(), llvm::NVPTXTargetLowering::getConstraintType(), llvm::SystemZTargetLowering::getConstraintType(), llvm::AArch64TargetLowering::getConstraintType(), llvm::ARMTargetLowering::getConstraintType(), llvm::PPCTargetLowering::getConstraintType(), llvm::X86TargetLowering::getConstraintType(), and llvm::hasInlineAsmMemConstraint().

unsigned TargetLowering::getJumpTableEncoding ( ) const

virtual

Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

getJumpTableEncoding - Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

Reimplemented in llvm::X86TargetLowering, llvm::ARMTargetLowering, and llvm::XCoreTargetLowering.

Definition at line 221 of file TargetLowering.cpp.

References llvm::MachineJumpTableInfo::EK_BlockAddress, llvm::MachineJumpTableInfo::EK_GPRel32BlockAddress, llvm::MachineJumpTableInfo::EK_LabelDifference32, llvm::TargetLoweringBase::getTargetMachine(), and llvm::Reloc::PIC_.

Referenced by llvm::X86TargetLowering::getJumpTableEncoding(), and getPICJumpTableRelocBase().

TargetLowering::ConstraintWeight TargetLowering::getMultipleConstraintMatchWeight	(	AsmOperandInfo &	info,
		int	maIndex
	)		const

virtual

Examine constraint type and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Definition at line 2337 of file TargetLowering.cpp.

References llvm::c_str(), llvm::InlineAsm::ConstraintInfo::Codes, CW_Invalid, for(), getSingleConstraintMatchWeight(), and llvm::InlineAsm::ConstraintInfo::multipleAlternatives.

Referenced by ParseConstraints().

SDValue TargetLowering::getPICJumpTableRelocBase	(	SDValue	Table,
		SelectionDAG &	DAG
	)		const

virtual

Returns relocation base for the given PIC jumptable.

Reimplemented in llvm::X86TargetLowering.

Definition at line 234 of file TargetLowering.cpp.

References llvm::MachineJumpTableInfo::EK_GPRel32BlockAddress, llvm::MachineJumpTableInfo::EK_GPRel64BlockAddress, llvm::SelectionDAG::getGLOBAL_OFFSET_TABLE(), getJumpTableEncoding(), and llvm::TargetLoweringBase::getPointerTy().

const MCExpr * TargetLowering::getPICJumpTableRelocBaseExpr	(	const MachineFunction *	MF,
		unsigned	JTI,
		MCContext &	Ctx
	)		const

virtual

This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

getPICJumpTableRelocBaseExpr - This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

Reimplemented in llvm::X86TargetLowering.

Definition at line 250 of file TargetLowering.cpp.

References llvm::MCSymbolRefExpr::Create(), and llvm::MachineFunction::getJTISymbol().

Referenced by llvm::AsmPrinter::EmitJumpTableInfo(), and llvm::X86TargetLowering::getPICJumpTableRelocBaseExpr().

virtual bool llvm::TargetLowering::getPostIndexedAddressParts	(	SDNode *	,
		SDNode *	,
		SDValue &	,
		SDValue &	,
		ISD::MemIndexedMode &	,
		SelectionDAG &
	)		const

inlinevirtual

Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

Reimplemented in llvm::ARMTargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1717 of file TargetLowering.h.

virtual bool llvm::TargetLowering::getPreIndexedAddressParts	(	SDNode *	,
		SDValue &	,
		SDValue &	,
		ISD::MemIndexedMode &	,
		SelectionDAG &
	)		const

inlinevirtual

Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

Reimplemented in llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 1707 of file TargetLowering.h.

std::pair< unsigned, const TargetRegisterClass * > TargetLowering::getRegForInlineAsmConstraint	(	const std::string &	Constraint,
		MVT	VT
	)		const

virtual

Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register.

Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.

This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer..

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::HexagonTargetLowering, llvm::NVPTXTargetLowering, llvm::MSP430TargetLowering, and llvm::SparcTargetLowering.

Definition at line 2062 of file TargetLowering.cpp.

References llvm::TargetRegisterClass::begin(), llvm::TargetRegisterClass::end(), llvm::MCRegisterInfo::getName(), llvm::TargetMachine::getRegisterInfo(), llvm::TargetLoweringBase::getTargetMachine(), llvm::TargetRegisterClass::hasType(), I, llvm::TargetLoweringBase::isLegalRC(), llvm::TargetRegisterInfo::regclass_begin(), and llvm::TargetRegisterInfo::regclass_end().

virtual const uint16_t* llvm::TargetLowering::getScratchRegisters ( CallingConv::ID CC ) const

inlinevirtual

Returns a 0 terminated array of registers that can be safely used as scratch registers.

Definition at line 2077 of file TargetLowering.h.

TargetLowering::ConstraintWeight TargetLowering::getSingleConstraintMatchWeight	(	AsmOperandInfo &	info,
		const char *	constraint
	)		const

virtual

Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::SystemZTargetLowering.

Definition at line 2361 of file TargetLowering.cpp.

References llvm::TargetLowering::AsmOperandInfo::CallOperandVal, CW_Constant, CW_Default, CW_Invalid, CW_Memory, CW_Register, llvm::Value::getType(), and llvm::Type::isIntegerTy().

Referenced by getMultipleConstraintMatchWeight(), llvm::SystemZTargetLowering::getSingleConstraintMatchWeight(), llvm::ARMTargetLowering::getSingleConstraintMatchWeight(), llvm::PPCTargetLowering::getSingleConstraintMatchWeight(), and llvm::X86TargetLowering::getSingleConstraintMatchWeight().

const char * TargetLowering::getTargetNodeName ( unsigned Opcode ) const

virtual

This method returns the name of a target specific DAG node.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::MipsTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, llvm::XCoreTargetLowering, llvm::HexagonTargetLowering, llvm::AMDGPUTargetLowering, llvm::NVPTXTargetLowering, llvm::MSP430TargetLowering, and llvm::SparcTargetLowering.

Definition at line 41 of file TargetLowering.cpp.

Referenced by llvm::SDNode::getOperationName().

virtual MVT llvm::TargetLowering::getTypeForExtArgOrReturn	(	MVT	VT,
		ISD::NodeType
	)		const

inlinevirtual

Return the type that should be used to zero or sign extend a zeroext/signext integer argument or return value. FIXME: Most C calling convention requires the return type to be promoted, but this is not true all the time, e.g. i1 on x86-64. It is also not necessary for non-C calling conventions. The frontend should handle this and include all of the necessary information.

Definition at line 2069 of file TargetLowering.h.

References llvm::MVT::bitsLT(), llvm::TargetLoweringBase::getRegisterType(), and llvm::MVT::i32.

virtual void llvm::TargetLowering::HandleByVal	(	CCState *	,
		unsigned &	,
		unsigned
	)		const

inlinevirtual

Target-specific cleanup for formal ByVal parameters.

Definition at line 2021 of file TargetLowering.h.

Referenced by llvm::CCState::HandleByVal().

virtual bool llvm::TargetLowering::IsDesirableToPromoteOp	(	SDValue	,
		EVT &
	)		const

inlinevirtual

This method query the target whether it is beneficial for dag combiner to promote the specified node. If true, it should return the desired promotion type by reference.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1902 of file TargetLowering.h.

virtual bool llvm::TargetLowering::isDesirableToTransformToIntegerOp	(	unsigned	,
		EVT
	)		const

inlinevirtual

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. e.g. f32 load -> i32 load can be profitable on ARM.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 1894 of file TargetLowering.h.

bool TargetLowering::isGAPlusOffset	(	SDNode *	N,
		const GlobalValue *&	GA,
		int64_t &	Offset
	)		const

virtual

Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1900 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::dyn_cast(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SDValue::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getSExtValue(), and N.

Referenced by llvm::SelectionDAG::InferPtrAlignment(), llvm::SelectionDAG::isConsecutiveLoad(), isConsecutiveLS(), and llvm::X86TargetLowering::isGAPlusOffset().

bool TargetLowering::isInTailCallPosition	(	SelectionDAG &	DAG,
		SDNode *	Node,
		SDValue &	Chain
	)		const

Check whether a given call node is in tail position within its function. If so, it sets Chain to the input chain of the tail call.

Definition at line 47 of file TargetLowering.cpp.

References F(), llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::AttributeSet::hasAttribute(), isUsedByReturnOnly(), llvm::Attribute::NoAlias, llvm::Attribute::SExt, and llvm::Attribute::ZExt.

Referenced by llvm::AArch64TargetLowering::LowerF128ToCall().

bool TargetLowering::isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const

virtual

Return true if folding a constant offset with the given GlobalAddress is legal. It is frequently not legal in PIC relocation models.

Reimplemented in llvm::PPCTargetLowering, llvm::ARMTargetLowering, and llvm::SparcTargetLowering.

Definition at line 257 of file TargetLowering.cpp.

References llvm::Reloc::DynamicNoPIC, llvm::GlobalAddressSDNode::getGlobal(), llvm::TargetLoweringBase::getTargetMachine(), llvm::GlobalValue::isDeclaration(), llvm::GlobalValue::isWeakForLinker(), and llvm::Reloc::Static.

virtual bool llvm::TargetLowering::isTypeDesirableForOp	(	unsigned	,
		EVT	VT
	)		const

inlinevirtual

Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1886 of file TargetLowering.h.

References llvm::TargetLoweringBase::isTypeLegal().

Referenced by SimplifyDemandedBits(), and SimplifySetCC().

virtual bool llvm::TargetLowering::isUsedByReturnOnly	(	SDNode *	,
		SDValue &
	)		const

inlinevirtual

Return true if result of the specified node is used by a return node only. It also compute and return the input chain for the tail call.

This is used to determine whether it is possible to codegen a libcall as tail call at legalization time.

Definition at line 2052 of file TargetLowering.h.

Referenced by isInTailCallPosition().

void TargetLowering::LowerAsmOperandForConstraint	(	SDValue	Op,
		std::string &	Constraint,
		std::vector< SDValue > &	Ops,
		SelectionDAG &	DAG
	)		const

virtual

Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, llvm::SystemZTargetLowering, and llvm::NVPTXTargetLowering.

Definition at line 1996 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BasicBlock, llvm::CallingConv::C, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), and llvm::MVT::i64.

Referenced by ChooseConstraint(), llvm::NVPTXTargetLowering::LowerAsmOperandForConstraint(), llvm::SystemZTargetLowering::LowerAsmOperandForConstraint(), llvm::AArch64TargetLowering::LowerAsmOperandForConstraint(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::PPCTargetLowering::LowerAsmOperandForConstraint(), and llvm::X86TargetLowering::LowerAsmOperandForConstraint().

virtual SDValue llvm::TargetLowering::LowerCall	(	CallLoweringInfo &	,
		SmallVectorImpl< SDValue > &
	)		const

inlinevirtual

This hook must be implemented to lower calls into the the specified DAG. The outgoing arguments to the call are described by the Outs array, and the values to be returned by the call are described by the Ins array. The implementation should fill in the InVals array with legal-type return values from the call, and return the resulting token chain value.

Reimplemented in llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::NVPTXTargetLowering, llvm::HexagonTargetLowering, llvm::SparcTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 2015 of file TargetLowering.h.

References llvm_unreachable.

Referenced by LowerCallTo().

std::pair< SDValue, SDValue > TargetLowering::LowerCallTo ( TargetLowering::CallLoweringInfo & CLI ) const

This function lowers an abstract call to a function into an actual call. This returns a pair of operands. The first element is the return value for the function (if RetTy is not VoidTy). The second element is the outgoing token chain. It calls LowerCall to do the actual lowering.

TargetLowering::LowerCallTo - This is the default LowerCallTo implementation, which just calls LowerCall. FIXME: When all targets are migrated to using LowerCall, this hook should be integrated into SDISel.

Definition at line 6991 of file SelectionDAGBuilder.cpp.

Referenced by llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), llvm::SelectionDAGBuilder::LowerCallOperands(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::AArch64TargetLowering::LowerF128ToCall(), LowerFSINCOS(), and makeLibCall().

virtual const MCExpr* llvm::TargetLowering::LowerCustomJumpTableEntry	(	const MachineJumpTableInfo *	,
		const MachineBasicBlock *	,
		unsigned	,
		MCContext &
	)		const

inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 1730 of file TargetLowering.h.

References llvm_unreachable.

virtual SDValue llvm::TargetLowering::LowerFormalArguments	(	SDValue	,
		CallingConv::ID	,
		bool	,
		const SmallVectorImpl< ISD::InputArg > &	,
		SDLoc	,
		SelectionDAG &	,
		SmallVectorImpl< SDValue > &
	)		const

inlinevirtual

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG. The implementation should fill in the InVals array with legal-type argument values, and return the resulting token chain value.

Reimplemented in llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::NVPTXTargetLowering, llvm::HexagonTargetLowering, llvm::SparcTargetLowering, llvm::SITargetLowering, and llvm::R600TargetLowering.

Definition at line 1917 of file TargetLowering.h.

References llvm_unreachable.

SDValue TargetLowering::LowerOperation	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

virtual

This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, llvm::MipsTargetLowering, llvm::HexagonTargetLowering, llvm::XCoreTargetLowering, llvm::AMDGPUTargetLowering, llvm::NVPTXTargetLowering, llvm::MSP430TargetLowering, llvm::SITargetLowering, llvm::SparcTargetLowering, llvm::MipsSETargetLowering, and llvm::R600TargetLowering.

Definition at line 7174 of file SelectionDAGBuilder.cpp.

References llvm_unreachable.

Referenced by LowerOperationWrapper().

void TargetLowering::LowerOperationWrapper	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG
	)		const

virtual

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. It replaces the LowerOperation callback in the type Legalizer. The reason we can not do away with LowerOperation entirely is that LegalizeDAG isn't yet ready to use this callback.

TODO: Consider merging with ReplaceNodeResults.

The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all. The default implementation calls LowerOperation.

Reimplemented in llvm::MipsTargetLowering.

Definition at line 7166 of file SelectionDAGBuilder.cpp.

References llvm::SDValue::getNode(), LowerOperation(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

virtual SDValue llvm::TargetLowering::LowerReturn	(	SDValue	,
		CallingConv::ID	,
		bool	,
		const SmallVectorImpl< ISD::OutputArg > &	,
		const SmallVectorImpl< SDValue > &	,
		SDLoc	,
		SelectionDAG &
	)		const

inlinevirtual

This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG. The implementation should return the resulting token chain value.

Reimplemented in llvm::SystemZTargetLowering, llvm::AArch64TargetLowering, llvm::HexagonTargetLowering, llvm::NVPTXTargetLowering, llvm::SparcTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 2039 of file TargetLowering.h.

References llvm_unreachable.

const char * TargetLowering::LowerXConstraint ( EVT ConstraintVT ) const

virtual

Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. This returns null if there is no replacement to make.

LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.

Reimplemented in llvm::X86TargetLowering.

Definition at line 1986 of file TargetLowering.cpp.

References llvm::EVT::isFloatingPoint(), and llvm::EVT::isInteger().

Referenced by ComputeConstraintToUse(), and llvm::X86TargetLowering::LowerXConstraint().

std::pair< SDValue, SDValue > TargetLowering::makeLibCall	(	SelectionDAG &	DAG,
		RTLIB::Libcall	LC,
		EVT	RetVT,
		const SDValue *	Ops,
		unsigned	NumOps,
		bool	isSigned,
		SDLoc	dl,
		bool	doesNotReturn = `false`,
		bool	isReturnValueUsed = `true`
	)		const

Returns a pair of (return value, chain).

Generate a libcall taking the given operands as arguments and returning a result of type RetVT.

Definition at line 84 of file TargetLowering.cpp.

References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getExternalSymbol(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::TargetLowering::ArgListEntry::isSExt, llvm::TargetLowering::ArgListEntry::isZExt, LowerCallTo(), llvm::TargetLowering::ArgListEntry::Node, and llvm::TargetLowering::ArgListEntry::Ty.

Referenced by llvm::AArch64TargetLowering::LowerFP_ROUND(), softenSetCCOperands(), and llvm::SelectionDAGBuilder::visitSPDescriptorFailure().

virtual bool llvm::TargetLowering::mayBeEmittedAsTailCall ( CallInst * ) const

inlinevirtual

Return true if the target may be able emit the call instruction as a tail call. This is used by optimization passes to determine if it's profitable to duplicate return instructions to enable tailcall optimization.

Reimplemented in llvm::SystemZTargetLowering.

Definition at line 2059 of file TargetLowering.h.

TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints ( ImmutableCallSite CS ) const

virtual

Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

ParseConstraints - Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

ConstraintOperands - Information about all of the constraints.

Definition at line 2128 of file TargetLowering.cpp.

References llvm::TargetLowering::AsmOperandInfo::CallOperandVal, llvm::TargetLowering::AsmOperandInfo::ConstraintCode, llvm::TargetLowering::AsmOperandInfo::ConstraintVT, llvm::dyn_cast(), llvm::IntegerType::get(), llvm::CallSiteBase< FunTy, ValTy, UserTy, InstrTy, CallTy, InvokeTy, IterTy >::getArgument(), llvm::CallSiteBase< FunTy, ValTy, UserTy, InstrTy, CallTy, InvokeTy, IterTy >::getCalledValue(), llvm::Type::getContext(), llvm::TargetLoweringBase::getDataLayout(), llvm::SequentialType::getElementType(), llvm::MVT::getIntegerVT(), getMultipleConstraintMatchWeight(), llvm::DataLayout::getPointerSizeInBits(), getRegForInlineAsmConstraint(), llvm::TargetLoweringBase::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::Value::getType(), llvm::CallSiteBase< FunTy, ValTy, UserTy, InstrTy, CallTy, InvokeTy, IterTy >::getType(), llvm::DataLayout::getTypeSizeInBits(), llvm::MVT::getVT(), llvm::InlineAsm::ConstraintInfo::hasMatchingInput(), llvm::InlineAsm::isClobber, llvm::InlineAsm::ConstraintInfo::isIndirect, llvm::InlineAsm::isInput, llvm::MVT::isInteger(), llvm::InlineAsm::isOutput, llvm::Type::isSingleValueType(), llvm::Type::isSized(), llvm::Type::isVoidTy(), llvm::InlineAsm::ConstraintInfo::MatchingInput, llvm::InlineAsm::ConstraintInfo::multipleAlternatives, llvm::MVT::Other, llvm::InlineAsm::ParseConstraints(), llvm::report_fatal_error(), llvm::InlineAsm::ConstraintInfo::selectAlternative(), and llvm::InlineAsm::ConstraintInfo::Type.

SDValue TargetLowering::PerformDAGCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

virtual

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::MipsTargetLowering, llvm::SITargetLowering, llvm::MipsSETargetLowering, and llvm::R600TargetLowering.

Definition at line 1932 of file TargetLowering.cpp.

virtual void llvm::TargetLowering::ReplaceNodeResults	(	SDNode *	,
		SmallVectorImpl< SDValue > &	,
		SelectionDAG &
	)		const

inlinevirtual

This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type. The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all.

If the target has no operations that require custom lowering, it need not implement this. The default implementation aborts.

Reimplemented in llvm::X86TargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::MipsTargetLowering, llvm::SparcTargetLowering, llvm::XCoreTargetLowering, and llvm::R600TargetLowering.

Definition at line 2114 of file TargetLowering.h.

References llvm_unreachable.

bool TargetLowering::SimplifyDemandedBits	(	SDValue	Op,
		const APInt &	DemandedMask,
		APInt &	KnownZero,
		APInt &	KnownOne,
		TargetLoweringOpt &	TLO,
		unsigned	Depth = `0`
	)		const

Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.

SimplifyDemandedBits - Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.

Definition at line 367 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::AssertZext, llvm::ISD::BITCAST, llvm::CallingConv::C, llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::SelectionDAG::ComputeMaskedBits(), llvm::ISD::Constant, llvm::TargetLowering::TargetLoweringOpt::DAG, llvm::dyn_cast(), llvm::APInt::exactLogBase2(), llvm::ISD::FGETSIGN, llvm::APInt::getAllOnesValue(), llvm::APInt::getBitsSet(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::APInt::getSignBit(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::tgtok::In, llvm::APInt::intersects(), llvm::APInt::isAllOnesValue(), llvm::EVT::isFloatingPoint(), llvm::isIntN(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isSimple(), isTypeDesirableForOp(), llvm::EVT::isVector(), llvm::APInt::lshr(), llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SHL, llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::APInt::trunc(), llvm::Intrinsic::trunc, llvm::ISD::TRUNCATE, llvm::ISD::UNDEF, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zext().

Referenced by PerformSELECTCombine().

SDValue TargetLowering::SimplifySetCC	(	EVT	VT,
		SDValue	N0,
		SDValue	N1,
		ISD::CondCode	Cond,
		bool	foldBooleans,
		DAGCombinerInfo &	DCI,
		SDLoc	dl
	)		const

Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.

SimplifySetCC - Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.

Definition at line 1121 of file TargetLowering.cpp.

Referenced by llvm::SITargetLowering::PerformDAGCombine().

void TargetLowering::softenSetCCOperands	(	SelectionDAG &	DAG,
		EVT	VT,
		SDValue &	NewLHS,
		SDValue &	NewRHS,
		ISD::CondCode &	CCCode,
		SDLoc	dl
	)		const

SoftenSetCCOperands - Soften the operands of a comparison. This code is shared among BR_CC, SELECT_CC, and SETCC handlers.

Definition at line 116 of file TargetLowering.cpp.

References llvm::MVT::f128, llvm::MVT::f32, llvm::MVT::f64, llvm::TargetLoweringBase::getCmpLibcallCC(), llvm::TargetLoweringBase::getCmpLibcallReturnType(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::SDValue::getValueType(), llvm_unreachable, makeLibCall(), llvm::RTLIB::O_F128, llvm::RTLIB::O_F32, llvm::RTLIB::O_F64, llvm::RTLIB::OEQ_F128, llvm::RTLIB::OEQ_F32, llvm::RTLIB::OEQ_F64, llvm::RTLIB::OGE_F128, llvm::RTLIB::OGE_F32, llvm::RTLIB::OGE_F64, llvm::RTLIB::OGT_F128, llvm::RTLIB::OGT_F32, llvm::RTLIB::OGT_F64, llvm::RTLIB::OLE_F128, llvm::RTLIB::OLE_F32, llvm::RTLIB::OLE_F64, llvm::RTLIB::OLT_F128, llvm::RTLIB::OLT_F32, llvm::RTLIB::OLT_F64, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::RTLIB::UNE_F128, llvm::RTLIB::UNE_F32, llvm::RTLIB::UNE_F64, llvm::RTLIB::UNKNOWN_LIBCALL, llvm::RTLIB::UO_F128, llvm::RTLIB::UO_F32, and llvm::RTLIB::UO_F64.

Referenced by llvm::AArch64TargetLowering::LowerBR_CC(), llvm::AArch64TargetLowering::LowerSELECT_CC(), and llvm::AArch64TargetLowering::LowerSETCC().

The documentation for this class was generated from the following files:

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