LLVM API Documentation
#include "AArch64.h"
#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64TargetMachine.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
#include <algorithm>
#include "AArch64GenInstrInfo.inc"
Go to the source code of this file.
Macros | |
#define | GET_INSTRINFO_CTOR_DTOR |
Functions | |
static bool | isCondBranch (unsigned Opc) |
static void | classifyCondBranch (MachineInstr *I, MachineBasicBlock *&TBB, SmallVectorImpl< MachineOperand > &Cond) |
#define GET_INSTRINFO_CTOR_DTOR |
Definition at line 32 of file AArch64InstrInfo.cpp.
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static |
Takes apart a given conditional branch MachineInstr (see isCondBranch), setting TBB to the destination basic block and populating the Cond vector with data necessary to recreate the conditional branch at a later date. First element will be the opcode, and subsequent ones define the conditions being branched on in an instruction-specific manner.
Definition at line 161 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::CreateImm(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm_unreachable, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::AArch64InstrInfo::AnalyzeBranch().
Does the Opcode represent a conditional branch that we can remove and re-add at the end of a basic block?
Definition at line 149 of file AArch64InstrInfo.cpp.
Referenced by llvm::AArch64InstrInfo::AnalyzeBranch(), and llvm::AArch64InstrInfo::RemoveBranch().