#include <MachineInstr.h>

Inheritance diagram for llvm::MachineInstr:

Collaboration diagram for llvm::MachineInstr:

Public Types
enum	CommentFlag { ReloadReuse = 0x1 }

enum	MIFlag { NoFlags = 0, FrameSetup = 1 << 0, BundledPred = 1 << 1, BundledSucc = 1 << 2 }

enum	QueryType { IgnoreBundle, AnyInBundle, AllInBundle }

enum	MICheckType { CheckDefs, CheckKillDead, IgnoreDefs, IgnoreVRegDefs }

typedef MachineMemOperand **	mmo_iterator

typedef MachineOperand *	mop_iterator
	iterator/begin/end - Iterate over all operands of a machine instruction. More...

typedef const MachineOperand *	const_mop_iterator

Public Member Functions
const MachineBasicBlock *	getParent () const

MachineBasicBlock *	getParent ()

uint8_t	getAsmPrinterFlags () const

void	clearAsmPrinterFlags ()

bool	getAsmPrinterFlag (CommentFlag Flag) const

void	setAsmPrinterFlag (CommentFlag Flag)

void	clearAsmPrinterFlag (CommentFlag Flag)

uint8_t	getFlags () const
	getFlags - Return the MI flags bitvector. More...

bool	getFlag (MIFlag Flag) const
	getFlag - Return whether an MI flag is set. More...

void	setFlag (MIFlag Flag)
	setFlag - Set a MI flag. More...

void	setFlags (unsigned flags)

void	clearFlag (MIFlag Flag)
	clearFlag - Clear a MI flag. More...

bool	isInsideBundle () const

bool	isBundled () const

bool	isBundledWithPred () const

bool	isBundledWithSucc () const

void	bundleWithPred ()

void	bundleWithSucc ()

void	unbundleFromPred ()
	Break bundle above this instruction. More...

void	unbundleFromSucc ()
	Break bundle below this instruction. More...

DebugLoc	getDebugLoc () const

void	emitError (StringRef Msg) const

const MCInstrDesc &	getDesc () const

int	getOpcode () const

unsigned	getNumOperands () const

const MachineOperand &	getOperand (unsigned i) const

MachineOperand &	getOperand (unsigned i)

unsigned	getNumExplicitOperands () const

mop_iterator	operands_begin ()

mop_iterator	operands_end ()

const_mop_iterator	operands_begin () const

const_mop_iterator	operands_end () const

mmo_iterator	memoperands_begin () const
	Access to memory operands of the instruction. More...

mmo_iterator	memoperands_end () const

bool	memoperands_empty () const

bool	hasOneMemOperand () const

bool	hasProperty (unsigned MCFlag, QueryType Type=AnyInBundle) const

bool	isVariadic (QueryType Type=IgnoreBundle) const

bool	hasOptionalDef (QueryType Type=IgnoreBundle) const

bool	isPseudo (QueryType Type=IgnoreBundle) const

bool	isReturn (QueryType Type=AnyInBundle) const

bool	isCall (QueryType Type=AnyInBundle) const

bool	isBarrier (QueryType Type=AnyInBundle) const

bool	isTerminator (QueryType Type=AnyInBundle) const

bool	isBranch (QueryType Type=AnyInBundle) const

bool	isIndirectBranch (QueryType Type=AnyInBundle) const

bool	isConditionalBranch (QueryType Type=AnyInBundle) const

bool	isUnconditionalBranch (QueryType Type=AnyInBundle) const

bool	isPredicable (QueryType Type=AllInBundle) const

bool	isCompare (QueryType Type=IgnoreBundle) const
	isCompare - Return true if this instruction is a comparison. More...

bool	isMoveImmediate (QueryType Type=IgnoreBundle) const

bool	isBitcast (QueryType Type=IgnoreBundle) const

bool	isSelect (QueryType Type=IgnoreBundle) const

bool	isNotDuplicable (QueryType Type=AnyInBundle) const

bool	hasDelaySlot (QueryType Type=AnyInBundle) const

bool	canFoldAsLoad (QueryType Type=IgnoreBundle) const

bool	mayLoad (QueryType Type=AnyInBundle) const

bool	mayStore (QueryType Type=AnyInBundle) const

bool	isCommutable (QueryType Type=IgnoreBundle) const

bool	isConvertibleTo3Addr (QueryType Type=IgnoreBundle) const

bool	usesCustomInsertionHook (QueryType Type=IgnoreBundle) const

bool	hasPostISelHook (QueryType Type=IgnoreBundle) const

bool	isRematerializable (QueryType Type=AllInBundle) const

bool	isAsCheapAsAMove (QueryType Type=AllInBundle) const

bool	hasExtraSrcRegAllocReq (QueryType Type=AnyInBundle) const

bool	hasExtraDefRegAllocReq (QueryType Type=AnyInBundle) const

bool	isIdenticalTo (const MachineInstr *Other, MICheckType Check=CheckDefs) const

MachineInstr *	removeFromParent ()

MachineInstr *	removeFromBundle ()

void	eraseFromParent ()

void	eraseFromBundle ()

bool	isLabel () const

bool	isPrologLabel () const

bool	isEHLabel () const

bool	isGCLabel () const

bool	isDebugValue () const

bool	isIndirectDebugValue () const

bool	isPHI () const

bool	isKill () const

bool	isImplicitDef () const

bool	isInlineAsm () const

bool	isMSInlineAsm () const

bool	isStackAligningInlineAsm () const

InlineAsm::AsmDialect	getInlineAsmDialect () const

bool	isInsertSubreg () const

bool	isSubregToReg () const

bool	isRegSequence () const

bool	isBundle () const

bool	isCopy () const

bool	isFullCopy () const

bool	isCopyLike () const

bool	isIdentityCopy () const
	isIdentityCopy - Return true is the instruction is an identity copy. More...

bool	isTransient () const

unsigned	getBundleSize () const

bool	readsRegister (unsigned Reg, const TargetRegisterInfo *TRI=NULL) const

bool	readsVirtualRegister (unsigned Reg) const

std::pair< bool, bool >	readsWritesVirtualRegister (unsigned Reg, SmallVectorImpl< unsigned > *Ops=0) const

bool	killsRegister (unsigned Reg, const TargetRegisterInfo *TRI=NULL) const

bool	definesRegister (unsigned Reg, const TargetRegisterInfo *TRI=NULL) const

bool	modifiesRegister (unsigned Reg, const TargetRegisterInfo *TRI) const

bool	registerDefIsDead (unsigned Reg, const TargetRegisterInfo *TRI=NULL) const

int	findRegisterUseOperandIdx (unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=NULL) const

MachineOperand *	findRegisterUseOperand (unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=NULL)

int	findRegisterDefOperandIdx (unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=NULL) const

MachineOperand *	findRegisterDefOperand (unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=NULL)

int	findFirstPredOperandIdx () const

int	findInlineAsmFlagIdx (unsigned OpIdx, unsigned *GroupNo=0) const

const TargetRegisterClass *	getRegClassConstraint (unsigned OpIdx, const TargetInstrInfo TII, const TargetRegisterInfo TRI) const

void	tieOperands (unsigned DefIdx, unsigned UseIdx)

unsigned	findTiedOperandIdx (unsigned OpIdx) const

bool	isRegTiedToUseOperand (unsigned DefOpIdx, unsigned *UseOpIdx=0) const

bool	isRegTiedToDefOperand (unsigned UseOpIdx, unsigned *DefOpIdx=0) const

void	clearKillInfo ()

void	substituteRegister (unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)

bool	addRegisterKilled (unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

void	clearRegisterKills (unsigned Reg, const TargetRegisterInfo *RegInfo)

bool	addRegisterDead (unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)

void	addRegisterDefined (unsigned Reg, const TargetRegisterInfo *RegInfo=0)

void	setPhysRegsDeadExcept (ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)

bool	isSafeToMove (const TargetInstrInfo TII, AliasAnalysis AA, bool &SawStore) const

bool	hasOrderedMemoryRef () const

bool	isInvariantLoad (AliasAnalysis *AA) const

unsigned	isConstantValuePHI () const

bool	hasUnmodeledSideEffects () const

bool	allDefsAreDead () const

void	copyImplicitOps (MachineFunction &MF, const MachineInstr *MI)

void	print (raw_ostream &OS, const TargetMachine *TM=0, bool SkipOpers=false) const

void	dump () const

void	addOperand (MachineFunction &MF, const MachineOperand &Op)

void	addOperand (const MachineOperand &Op)

void	setDesc (const MCInstrDesc &tid)

void	setDebugLoc (const DebugLoc dl)

void	RemoveOperand (unsigned i)

void	addMemOperand (MachineFunction &MF, MachineMemOperand *MO)

void	setMemRefs (mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)

Public Member Functions inherited from llvm::ilist_node< MachineInstr >
MachineInstr *	getPrevNode ()
	Get the previous node, or 0 for the list head. More...

const MachineInstr *	getPrevNode () const
	Get the previous node, or 0 for the list head. More...

MachineInstr *	getNextNode ()
	Get the next node, or 0 for the list tail. More...

const MachineInstr *	getNextNode () const
	Get the next node, or 0 for the list tail. More...

Friends
struct	ilist_traits< MachineInstr >

struct	ilist_traits< MachineBasicBlock >

class	MachineFunction

Additional Inherited Members
Protected Member Functions inherited from llvm::ilist_node< MachineInstr >
	ilist_node ()

Detailed Description

MachineInstr - Representation of each machine instruction.

This class isn't a POD type, but it must have a trivial destructor. When a MachineFunction is deleted, all the contained MachineInstrs are deallocated without having their destructor called.

Definition at line 50 of file MachineInstr.h.

Member Typedef Documentation

typedef const MachineOperand* llvm::MachineInstr::const_mop_iterator

Definition at line 282 of file MachineInstr.h.

typedef MachineMemOperand** llvm::MachineInstr::mmo_iterator

Definition at line 52 of file MachineInstr.h.

typedef MachineOperand* llvm::MachineInstr::mop_iterator

iterator/begin/end - Iterate over all operands of a machine instruction.

Definition at line 281 of file MachineInstr.h.

Member Enumeration Documentation

enum llvm::MachineInstr::CommentFlag

Flags to specify different kinds of comments to output in assembly code. These flags carry semantic information not otherwise easily derivable from the IR text.

Enumerator
ReloadReuse

Definition at line 58 of file MachineInstr.h.

enum llvm::MachineInstr::MICheckType

Enumerator
CheckDefs
CheckKillDead
IgnoreDefs
IgnoreVRegDefs

Definition at line 587 of file MachineInstr.h.

enum llvm::MachineInstr::MIFlag

Enumerator
NoFlags
FrameSetup
BundledPred
BundledSucc

Definition at line 62 of file MachineInstr.h.

enum llvm::MachineInstr::QueryType

API for querying MachineInstr properties. They are the same as MCInstrDesc queries but they are bundle aware.

Enumerator
IgnoreBundle
AnyInBundle
AllInBundle

Definition at line 304 of file MachineInstr.h.

Member Function Documentation

void MachineInstr::addMemOperand	(	MachineFunction &	MF,
		MachineMemOperand *	MO
	)

addMemOperand - Add a MachineMemOperand to the machine instruction. This function should be used only occasionally. The setMemRefs function is the primary method for setting up a MachineInstr's MemRefs list.

Definition at line 744 of file MachineInstr.cpp.

References llvm::MachineFunction::allocateMemRefsArray().

Referenced by llvm::MachineInstrBuilder::addMemOperand(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::PPCInstrInfo::loadRegFromStackSlot(), and llvm::PPCInstrInfo::storeRegToStackSlot().

void MachineInstr::addOperand	(	MachineFunction &	MF,
		const MachineOperand &	Op
	)

Add the specified operand to the instruction. If it is an implicit operand, it is added to the end of the operand list. If it is an explicit operand it is added at the end of the explicit operand list (before the first implicit operand).

MF must be the machine function that was used to allocate this instruction.

MachineInstrBuilder provides a more convenient interface for creating instructions and adding operands.

addOperand - Add the specified operand to the instruction. If it is an implicit operand, it is added to the end of the operand list. If it is an explicit operand it is added at the end of the explicit operand list (before the first implicit operand).

Definition at line 622 of file MachineInstr.cpp.

void MachineInstr::addOperand ( const MachineOperand & Op )

Add an operand without providing an MF reference. This only works for instructions that are inserted in a basic block.

MachineInstrBuilder and the two-argument addOperand(MF, MO) should be preferred.

Definition at line 593 of file MachineInstr.cpp.

bool MachineInstr::addRegisterDead	(	unsigned	Reg,
		const TargetRegisterInfo *	RegInfo,
		bool	AddIfNotFound = `false`
	)

addRegisterDead - We have determined MI defined a register without a use. Look for the operand that defines it and mark it as IsDead. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.

Definition at line 1708 of file MachineInstr.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::MachineOperand::CreateReg(), llvm::SmallVectorBase::empty(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImplicit(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MCRegisterInfo::isSubRegister(), llvm::MCRegisterInfo::isSuperRegister(), llvm::MCRegAliasIterator::isValid(), llvm::SmallVectorTemplateBase< T, isPodLike >::pop_back(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::MachineOperand::setIsDead().

Referenced by llvm::LiveVariables::addVirtualRegisterDead(), and llvm::LiveIntervals::shrinkToUses().

void MachineInstr::addRegisterDefined	(	unsigned	Reg,
		const TargetRegisterInfo *	RegInfo = `0`
	)

addRegisterDefined - We have determined MI defines a register. Make sure there is an operand defining Reg.

Definition at line 1760 of file MachineInstr.cpp.

References llvm::MachineOperand::CreateReg(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), and llvm::MachineOperand::isReg().

Referenced by llvm::SparcInstrInfo::copyPhysReg(), and llvm::ARMBaseInstrInfo::copyPhysReg().

bool MachineInstr::addRegisterKilled	(	unsigned	IncomingReg,
		const TargetRegisterInfo *	RegInfo,
		bool	AddIfNotFound = `false`
	)

addRegisterKilled - We have determined MI kills a register. Look for the operand that uses it and mark it as IsKill. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.

Definition at line 1635 of file MachineInstr.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::MachineOperand::CreateReg(), llvm::SmallVectorBase::empty(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MCRegisterInfo::isSubRegister(), llvm::MCRegisterInfo::isSuperRegister(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), llvm::MCRegAliasIterator::isValid(), llvm::SmallVectorTemplateBase< T, isPodLike >::pop_back(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::MachineOperand::setIsKill().

Referenced by llvm::LiveIntervals::addKillFlags(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), llvm::SparcInstrInfo::copyPhysReg(), and llvm::ARMBaseInstrInfo::copyPhysReg().

bool MachineInstr::allDefsAreDead ( ) const

allDefsAreDead - Return true if all the defs of this instruction are dead.

Definition at line 1357 of file MachineInstr.cpp.

References llvm::MachineOperand::isDead(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isUse().

Referenced by llvm::LiveIntervals::shrinkToUses().

void MachineInstr::bundleWithPred ( )

Bundle this instruction with its predecessor. This can be an unbundled instruction, or it can be the first instruction in a bundle.

Definition at line 871 of file MachineInstr.cpp.

Referenced by llvm::MIBundleBuilder::insert(), and llvm::MIBundleBuilder::MIBundleBuilder().

void MachineInstr::bundleWithSucc ( )

Bundle this instruction with its successor. This can be an unbundled instruction, or it can be the last instruction in a bundle.

Definition at line 880 of file MachineInstr.cpp.

Referenced by llvm::MIBundleBuilder::insert().

bool llvm::MachineInstr::canFoldAsLoad ( QueryType Type = IgnoreBundle ) const

inline

canFoldAsLoad - Return true for instructions that can be folded as memory operands in other instructions. The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.

Definition at line 454 of file MachineInstr.h.

References llvm::MCID::FoldableAsLoad, and hasProperty().

Referenced by llvm::TargetInstrInfo::foldMemoryOperand().

void llvm::MachineInstr::clearAsmPrinterFlag ( CommentFlag Flag )

inline

clearAsmPrinterFlag - clear specific AsmPrinter flags

Definition at line 144 of file MachineInstr.h.

void llvm::MachineInstr::clearAsmPrinterFlags ( )

inline

clearAsmPrinterFlags - clear the AsmPrinter bitvector

Definition at line 128 of file MachineInstr.h.

void llvm::MachineInstr::clearFlag ( MIFlag Flag )

inline

clearFlag - Clear a MI flag.

Definition at line 170 of file MachineInstr.h.

Referenced by llvm::MachineBasicBlock::remove_instr().

void MachineInstr::clearKillInfo ( )

clearKillInfo - Clears kill flags on all operands.

Definition at line 1194 of file MachineInstr.cpp.

References llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), and llvm::MachineOperand::setIsKill().

void MachineInstr::clearRegisterKills	(	unsigned	Reg,
		const TargetRegisterInfo *	RegInfo
	)

clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is provided, this includes super-register kills.

Definition at line 1694 of file MachineInstr.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MCRegisterInfo::isSuperRegister(), llvm::MachineOperand::isUse(), and llvm::MachineOperand::setIsKill().

Referenced by llvm::LiveIntervals::addKillFlags().

void MachineInstr::copyImplicitOps	(	MachineFunction &	MF,
		const MachineInstr *	MI
	)

copyImplicitOps - Copy implicit register operands from specified instruction to this instruction.

Definition at line 1370 of file MachineInstr.cpp.

References getDesc(), llvm::MCInstrDesc::getNumOperands(), getNumOperands(), getOperand(), llvm::MachineOperand::isImplicit(), and llvm::MachineOperand::isReg().

Referenced by llvm::MachineInstrBuilder::copyImplicitOps(), llvm::HexagonFrameLowering::emitEpilogue(), and llvm::X86FrameLowering::emitEpilogue().

bool llvm::MachineInstr::definesRegister	(	unsigned	Reg,
		const TargetRegisterInfo *	TRI = `NULL`
	)		const

inline

definesRegister - Return true if the MachineInstr fully defines the specified register. If TargetRegisterInfo is passed, then it also checks if there is a def of a super-register. NOTE: It's ignoring subreg indices on virtual registers.

Definition at line 753 of file MachineInstr.h.

References findRegisterDefOperandIdx().

Referenced by checkAndUpdateEFLAGSKill(), getImplicitSPRUseForDPRUse(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), and llvm::PPCInstrInfo::optimizeCompareInstr().

void MachineInstr::dump ( ) const

Definition at line 1380 of file MachineInstr.cpp.

References llvm::dbgs().

Referenced by llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), llvm::ScheduleDAGInstrs::dumpNode(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::HexagonLowerToMC(), llvm::MSP430MCInstLower::Lower(), llvm::LowerPPCMachineInstrToMCInst(), and llvm::AggressiveAntiDepBreaker::Observe().

void MachineInstr::emitError ( StringRef Msg ) const

emitError - Emit an error referring to the source location of this instruction. This should only be used for inline assembly that is somehow impossible to compile. Other errors should have been handled much earlier.

If this method returns, the caller should try to recover from the error.

Definition at line 1827 of file MachineInstr.cpp.

References llvm::MachineOperand::CI, llvm::MachineOperand::getMetadata(), llvm::MDNode::getNumOperands(), llvm::MDNode::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::ConstantInt::getZExtValue(), llvm::MachineOperand::isMetadata(), llvm::MachineOperand::MBB, and llvm::report_fatal_error().

Referenced by llvm::RegAllocBase::allocatePhysRegs().

void MachineInstr::eraseFromBundle ( )

Unlink 'this' form its basic block and delete it.

If the instruction is part of a bundle, the other instructions in the bundle remain bundled.

Definition at line 851 of file MachineInstr.cpp.

References llvm::MachineOperand::getParent().

void MachineInstr::eraseFromParent ( )

Unlink 'this' from the containing basic block and delete it.

If this instruction is the header of a bundle, the whole bundle is erased. This function can not be used for instructions inside a bundle, use eraseFromBundle() to erase individual bundled instructions.

Definition at line 846 of file MachineInstr.cpp.

References llvm::MachineOperand::getParent().

int MachineInstr::findFirstPredOperandIdx ( ) const

findFirstPredOperandIdx() - Find the index of the first operand in the operand list that is used to represent the predicate. It returns -1 if none is found.

Definition at line 1082 of file MachineInstr.cpp.

References llvm::MCInstrDesc::isPredicable(), llvm::MCOperandInfo::isPredicate(), and llvm::MCInstrDesc::OpInfo.

Referenced by llvm::ARMBaseInstrInfo::commuteInstruction(), llvm::Thumb1RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::getInstrPredicate(), llvm::ARMBaseInstrInfo::getPredicate(), llvm::ARMBaseInstrInfo::isPredicated(), llvm::R600InstrInfo::isPredicated(), llvm::ARMBaseInstrInfo::PredicateInstruction(), and llvm::R600InstrInfo::PredicateInstruction().

int MachineInstr::findInlineAsmFlagIdx	(	unsigned	OpIdx,
		unsigned *	GroupNo = `0`
	)		const

findInlineAsmFlagIdx() - Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instruction. Returns -1 if getOperand(OpIdx) does not belong to an inline asm operand group.

If GroupNo is not NULL, it will receive the number of the operand group containing OpIdx.

The flag operand is an immediate that can be decoded with methods like InlineAsm::hasRegClassConstraint().

Definition at line 922 of file MachineInstr.cpp.

References llvm::MachineOperand::getImm(), llvm::InlineAsm::getNumOperandRegisters(), and llvm::MachineOperand::isImm().

MachineOperand* llvm::MachineInstr::findRegisterDefOperand	(	unsigned	Reg,
		bool	isDead = `false`,
		const TargetRegisterInfo *	TRI = `NULL`
	)

inline

findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an index.

Definition at line 798 of file MachineInstr.h.

References findRegisterDefOperandIdx(), and getOperand().

Referenced by llvm::AggressiveAntiDepBreaker::BreakAntiDependencies().

int MachineInstr::findRegisterDefOperandIdx	(	unsigned	Reg,
		bool	isDead = `false`,
		bool	Overlap = `false`,
		const TargetRegisterInfo *	TRI = `NULL`
	)		const

findRegisterDefOperandIdx() - Returns the operand index that is a def of the specified register or -1 if it is not found. If isDead is true, defs that are not dead are skipped. If Overlap is true, then it also looks for defs that merely overlap the specified register. If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register. This may also return a register mask operand when Overlap is true.

findRegisterDefOperandIdx() - Returns the operand index that is a def of the specified register or -1 if it is not found. If isDead is true, defs that are not dead are skipped. If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register.

Definition at line 1053 of file MachineInstr.cpp.

References llvm::MachineOperand::clobbersPhysReg(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MCRegisterInfo::isSubRegister(), llvm::MachineOperand::Reg, and llvm::TargetRegisterInfo::regsOverlap().

Referenced by llvm::ScheduleDAGInstrs::addVRegUseDeps(), llvm::R600InstrInfo::definesAddressRegister(), definesRegister(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), findRegisterDefOperand(), modifiesRegister(), and registerDefIsDead().

MachineOperand* llvm::MachineInstr::findRegisterUseOperand	(	unsigned	Reg,
		bool	isKill = `false`,
		const TargetRegisterInfo *	TRI = `NULL`
	)

inline

findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an index.

Definition at line 780 of file MachineInstr.h.

References findRegisterUseOperandIdx(), getOperand(), and isKill().

int MachineInstr::findRegisterUseOperandIdx	(	unsigned	Reg,
		bool	isKill = `false`,
		const TargetRegisterInfo *	TRI = `NULL`
	)		const

findRegisterUseOperandIdx() - Returns the operand index that is a use of the specific register or -1 if it is not found. It further tightens the search criteria to a use that kills the register if isKill is true.

findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of the specific register or -1 if it is not found. It further tightens the search criteria to a use that kills the register if isKill is true.

Definition at line 1000 of file MachineInstr.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MCRegisterInfo::isSubRegister(), and llvm::MachineOperand::isUse().

Referenced by findRegisterUseOperand(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), killsRegister(), readsRegister(), and llvm::R600InstrInfo::usesAddressRegister().

unsigned MachineInstr::findTiedOperandIdx ( unsigned OpIdx ) const

findTiedOperandIdx - Given the index of a tied register operand, find the operand it is tied to. Defs are tied to uses and vice versa. Returns the index of the tied operand which must exist.

Given the index of a tied register operand, find the operand it is tied to. Defs are tied to uses and vice versa. Returns the index of the tied operand which must exist.

Definition at line 1137 of file MachineInstr.cpp.

References llvm::MachineOperand::getImm(), llvm::InlineAsm::getNumOperandRegisters(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), llvm::MachineOperand::isUse(), llvm::InlineAsm::isUseOperandTiedToDef(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by isRegTiedToDefOperand(), and isRegTiedToUseOperand().

bool llvm::MachineInstr::getAsmPrinterFlag ( CommentFlag Flag ) const

inline

getAsmPrinterFlag - Return whether an AsmPrinter flag is set.

Definition at line 132 of file MachineInstr.h.

Referenced by emitComments().

uint8_t llvm::MachineInstr::getAsmPrinterFlags ( ) const

inline

getAsmPrinterFlags - Return the asm printer flags bitvector.

Definition at line 124 of file MachineInstr.h.

unsigned MachineInstr::getBundleSize ( ) const

Return the number of instructions inside the MI bundle, excluding the bundle header.

This is the number of instructions that MachineBasicBlock::iterator skips, 0 for unbundled instructions.

Return the number of instructions inside the MI bundle, not counting the header instruction.

Definition at line 989 of file MachineInstr.cpp.

References I.

Referenced by llvm::HexagonAsmPrinter::EmitInstruction().

DebugLoc llvm::MachineInstr::getDebugLoc ( ) const

inline

getDebugLoc - Returns the debug location id of this MachineInstr.

Definition at line 244 of file MachineInstr.h.

Referenced by llvm::DwarfDebug::beginFunction(), llvm::DwarfDebug::beginInstruction(), llvm::X86InstrInfo::classifyLEAReg(), llvm::PPCInstrInfo::commuteInstruction(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::SparcFrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::PPCFrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::Thumb1RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::AArch64TargetLowering::emitAtomicBinary(), llvm::PPCTargetLowering::EmitAtomicBinary(), llvm::AArch64TargetLowering::emitAtomicBinaryMinMax(), llvm::AArch64TargetLowering::emitAtomicCmpSwap(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::AArch64TargetLowering::EmitF128CSEL(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::SparcTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::NVPTXAsmPrinter::emitLineNumberAsDotLoc(), EmitMonitor(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), EmitPCMPSTRI(), EmitPCMPSTRM(), llvm::MSP430TargetLowering::EmitShiftInstr(), EmitXBegin(), llvm::AArch64InstrInfo::expandPostRAPseudo(), expandPseudoDIV(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), forceReg(), FuseInst(), FuseTwoAddrInst(), HandleVRSaveUpdate(), isIdenticalTo(), llvm::SIInstrInfo::legalizeOperands(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), MakeM0Inst(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), llvm::Thumb1RegisterInfo::rewriteFrameIndex(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::ARMBaseInstrInfo::setExecutionDomain(), and llvm::X86InstrInfo::unfoldMemoryOperand().

const MCInstrDesc& llvm::MachineInstr::getDesc ( ) const

inline

getDesc - Returns the target instruction descriptor of this MachineInstr.

Definition at line 257 of file MachineInstr.h.

bool llvm::MachineInstr::getFlag ( MIFlag Flag ) const

inline

getFlag - Return whether an MI flag is set.

Definition at line 154 of file MachineInstr.h.

Referenced by llvm::DwarfDebug::beginFunction(), llvm::ARMAsmPrinter::EmitInstruction(), isBundledWithPred(), isBundledWithSucc(), and isInsideBundle().

uint8_t llvm::MachineInstr::getFlags ( ) const

inline

getFlags - Return the MI flags bitvector.

Definition at line 149 of file MachineInstr.h.

InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect ( ) const

Definition at line 916 of file MachineInstr.cpp.

Referenced by isMSInlineAsm().

unsigned MachineInstr::getNumExplicitOperands ( ) const

getNumExplicitOperands - Returns the number of non-implicit operands.

Definition at line 858 of file MachineInstr.cpp.

References llvm::MachineOperand::isImplicit(), and llvm::MachineOperand::isReg().

Referenced by llvm::SystemZInstrInfo::analyzeCompare(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), isCompareZero(), and llvm::AMDGPUMCInstLower::lower().

unsigned llvm::MachineInstr::getNumOperands ( ) const

inline

Access to explicit operands of the instruction.

Definition at line 265 of file MachineInstr.h.

Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::DwarfDebug::beginFunction(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::DwarfException::CallToNoUnwindFunction(), canFoldCopy(), canFoldIntoMOVCC(), clobbersCTR(), llvm::SIInstrInfo::commuteInstruction(), llvm::AMDGPUInstrInfo::convertToISA(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), copyImplicitOps(), definesCPSR(), llvm::ARMBaseInstrInfo::DefinesPredicate(), llvm::HexagonInstrInfo::DefinesPredicate(), llvm::PPCInstrInfo::DefinesPredicate(), emitDebugValueComment(), EmitGCCInlineAsmStr(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), emitKill(), EmitMSInlineAsmStr(), EmitPCMPSTRI(), EmitPCMPSTRM(), llvm::AMDGPUAsmPrinter::EmitProgramInfoR600(), llvm::AMDGPUAsmPrinter::EmitProgramInfoSI(), findCorrespondingPred(), finishConvertToThreeAddress(), llvm::PPCInstrInfo::FoldImmediate(), foldPatchpoint(), FuseInst(), FuseTwoAddrInst(), getDebugLocEntry(), llvm::MachineInstrExpressionTrait::getHashValue(), getLSMultipleTransferSize(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::ARMBaseInstrInfo::getNumMicroOps(), getOperand(), getPHIDeps(), getPHISrcRegOpIdx(), GetPostIncrementOperand(), getRegsUsedByPHIs(), GetStoreValueOperand(), HandleVRSaveUpdate(), HashMachineInstr(), hasLiveCondCodeDef(), hasVGPROperands(), hasYmmReg(), llvm::HexagonLowerToMC(), INITIALIZE_PASS(), isCSRestore(), isDbgValueInDefinedReg(), isIdenticalTo(), llvm::isLeaMem(), llvm::isMem(), isMemoryOp(), isSourceDefinedByImplicitDef(), llvm::ARMBaseInstrInfo::isSwiftFastImmShift(), isTwoAddrUse(), llvm::SIInstrInfo::legalizeOperands(), llvm::XCoreMCInstLower::Lower(), llvm::MipsMCInstLower::Lower(), llvm::SystemZMCInstLower::lower(), llvm::MSP430MCInstLower::Lower(), llvm::LowerAArch64MachineInstrToMCInst(), llvm::LowerARMMachineInstrToMCInst(), llvm::LowerPPCMachineInstrToMCInst(), MaySpeculate(), llvm::SIInstrInfo::moveToVALU(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::PatchPointOpers::PatchPointOpers(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), removeKillInfo(), removeOperands(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::Thumb1RegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), resultTests(), llvm::rewriteT2FrameIndex(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::LiveVariables::runOnMachineFunction(), TrackDefUses(), llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), llvm::tryFoldSPUpdateIntoPushPop(), llvm::X86InstrInfo::unfoldMemoryOperand(), UpdateCPSRDef(), UpdateCPSRUse(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::ValueIsNewPHI(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), and llvm::MachineRegisterInfo::verifyUseList().

int llvm::MachineInstr::getOpcode ( ) const

inline

getOpcode - Returns the opcode of this MachineInstr.

Definition at line 261 of file MachineInstr.h.

References llvm::MCInstrDesc::Opcode.

const MachineOperand& llvm::MachineInstr::getOperand ( unsigned i ) const

inline

Definition at line 267 of file MachineInstr.h.

References getNumOperands().

MachineOperand& llvm::MachineInstr::getOperand ( unsigned i )

inline

Definition at line 271 of file MachineInstr.h.

References getNumOperands().

const MachineBasicBlock* llvm::MachineInstr::getParent ( ) const

inline

Definition at line 119 of file MachineInstr.h.

MachineBasicBlock* llvm::MachineInstr::getParent ( )

inline

Definition at line 120 of file MachineInstr.h.

const TargetRegisterClass * MachineInstr::getRegClassConstraint	(	unsigned	OpIdx,
		const TargetInstrInfo *	TII,
		const TargetRegisterInfo *	TRI
	)		const

getRegClassConstraint - Compute the static register class constraint for operand OpIdx. For normal instructions, this is derived from the MCInstrDesc. For inline assembly it is derived from the flag words.

Returns NULL if the static register classs constraint cannot be determined.

Definition at line 951 of file MachineInstr.cpp.

References llvm::InlineAsm::getKind(), getParent(), llvm::MachineOperand::getParent(), llvm::TargetRegisterInfo::getPointerRegClass(), llvm::TargetInstrInfo::getRegClass(), llvm::TargetRegisterInfo::getRegClass(), llvm::InlineAsm::hasRegClassConstraint(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isUse().

bool llvm::MachineInstr::hasDelaySlot ( QueryType Type = AnyInBundle ) const

inline

hasDelaySlot - Returns true if the specified instruction has a delay slot which must be filled by the code generator.

Definition at line 442 of file MachineInstr.h.

References llvm::MCID::DelaySlot, and hasProperty().

Referenced by hasUnoccupiedSlot().

bool llvm::MachineInstr::hasExtraDefRegAllocReq ( QueryType Type = AnyInBundle ) const

inline

hasExtraDefRegAllocReq - Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.

Definition at line 582 of file MachineInstr.h.

References llvm::MCID::ExtraDefRegAllocReq, and hasProperty().

Referenced by llvm::CriticalAntiDepBreaker::BreakAntiDependencies().

bool llvm::MachineInstr::hasExtraSrcRegAllocReq ( QueryType Type = AnyInBundle ) const

inline

hasExtraSrcRegAllocReq - Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.

Definition at line 572 of file MachineInstr.h.

References llvm::MCID::ExtraSrcRegAllocReq, and hasProperty().

bool llvm::MachineInstr::hasOneMemOperand ( ) const

inline

hasOneMemOperand - Return true if this instruction has exactly one MachineMemOperand.

Definition at line 297 of file MachineInstr.h.

Referenced by EmitPCMPSTRI(), EmitPCMPSTRM(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::ARMBaseInstrInfo::getOperandLatency(), getUnderlyingObjectsForInstr(), isMemoryOp(), MIsNeedChainEdge(), llvm::X86InstrInfo::optimizeCompareInstr(), and llvm::X86InstrInfo::unfoldMemoryOperand().

bool llvm::MachineInstr::hasOptionalDef ( QueryType Type = IgnoreBundle ) const

inline

hasOptionalDef - Set if this instruction has an optional definition, e.g. ARM instructions which can set condition code if 's' bit is set.

Definition at line 334 of file MachineInstr.h.

References llvm::MCID::HasOptionalDef, and hasProperty().

Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), and llvm::ARMBaseInstrInfo::optimizeSelect().

bool MachineInstr::hasOrderedMemoryRef ( ) const

hasOrderedMemoryRef - Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available. Return false if it is known to have no ordered or volatile memory references.

hasOrderedMemoryRef - Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available. Return false if it is known to have no ordered memory references.

Definition at line 1263 of file MachineInstr.cpp.

References I.

Referenced by isGlobalMemoryObject().

bool llvm::MachineInstr::hasPostISelHook ( QueryType Type = IgnoreBundle ) const

inline

hasPostISelHook - Return true if this instruction requires adjustment after instruction selection by calling a target hook. For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.

Definition at line 540 of file MachineInstr.h.

References llvm::MCID::HasPostISelHook, and hasProperty().

Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), and llvm::TargetLowering::AdjustInstrPostInstrSelection().

bool llvm::MachineInstr::hasProperty	(	unsigned	MCFlag,
		QueryType	Type = `AnyInBundle`
	)		const

inline

hasProperty - Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has the specified property. The first argument is the property being queried. The second argument indicates whether the query should look inside instruction bundles.

Definition at line 315 of file MachineInstr.h.

References getDesc(), llvm::MCInstrDesc::getFlags(), IgnoreBundle, isBundled(), and isBundledWithPred().

Referenced by canFoldAsLoad(), hasDelaySlot(), hasExtraDefRegAllocReq(), hasExtraSrcRegAllocReq(), hasOptionalDef(), hasPostISelHook(), isAsCheapAsAMove(), isBarrier(), isBitcast(), isBranch(), isCall(), isCommutable(), isCompare(), isConvertibleTo3Addr(), isIndirectBranch(), isMoveImmediate(), isNotDuplicable(), isPredicable(), isPseudo(), isRematerializable(), isReturn(), isSelect(), isTerminator(), isVariadic(), mayLoad(), mayStore(), and usesCustomInsertionHook().

bool MachineInstr::hasUnmodeledSideEffects ( ) const

hasUnmodeledSideEffects - Return true if this instruction has side effects that are not modeled by mayLoad / mayStore, etc. For all instructions, the property is encoded in MCInstrDesc::Flags (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is INLINEASM instruction, in which case the side effect property is encoded in one of its operands (see InlineAsm::Extra_HasSideEffect).

Definition at line 1343 of file MachineInstr.cpp.

References llvm::MCID::UnmodeledSideEffects.

Referenced by isGlobalMemoryObject(), isUnsafeMemoryObject(), and isUnsafeToMoveAcross().

bool llvm::MachineInstr::isAsCheapAsAMove ( QueryType Type = AllInBundle ) const

inline

isAsCheapAsAMove - Returns true if this instruction has the same cost (or less) than a move instruction. This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.

Definition at line 560 of file MachineInstr.h.

References llvm::MCID::CheapAsAMove, and hasProperty().

Referenced by llvm::LiveRangeEdit::canRematerializeAt().

bool llvm::MachineInstr::isBarrier ( QueryType Type = AnyInBundle ) const

inline

isBarrier - Returns true if the specified instruction stops control flow from executing the instruction immediately following it. Examples include unconditional branches and return instructions.

Definition at line 356 of file MachineInstr.h.

References llvm::MCID::Barrier, and hasProperty().

Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), llvm::MachineBasicBlock::canFallThrough(), llvm::ARMHazardRecognizer::getHazardType(), isConditionalBranch(), isUnconditionalBranch(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::PPCInstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), and ProfitableToMerge().

bool llvm::MachineInstr::isBitcast ( QueryType Type = IgnoreBundle ) const

inline

isBitcast - Return true if this instruction is a bitcast instruction.

Definition at line 423 of file MachineInstr.h.

References llvm::MCID::Bitcast, and hasProperty().

Referenced by getCopyOrBitcastDefUseIdx().

bool llvm::MachineInstr::isBranch ( QueryType Type = AnyInBundle ) const

inline

isBranch - Returns true if this is a conditional, unconditional, or indirect branch. Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to get more information.

Definition at line 374 of file MachineInstr.h.

References llvm::MCID::Branch, and hasProperty().

Referenced by llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::AsmPrinter::isBlockOnlyReachableByFallthrough(), isConditionalBranch(), isUnconditionalBranch(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::PPCInstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), and llvm::X86InstrInfo::optimizeCompareInstr().

bool llvm::MachineInstr::isBundle ( ) const

inline

Definition at line 666 of file MachineInstr.h.

References llvm::TargetOpcode::BUNDLE, and getOpcode().

Referenced by llvm::HexagonInstrInfo::AnalyzeBranch(), llvm::TargetSchedModel::computeInstrLatency(), llvm::HexagonAsmPrinter::EmitInstruction(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::ARMBaseInstrInfo::getOperandLatency(), INITIALIZE_PASS(), llvm::ARMBaseInstrInfo::isPredicated(), and llvm::TargetInstrInfo::PredicateInstruction().

bool llvm::MachineInstr::isBundled ( ) const

inline

isBundled - Return true if this instruction part of a bundle. This is true if either itself or its following instruction is marked "InsideBundle".

Definition at line 216 of file MachineInstr.h.

References isBundledWithPred(), and isBundledWithSucc().

Referenced by llvm::LiveIntervals::handleMove(), and hasProperty().

bool llvm::MachineInstr::isBundledWithPred ( ) const

inline

Return true if this instruction is part of a bundle, and it is not the first instruction in the bundle.

Definition at line 222 of file MachineInstr.h.

References BundledPred, and getFlag().

Referenced by hasProperty(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::insertAfter(), isBundled(), and unbundleSingleMI().

bool llvm::MachineInstr::isBundledWithSucc ( ) const

inline

Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle.

Definition at line 226 of file MachineInstr.h.

References BundledSucc, and getFlag().

Referenced by hasUnoccupiedSlot(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::insertAfter(), isBundled(), and unbundleSingleMI().

bool llvm::MachineInstr::isCall ( QueryType Type = AnyInBundle ) const

inline

Definition at line 349 of file MachineInstr.h.

References llvm::MCID::Call, and hasProperty().

Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::DwarfException::CallToNoUnwindFunction(), llvm::MachineTraceMetrics::getResources(), hasYmmReg(), llvm::ScheduleDAGInstrs::initSUnits(), isGlobalMemoryObject(), and llvm::ARMBaseInstrInfo::isSchedulingBoundary().

bool llvm::MachineInstr::isCommutable ( QueryType Type = IgnoreBundle ) const

inline

isCommutable - Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.

Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.

Definition at line 502 of file MachineInstr.h.

References llvm::MCID::Commutable, and hasProperty().

Referenced by llvm::ScheduleDAGInstrs::initSUnits(), llvm::SIInstrInfo::legalizeOperands(), and llvm::X86InstrInfo::optimizeLoadInstr().

bool llvm::MachineInstr::isCompare ( QueryType Type = IgnoreBundle ) const

inline

isCompare - Return true if this instruction is a comparison.

Definition at line 411 of file MachineInstr.h.

References llvm::MCID::Compare, and hasProperty().

Referenced by llvm::SystemZInstrInfo::analyzeCompare(), lowerRIHigh(), and lowerRILow().

bool llvm::MachineInstr::isConditionalBranch ( QueryType Type = AnyInBundle ) const

inline

isConditionalBranch - Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.

Definition at line 388 of file MachineInstr.h.

References isBarrier(), isBranch(), and isIndirectBranch().

unsigned MachineInstr::isConstantValuePHI ( ) const

isConstantValuePHI - If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return 0.

Definition at line 1330 of file MachineInstr.cpp.

References llvm::MachineOperand::getReg(), and llvm::MachineOperand::Reg.

Referenced by llvm::MachineSSAUpdater::GetValueInMiddleOfBlock().

bool llvm::MachineInstr::isConvertibleTo3Addr ( QueryType Type = IgnoreBundle ) const

inline

isConvertibleTo3Addr - Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.

If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).

Definition at line 520 of file MachineInstr.h.

References llvm::MCID::ConvertibleTo3Addr, and hasProperty().

bool llvm::MachineInstr::isCopy ( ) const

inline

Definition at line 669 of file MachineInstr.h.

References llvm::TargetOpcode::COPY, and getOpcode().

Referenced by biasPhysRegCopy(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), canFoldCopy(), llvm::TargetInstrInfo::canFoldMemoryOperand(), llvm::X86InstrInfo::foldMemoryOperandImpl(), getCopyOrBitcastDefUseIdx(), INITIALIZE_PASS(), isCopyLike(), isCopyToReg(), isFullCopy(), isIdentityCopy(), isLocalCopy(), MIIsInTerminatorSequence(), and llvm::SelectionDAGISel::runOnMachineFunction().

bool llvm::MachineInstr::isCopyLike ( ) const

inline

isCopyLike - Return true if the instruction behaves like a copy. This does not include native copy instructions.

Definition at line 678 of file MachineInstr.h.

References isCopy(), and isSubregToReg().

Referenced by llvm::ARMBaseInstrInfo::getOperandLatency(), and llvm::SplitAnalysis::shouldSplitSingleBlock().

bool llvm::MachineInstr::isDebugValue ( ) const

inline

Definition at line 639 of file MachineInstr.h.

References llvm::TargetOpcode::DBG_VALUE, and getOpcode().

Referenced by llvm::DwarfDebug::beginFunction(), llvm::DwarfDebug::beginInstruction(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::RegPressureTracker::bumpDownwardPressure(), llvm::RegPressureTracker::bumpUpwardPressure(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), llvm::ConnectedVNInfoEqClasses::Distribute(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::Thumb1RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::ARMHazardRecognizer::EmitInstruction(), llvm::PPCHazardRecognizer970::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::DwarfDebug::endInstruction(), findUseBetween(), llvm::ARMHazardRecognizer::getHazardType(), llvm::PPCHazardRecognizer970::getHazardType(), llvm::ScheduleDAGInstrs::initSUnits(), llvm::SlotIndexes::insertMachineInstrInMaps(), isDbgValueInDefinedReg(), isDefLiveOut(), isIndirectDebugValue(), llvm::HexagonInstrInfo::isSchedulingBoundary(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), isUnsafeToMoveAcross(), MIIsInTerminatorSequence(), llvm::CriticalAntiDepBreaker::Observe(), llvm::SlotIndexes::repairIndexesInRange(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::LiveVariables::runOnMachineFunction(), llvm::SlotIndexes::runOnMachineFunction(), llvm::LiveIntervals::shrinkToUses(), llvm::RegScavenger::unprocess(), and llvm::AntiDepBreaker::UpdateDbgValue().

bool llvm::MachineInstr::isEHLabel ( ) const

inline

Definition at line 637 of file MachineInstr.h.

References llvm::TargetOpcode::EH_LABEL, and getOpcode().

bool llvm::MachineInstr::isFullCopy ( ) const

inline

Definition at line 672 of file MachineInstr.h.

References getOperand(), llvm::MachineOperand::getSubReg(), and isCopy().

Referenced by isFullCopyOf().

bool llvm::MachineInstr::isGCLabel ( ) const

inline

Definition at line 638 of file MachineInstr.h.

References llvm::TargetOpcode::GC_LABEL, and getOpcode().

bool MachineInstr::isIdenticalTo	(	const MachineInstr *	Other,
		MICheckType	Check = `CheckDefs`
	)		const

isIdenticalTo - Return true if this instruction is identical to (same opcode and same operands as) the specified instruction.

Definition at line 773 of file MachineInstr.cpp.

References getDebugLoc(), getNumOperands(), getOpcode(), getOperand(), getParent(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::instr_end(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), and llvm::DebugLoc::isUnknown().

Referenced by llvm::DwarfDebug::beginFunction(), llvm::MachineInstrExpressionTrait::isEqual(), llvm::ARMBaseInstrInfo::produceSameValue(), and llvm::TargetInstrInfo::produceSameValue().

bool llvm::MachineInstr::isIdentityCopy ( ) const

inline

isIdentityCopy - Return true is the instruction is an identity copy.

Definition at line 683 of file MachineInstr.h.

References getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isCopy().

Referenced by llvm::VirtRegAuxInfo::calculateSpillWeightAndHint().

bool llvm::MachineInstr::isImplicitDef ( ) const

inline

Definition at line 650 of file MachineInstr.h.

References getOpcode(), and llvm::TargetOpcode::IMPLICIT_DEF.

Referenced by llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), llvm::ARMBaseInstrInfo::getOperandLatency(), and MIIsInTerminatorSequence().

bool llvm::MachineInstr::isIndirectBranch ( QueryType Type = AnyInBundle ) const

inline

isIndirectBranch - Return true if this is an indirect branch, such as a branch through a register.

Definition at line 380 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::IndirectBranch.

Referenced by llvm::MipsInstrInfo::AnalyzeBranch(), llvm::AsmPrinter::isBlockOnlyReachableByFallthrough(), isConditionalBranch(), and isUnconditionalBranch().

bool llvm::MachineInstr::isIndirectDebugValue ( ) const

inline

A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate.

Definition at line 642 of file MachineInstr.h.

References getOperand(), isDebugValue(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().

Referenced by llvm::SelectionDAGISel::runOnMachineFunction().

bool llvm::MachineInstr::isInlineAsm ( ) const

inline

Definition at line 651 of file MachineInstr.h.

References getOpcode(), and llvm::TargetOpcode::INLINEASM.

Referenced by llvm::RegAllocBase::allocatePhysRegs(), llvm::PPCRegisterInfo::eliminateFrameIndex(), getOffsetONFromFION(), llvm::HexagonInstrInfo::isSchedulingBoundary(), isUnsafeToMoveAcross(), mayLoad(), and mayStore().

bool llvm::MachineInstr::isInsertSubreg ( ) const

inline

Definition at line 657 of file MachineInstr.h.

References getOpcode(), and llvm::TargetOpcode::INSERT_SUBREG.

Referenced by AvoidsSinking(), llvm::ARMBaseInstrInfo::getOperandLatency(), and isCopyToReg().

bool llvm::MachineInstr::isInsideBundle ( ) const

inline

isInsideBundle - Return true if MI is in a bundle (but not the first MI in a bundle).

A bundle looks like this before it's finalized:

| MI |

|

| MI * |

|

| MI * |

In this case, the first MI starts a bundle but is not inside a bundle, the next 2 MIs are considered "inside" the bundle.

After a bundle is finalized, it looks like this:

| Bundle |

|

| MI * |

|

| MI * |

|

| MI * |

The first instruction has the special opcode "BUNDLE". It's not "inside" a bundle, but the next three MIs are.

Definition at line 210 of file MachineInstr.h.

References BundledPred, and getFlag().

Referenced by llvm::BuildMI(), and llvm::SlotIndexes::insertMachineInstrInMaps().

bool MachineInstr::isInvariantLoad ( AliasAnalysis * AA ) const

isInvariantLoad - Return true if this instruction is loading from a location whose value is invariant across the function. For example, loading a value from the constant pool or from the argument area of a function if it does not change. This should only return true of all loads the instruction does are invariant (if it does multiple loads).

Definition at line 1289 of file MachineInstr.cpp.

References getParent(), llvm::MachineOperand::getParent(), I, and llvm::AliasAnalysis::pointsToConstantMemory().

Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph(), isGlobalMemoryObject(), and llvm::X86InstrInfo::isReallyTriviallyReMaterializable().

bool llvm::MachineInstr::isKill ( ) const

inline

Definition at line 649 of file MachineInstr.h.

References getOpcode(), and llvm::TargetOpcode::KILL.

Referenced by llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), and findRegisterUseOperand().

bool llvm::MachineInstr::isLabel ( ) const

inline

isLabel - Returns true if the MachineInstr represents a label.

Definition at line 628 of file MachineInstr.h.

References llvm::TargetOpcode::EH_LABEL, llvm::TargetOpcode::GC_LABEL, getOpcode(), and llvm::TargetOpcode::PROLOG_LABEL.

Referenced by llvm::DwarfDebug::beginFunction(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::GetInstSizeInBytes(), llvm::HexagonInstrInfo::isSchedulingBoundary(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), and llvm::TargetInstrInfo::isSchedulingBoundary().

bool llvm::MachineInstr::isMoveImmediate ( QueryType Type = IgnoreBundle ) const

inline

isMoveImmediate - Return true if this instruction is a move immediate (including conditional moves) instruction.

Definition at line 417 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::MoveImm.

bool llvm::MachineInstr::isMSInlineAsm ( ) const

inline

Definition at line 652 of file MachineInstr.h.

References getInlineAsmDialect(), getOpcode(), and llvm::TargetOpcode::INLINEASM.

bool llvm::MachineInstr::isNotDuplicable ( QueryType Type = AnyInBundle ) const

inline

isNotDuplicable - Return true if this instruction cannot be safely duplicated. For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.

Definition at line 436 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::NotDuplicable.

Referenced by llvm::TargetInstrInfo::duplicate().

bool llvm::MachineInstr::isPHI ( ) const

inline

Definition at line 648 of file MachineInstr.h.

References getOpcode(), and llvm::TargetOpcode::PHI.

Referenced by llvm::LiveRangeCalc::createDeadDefs(), llvm::LiveRangeCalc::extendToUses(), getPHIDeps(), getRegsUsedByPHIs(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::InstrIsPHI(), ProcessSourceNode(), llvm::MachineSSAUpdater::RewriteUse(), llvm::LiveVariables::runOnMachineFunction(), and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

bool llvm::MachineInstr::isPredicable ( QueryType Type = AllInBundle ) const

inline

Return true if this instruction has a predicate operand that controls execution. It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.

Definition at line 404 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Predicable.

Referenced by canFoldIntoMOVCC(), llvm::Thumb1RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseInstrInfo::GetInstSizeInBytes(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), and llvm::TargetInstrInfo::PredicateInstruction().

bool llvm::MachineInstr::isPrologLabel ( ) const

inline

Definition at line 634 of file MachineInstr.h.

References getOpcode(), and llvm::TargetOpcode::PROLOG_LABEL.

Referenced by llvm::AsmPrinter::EmitFunctionBody().

bool llvm::MachineInstr::isPseudo ( QueryType Type = IgnoreBundle ) const

inline

isPseudo - Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

Definition at line 341 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Pseudo.

bool llvm::MachineInstr::isRegSequence ( ) const

inline

Definition at line 663 of file MachineInstr.h.

References getOpcode(), and llvm::TargetOpcode::REG_SEQUENCE.

Referenced by AvoidsSinking(), and llvm::ARMBaseInstrInfo::getOperandLatency().

bool llvm::MachineInstr::isRegTiedToDefOperand	(	unsigned	UseOpIdx,
		unsigned *	DefOpIdx = `0`
	)		const

inline

isRegTiedToDefOperand - Return true if the use operand of the specified index is tied to an def operand. It also returns the def operand index by reference if DefOpIdx is not null.

Definition at line 862 of file MachineInstr.h.

References findTiedOperandIdx(), getOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), and llvm::MachineOperand::isUse().

Referenced by llvm::MachineOperandIteratorBase::analyzeVirtReg(), llvm::LiveRangeCalc::extendToUses(), and isTwoAddrUse().

bool llvm::MachineInstr::isRegTiedToUseOperand	(	unsigned	DefOpIdx,
		unsigned *	UseOpIdx = `0`
	)		const

inline

isRegTiedToUseOperand - Given the index of a register def operand, check if the register def is tied to a source operand, due to either two-address elimination or inline assembly constraints. Returns the first tied use operand index by reference if UseOpIdx is not null.

Definition at line 850 of file MachineInstr.h.

References findTiedOperandIdx(), getOperand(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isTied().

bool llvm::MachineInstr::isRematerializable ( QueryType Type = AllInBundle ) const

inline

isRematerializable - Returns true if this instruction is a candidate for remat. This flag is deprecated, please don't use it anymore. If this flag is set, the isReallyTriviallyReMaterializable() method is called to verify the instruction is really rematable.

Definition at line 548 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Rematerializable.

bool llvm::MachineInstr::isReturn ( QueryType Type = AnyInBundle ) const

inline

Definition at line 345 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Return.

Referenced by HandleVRSaveUpdate(), llvm::CriticalAntiDepBreaker::StartBlock(), and llvm::AggressiveAntiDepBreaker::StartBlock().

bool MachineInstr::isSafeToMove	(	const TargetInstrInfo *	TII,
		AliasAnalysis *	AA,
		bool &	SawStore
	)		const

isSafeToMove - Return true if it is safe to move this instruction. If SawStore is set to true, it means that there is a store (or call) between the instruction's location and its intended destination.

Definition at line 1228 of file MachineInstr.cpp.

References SawStore.

Referenced by canFoldIntoMOVCC(), MaySpeculate(), and llvm::X86InstrInfo::optimizeLoadInstr().

bool llvm::MachineInstr::isSelect ( QueryType Type = IgnoreBundle ) const

inline

isSelect - Return true if this instruction is a select instruction.

Definition at line 429 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Select.

bool MachineInstr::isStackAligningInlineAsm ( ) const

Definition at line 907 of file MachineInstr.cpp.

bool llvm::MachineInstr::isSubregToReg ( ) const

inline

Definition at line 660 of file MachineInstr.h.

References getOpcode(), and llvm::TargetOpcode::SUBREG_TO_REG.

Referenced by AvoidsSinking(), isCopyLike(), and isCopyToReg().

bool llvm::MachineInstr::isTerminator ( QueryType Type = AnyInBundle ) const

inline

isTerminator - Returns true if this instruction part of the terminator for a basic block. Typically this is things like return and branch instructions.

Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.

Definition at line 366 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Terminator.

Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph(), findInsertLocation(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::PPCInstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), and llvm::TargetInstrInfo::isUnpredicatedTerminator().

bool llvm::MachineInstr::isTransient ( ) const

inline

isTransient - Return true if this is a transient instruction that is either very likely to be eliminated during register allocation (such as copy-like instructions), or if this instruction doesn't have an execution-time cost.

Definition at line 692 of file MachineInstr.h.

References llvm::TargetOpcode::COPY, llvm::TargetOpcode::DBG_VALUE, llvm::TargetOpcode::EH_LABEL, llvm::TargetOpcode::GC_LABEL, getOpcode(), llvm::TargetOpcode::IMPLICIT_DEF, llvm::TargetOpcode::INSERT_SUBREG, llvm::TargetOpcode::KILL, llvm::TargetOpcode::PHI, llvm::TargetOpcode::PROLOG_LABEL, llvm::TargetOpcode::REG_SEQUENCE, and llvm::TargetOpcode::SUBREG_TO_REG.

Referenced by llvm::TargetSchedModel::computeOperandLatency(), llvm::TargetInstrInfo::defaultDefLatency(), llvm::TargetSchedModel::getNumMicroOps(), llvm::MachineTraceMetrics::getResources(), updatePhysDepsUpwards(), llvm::SchedDFSImpl::visitPostorderNode(), and llvm::SchedDFSImpl::visitPreorder().

bool llvm::MachineInstr::isUnconditionalBranch ( QueryType Type = AnyInBundle ) const

inline

isUnconditionalBranch - Return true if this is a branch which always transfers control flow to some other block. The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.

Definition at line 396 of file MachineInstr.h.

References isBarrier(), isBranch(), and isIndirectBranch().

bool llvm::MachineInstr::isVariadic ( QueryType Type = IgnoreBundle ) const

inline

isVariadic - Return true if this instruction can have a variable number of operands. In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).

Definition at line 328 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Variadic.

Referenced by llvm::SIInstrInfo::getOpRegClass().

bool llvm::MachineInstr::killsRegister	(	unsigned	Reg,
		const TargetRegisterInfo *	TRI = `NULL`
	)		const

inline

killsRegister - Return true if the MachineInstr kills the specified register. If TargetRegisterInfo is passed, then it also checks if there is a kill of a super-register.

Definition at line 745 of file MachineInstr.h.

References findRegisterUseOperandIdx().

Referenced by llvm::X86InstrInfo::classifyLEAReg(), isPlainlyKilled(), and llvm::X86InstrInfo::optimizeCompareInstr().

bool llvm::MachineInstr::mayLoad ( QueryType Type = AnyInBundle ) const

inline

mayLoad - Return true if this instruction could possibly read memory. Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.

Definition at line 465 of file MachineInstr.h.

References llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), and llvm::MCID::MayLoad.

Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::TargetInstrInfo::defaultDefLatency(), llvm::Thumb1RegisterInfo::eliminateFrameIndex(), llvm::ARMHazardRecognizer::getHazardType(), llvm::TargetInstrInfo::getInstrLatency(), isGlobalMemoryObject(), isLoadFromGOTOrConstantPool(), llvm::ARMBaseInstrInfo::isLoadFromStackSlotPostFE(), and llvm::X86InstrInfo::optimizeLoadInstr().

bool llvm::MachineInstr::mayStore ( QueryType Type = AnyInBundle ) const

inline

mayStore - Return true if this instruction could possibly modify memory. Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.

Definition at line 479 of file MachineInstr.h.

References llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), and llvm::MCID::MayStore.

Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::Thumb1RegisterInfo::eliminateFrameIndex(), llvm::ARMHazardRecognizer::getHazardType(), hasRAWHazard(), llvm::ARMBaseInstrInfo::isStoreToStackSlotPostFE(), and MIsNeedChainEdge().

mmo_iterator llvm::MachineInstr::memoperands_begin ( ) const

inline

Access to memory operands of the instruction.

Definition at line 291 of file MachineInstr.h.

Referenced by concatenateMemOperands(), emitComments(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::PPCHazardRecognizer970::EmitInstruction(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), EmitPCMPSTRI(), EmitPCMPSTRM(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::PPCHazardRecognizer970::getHazardType(), llvm::ARMBaseInstrInfo::getNumLDMAddresses(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::ARMBaseInstrInfo::getOperandLatency(), getUnderlyingObjectsForInstr(), llvm::TargetInstrInfo::hasLoadFromStackSlot(), llvm::TargetInstrInfo::hasStoreToStackSlot(), InstructionStoresToFI(), isLoadFromGOTOrConstantPool(), isMemoryOp(), isUnsafeMemoryObject(), MIsNeedChainEdge(), llvm::ARMBaseInstrInfo::reMaterialize(), and llvm::X86InstrInfo::unfoldMemoryOperand().

bool llvm::MachineInstr::memoperands_empty ( ) const

inline

Definition at line 293 of file MachineInstr.h.

Referenced by concatenateMemOperands(), llvm::PPCHazardRecognizer970::getHazardType(), and isUnsafeMemoryObject().

mmo_iterator llvm::MachineInstr::memoperands_end ( ) const

inline

Definition at line 292 of file MachineInstr.h.

Referenced by concatenateMemOperands(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), EmitPCMPSTRI(), EmitPCMPSTRM(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::ARMBaseInstrInfo::getNumLDMAddresses(), llvm::TargetInstrInfo::hasLoadFromStackSlot(), llvm::TargetInstrInfo::hasStoreToStackSlot(), InstructionStoresToFI(), isLoadFromGOTOrConstantPool(), llvm::ARMBaseInstrInfo::reMaterialize(), and llvm::X86InstrInfo::unfoldMemoryOperand().

bool llvm::MachineInstr::modifiesRegister	(	unsigned	Reg,
		const TargetRegisterInfo *	TRI
	)		const

inline

modifiesRegister - Return true if the MachineInstr modifies (fully define or partially define) the specified register. NOTE: It's ignoring subreg indices on virtual registers.

Definition at line 760 of file MachineInstr.h.

References findRegisterDefOperandIdx().

Referenced by DoesModifyCalleeSavedReg(), llvm::TargetInstrInfo::isSchedulingBoundary(), isUnsafeToMoveAcross(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), and removeIPMBasedCompare().

mop_iterator llvm::MachineInstr::operands_begin ( )

inline

Definition at line 284 of file MachineInstr.h.

Referenced by llvm::DwarfDebug::beginFunction(), getPredicatedRegister(), llvm::AsmPrinter::isBlockOnlyReachableByFallthrough(), llvm::HexagonInstrInfo::isExtended(), MIIsInTerminatorSequence(), llvm::R600InstrInfo::readsLDSSrcReg(), llvm::StackMaps::recordPatchPoint(), llvm::StackMaps::recordStackMap(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::R600SchedStrategy::schedNode(), and llvm::MachineBasicBlock::SplitCriticalEdge().

const_mop_iterator llvm::MachineInstr::operands_begin ( ) const

inline

Definition at line 287 of file MachineInstr.h.

mop_iterator llvm::MachineInstr::operands_end ( )

inline

Definition at line 285 of file MachineInstr.h.

Referenced by llvm::DwarfDebug::beginFunction(), getPredicatedRegister(), llvm::AsmPrinter::isBlockOnlyReachableByFallthrough(), llvm::HexagonInstrInfo::isExtended(), MIIsInTerminatorSequence(), llvm::R600InstrInfo::readsLDSSrcReg(), llvm::StackMaps::recordPatchPoint(), llvm::StackMaps::recordStackMap(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::R600SchedStrategy::schedNode(), and llvm::MachineBasicBlock::SplitCriticalEdge().

const_mop_iterator llvm::MachineInstr::operands_end ( ) const

inline

Definition at line 288 of file MachineInstr.h.

void MachineInstr::print	(	raw_ostream &	OS,
		const TargetMachine *	TM = `0`,
		bool	SkipOpers = `false`
	)		const

Definition at line 1410 of file MachineInstr.cpp.

Referenced by llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ScheduleDAGInstrs::getGraphNodeLabel(), and llvm::operator<<().

bool llvm::MachineInstr::readsRegister	(	unsigned	Reg,
		const TargetRegisterInfo *	TRI = `NULL`
	)		const

inline

readsRegister - Return true if the MachineInstr reads the specified register. If TargetRegisterInfo is passed, then it also checks if there is a read of a super-register. This does not count partial redefines of virtual registers as reads: reg1024:6 = OP.

Definition at line 724 of file MachineInstr.h.

References findRegisterUseOperandIdx().

Referenced by checkAndUpdateEFLAGSKill(), llvm::TargetSchedModel::computeOutputLatency(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), getImplicitSPRUseForDPRUse(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), hasRAWHazard(), isUnsafeToMoveAcross(), llvm::SIInstrInfo::legalizeOperands(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), and llvm::ARMBaseInstrInfo::setExecutionDomain().

bool llvm::MachineInstr::readsVirtualRegister ( unsigned Reg ) const

inline

readsVirtualRegister - Return true if the MachineInstr reads the specified virtual register. Take into account that a partial define is a read-modify-write operation.

Definition at line 731 of file MachineInstr.h.

References readsWritesVirtualRegister().

Referenced by llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), llvm::SplitEditor::leaveIntvAfter(), and llvm::LiveIntervals::shrinkToUses().

std::pair< bool, bool > MachineInstr::readsWritesVirtualRegister	(	unsigned	Reg,
		SmallVectorImpl< unsigned > *	Ops = `0`
	)		const

readsWritesVirtualRegister - Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg. This also considers partial defines. If Ops is not null, all operand indices for Reg are added.

readsWritesVirtualRegister - Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg. This also considers partial defines.

Definition at line 1024 of file MachineInstr.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::MachineOperand::Reg.

Referenced by llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), and readsVirtualRegister().

bool llvm::MachineInstr::registerDefIsDead	(	unsigned	Reg,
		const TargetRegisterInfo *	TRI = `NULL`
	)		const

inline

registerDefIsDead - Returns true if the register is dead in this machine instruction. If TargetRegisterInfo is passed, then it also checks if there is a dead def of a super-register.

Definition at line 767 of file MachineInstr.h.

References findRegisterDefOperandIdx().

Referenced by llvm::ScheduleDAGInstrs::addPhysRegDeps(), and llvm::X86InstrInfo::optimizeCompareInstr().

MachineInstr * MachineInstr::removeFromBundle ( )

Unlink this instruction from its basic block and return it without deleting it.

If the instruction is part of a bundle, the other instructions in the bundle remain bundled.

Definition at line 841 of file MachineInstr.cpp.

References llvm::MachineOperand::getParent().

MachineInstr * MachineInstr::removeFromParent ( )

Unlink 'this' from the containing basic block, and return it without deleting it.

This function can not be used on bundled instructions, use removeFromBundle() to remove individual instructions from a bundle.

Definition at line 836 of file MachineInstr.cpp.

References llvm::MachineOperand::getParent().

void MachineInstr::RemoveOperand ( unsigned OpNo )

RemoveOperand - Erase an operand from an instruction, leaving it with one fewer operand than it started with.

Definition at line 717 of file MachineInstr.cpp.

References llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), moveOperands(), MRI, N, and llvm::MachineRegisterInfo::removeRegOperandFromUseList().

Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), INITIALIZE_PASS(), llvm::SIInstrInfo::moveToVALU(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), removeOperands(), llvm::rewriteARMFrameIndex(), llvm::Thumb1RegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::ARMBaseInstrInfo::setExecutionDomain(), and llvm::tryFoldSPUpdateIntoPushPop().

void llvm::MachineInstr::setAsmPrinterFlag ( CommentFlag Flag )

inline

setAsmPrinterFlag - Set a flag for the AsmPrinter.

Definition at line 138 of file MachineInstr.h.

void llvm::MachineInstr::setDebugLoc ( const DebugLoc dl )

inline

setDebugLoc - Replace current source information with new such. Avoid using this, the constructor argument is preferable.

Definition at line 989 of file MachineInstr.h.

void llvm::MachineInstr::setDesc ( const MCInstrDesc & tid )

inline

setDesc - Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

Definition at line 984 of file MachineInstr.h.

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::SIInstrInfo::commuteInstruction(), llvm::X86InstrInfo::commuteInstruction(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::Thumb1RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), Expand2AddrUndef(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), INITIALIZE_PASS(), llvm::SIInstrInfo::moveToVALU(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::rewriteARMFrameIndex(), llvm::Thumb1RegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomain(), llvm::X86InstrInfo::unfoldMemoryOperand(), and UpdateOp().

void llvm::MachineInstr::setFlag ( MIFlag Flag )

inline

setFlag - Set a MI flag.

Definition at line 159 of file MachineInstr.h.

Referenced by llvm::X86FrameLowering::emitPrologue(), emitSPUpdate(), llvm::MIBundleBuilder::insert(), and llvm::MachineInstrBuilder::setMIFlag().

void llvm::MachineInstr::setFlags ( unsigned flags )

inline

Definition at line 163 of file MachineInstr.h.

References BundledPred, and BundledSucc.

Referenced by llvm::MachineInstrBuilder::setMIFlags().

void llvm::MachineInstr::setMemRefs	(	mmo_iterator	NewMemRefs,
		mmo_iterator	NewMemRefsEnd
	)

inline

setMemRefs - Assign this MachineInstr's memory reference descriptor list. This does not transfer ownership.

Definition at line 1003 of file MachineInstr.h.

Referenced by concatenateMemOperands(), EmitPCMPSTRI(), EmitPCMPSTRM(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::ARMBaseInstrInfo::reMaterialize(), and llvm::MachineInstrBuilder::setMemRefs().

void MachineInstr::setPhysRegsDeadExcept	(	ArrayRef< unsigned >	UsedRegs,
		const TargetRegisterInfo &	TRI
	)

setPhysRegsDeadExcept - Mark every physreg used by this instruction as dead except those in the UsedRegs list.

On instructions with register mask operands, also add implicit-def operands for all registers in UsedRegs.

Definition at line 1779 of file MachineInstr.cpp.

References llvm::ArrayRef< T >::begin(), llvm::RegState::Dead, llvm::ArrayRef< T >::end(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::TargetRegisterInfo::regsOverlap(), and llvm::MachineOperand::setIsDead().

void MachineInstr::substituteRegister	(	unsigned	FromReg,
		unsigned	ToReg,
		unsigned	SubIdx,
		const TargetRegisterInfo &	RegInfo
	)

substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessary.

Definition at line 1202 of file MachineInstr.cpp.

References llvm::MachineOperand::getReg(), llvm::MCRegisterInfo::getSubReg(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::substPhysReg(), and llvm::MachineOperand::substVirtReg().

Referenced by llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), and llvm::TargetInstrInfo::reMaterialize().

void MachineInstr::tieOperands	(	unsigned	DefIdx,
		unsigned	UseIdx
	)

tieOperands - Add a tie between the register operands at DefIdx and UseIdx. The tie will cause the register allocator to ensure that the two operands are assigned the same physical register.

Tied operands are managed automatically for explicit operands in the MCInstrDesc. This method is for exceptional cases like inline asm.

tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.

Use and def operands can be tied together, indicated by a non-zero TiedTo field. TiedTo can have these values:

0: Operand is not tied to anything. 1 to TiedMax-1: Tied to getOperand(TiedTo-1). TiedMax: Tied to an operand >= TiedMax-1.

The tied def must be one of the first TiedMax operands on a normal instruction. INLINEASM instructions allow more tied defs.

Definition at line 1112 of file MachineInstr.cpp.

References llvm::MachineOperand::isDef(), llvm::MachineOperand::isTied(), llvm::MachineOperand::isUse(), and TiedMax.

Referenced by llvm::ARMBaseInstrInfo::optimizeSelect().

void MachineInstr::unbundleFromPred ( )

Break bundle above this instruction.

Definition at line 889 of file MachineInstr.cpp.

Referenced by unbundleSingleMI().

void MachineInstr::unbundleFromSucc ( )

Break bundle below this instruction.

Definition at line 898 of file MachineInstr.cpp.

Referenced by unbundleSingleMI().

bool llvm::MachineInstr::usesCustomInsertionHook ( QueryType Type = IgnoreBundle ) const

inline

usesCustomInsertionHook - Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.

If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.

Definition at line 532 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::UsesCustomInserter.

Referenced by INITIALIZE_PASS().