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AMDGPUMCTargetDesc.cpp
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1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief This file provides AMDGPU specific target descriptions.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUMCTargetDesc.h"
16 #include "AMDGPUMCAsmInfo.h"
18 #include "llvm/MC/MCCodeGenInfo.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCStreamer.h"
26 
27 #define GET_INSTRINFO_MC_DESC
28 #include "AMDGPUGenInstrInfo.inc"
29 
30 #define GET_SUBTARGETINFO_MC_DESC
31 #include "AMDGPUGenSubtargetInfo.inc"
32 
33 #define GET_REGINFO_MC_DESC
34 #include "AMDGPUGenRegisterInfo.inc"
35 
36 using namespace llvm;
37 
39  MCInstrInfo *X = new MCInstrInfo();
40  InitAMDGPUMCInstrInfo(X);
41  return X;
42 }
43 
46  InitAMDGPUMCRegisterInfo(X, 0);
47  return X;
48 }
49 
51  StringRef FS) {
53  InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
54  return X;
55 }
56 
59  CodeGenOpt::Level OL) {
60  MCCodeGenInfo *X = new MCCodeGenInfo();
61  X->InitMCCodeGenInfo(RM, CM, OL);
62  return X;
63 }
64 
66  unsigned SyntaxVariant,
67  const MCAsmInfo &MAI,
68  const MCInstrInfo &MII,
69  const MCRegisterInfo &MRI,
70  const MCSubtargetInfo &STI) {
71  return new AMDGPUInstPrinter(MAI, MII, MRI);
72 }
73 
75  const MCRegisterInfo &MRI,
76  const MCSubtargetInfo &STI,
77  MCContext &Ctx) {
78  if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
79  return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
80  } else {
81  return createR600MCCodeEmitter(MCII, MRI, STI);
82  }
83 }
84 
86  MCContext &Ctx, MCAsmBackend &MAB,
87  raw_ostream &_OS,
88  MCCodeEmitter *_Emitter,
89  bool RelaxAll,
90  bool NoExecStack) {
91  return createELFStreamer(Ctx, 0, MAB, _OS, _Emitter, false, false);
92 }
93 
94 extern "C" void LLVMInitializeR600TargetMC() {
95 
97 
99 
101 
103 
105 
107 
109 
111 
113 }
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI)
static MCStreamer * createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, bool RelaxAll, bool NoExecStack)
static MCInstrInfo * createAMDGPUMCInstrInfo()
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
MCStreamer * createELFStreamer(MCContext &Ctx, MCTargetStreamer *TargetStreamer, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *CE, bool RelaxAll, bool NoExecStack)
Target TheAMDGPUTarget
The target for the AMDGPU backend.
static MCInstPrinter * createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI)
void InitMCCodeGenInfo(Reloc::Model RM=Reloc::Default, CodeModel::Model CM=CodeModel::Default, CodeGenOpt::Level OL=CodeGenOpt::Default)
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
static MCCodeGenInfo * createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
static void RegisterMCObjectStreamer(Target &T, Target::MCObjectStreamerCtorTy Fn)
const MCInstrInfo & MII
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
static MCSubtargetInfo * createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS)
static void RegisterMCCodeGenInfo(Target &T, Target::MCCodeGenInfoCtorFnTy Fn)
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
uint64_t getFeatureBits() const
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
Provides AMDGPU specific target descriptions.
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx)
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
MCAsmBackend - Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:34
static MCCodeEmitter * createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx)
cl::opt< bool > RelaxAll("mc-relax-all", cl::desc("When used with filetype=obj, ""relax all fixups in the emitted object file"))
const MCRegisterInfo & MRI
void LLVMInitializeR600TargetMC()
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
static RegisterPass< NVPTXAllocaHoisting > X("alloca-hoisting","Hoisting alloca instructions in non-entry ""blocks to the entry block")
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU)
static MCRegisterInfo * createAMDGPUMCRegisterInfo(StringRef TT)