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LiveStackAnalysis.cpp
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1 //===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the live stack slot analysis pass. It is analogous to
11 // live interval analysis except it's analyzing liveness of stack slots rather
12 // than registers.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #define DEBUG_TYPE "livestacks"
18 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Support/Debug.h"
24 #include <limits>
25 using namespace llvm;
26 
27 char LiveStacks::ID = 0;
28 INITIALIZE_PASS_BEGIN(LiveStacks, "livestacks",
29  "Live Stack Slot Analysis", false, false)
32  "Live Stack Slot Analysis", false, false)
33 
34 char &llvm::LiveStacksID = LiveStacks::ID;
35 
36 void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
37  AU.setPreservesAll();
38  AU.addPreserved<SlotIndexes>();
39  AU.addRequiredTransitive<SlotIndexes>();
41 }
42 
44  // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
45  VNInfoAllocator.Reset();
46  S2IMap.clear();
47  S2RCMap.clear();
48 }
49 
51  TRI = MF.getTarget().getRegisterInfo();
52  // FIXME: No analysis is being done right now. We are relying on the
53  // register allocators to provide the information.
54  return false;
55 }
56 
59  assert(Slot >= 0 && "Spill slot indice must be >= 0");
60  SS2IntervalMap::iterator I = S2IMap.find(Slot);
61  if (I == S2IMap.end()) {
62  I = S2IMap.insert(I, std::make_pair(Slot,
64  S2RCMap.insert(std::make_pair(Slot, RC));
65  } else {
66  // Use the largest common subclass register class.
67  const TargetRegisterClass *OldRC = S2RCMap[Slot];
68  S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
69  }
70  return I->second;
71 }
72 
73 /// print - Implement the dump method.
74 void LiveStacks::print(raw_ostream &OS, const Module*) const {
75 
76  OS << "********** INTERVALS **********\n";
77  for (const_iterator I = begin(), E = end(); I != E; ++I) {
78  I->second.print(OS);
79  int Slot = I->first;
80  const TargetRegisterClass *RC = getIntervalRegClass(Slot);
81  if (RC)
82  OS << " [" << RC->getName() << "]\n";
83  else
84  OS << " [Unknown]\n";
85  }
86 }
The main container class for the LLVM Intermediate Representation.
Definition: Module.h:112
virtual bool runOnMachineFunction(MachineFunction &)
runOnMachineFunction - pass entry point
INITIALIZE_PASS_BEGIN(LiveStacks,"livestacks","Live Stack Slot Analysis", false, false) INITIALIZE_PASS_END(LiveStacks
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
F(f)
const_iterator end() const
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:167
const TargetRegisterClass * getIntervalRegClass(int Slot) const
const char * getName() const
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:172
virtual void releaseMemory()
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
LiveInterval & getOrCreateInterval(int Slot, const TargetRegisterClass *RC)
SS2IntervalMap::const_iterator const_iterator
Live Stack Slot Analysis
char & LiveStacksID
LiveStacks pass. An analysis keeping track of the liveness of stack slots.
virtual void print(raw_ostream &O, const Module *=0) const
print - Implement the dump method.
Live Stack Slot false
virtual void getAnalysisUsage(AnalysisUsage &AU) const
#define I(x, y, z)
Definition: MD5.cpp:54
const TargetMachine & getTarget() const
virtual const TargetRegisterInfo * getRegisterInfo() const
const_iterator begin() const
static unsigned index2StackSlot(int FI)