#include <TargetRegisterInfo.h>

Collaboration diagram for llvm::TargetRegisterClass:

Public Types
typedef const MCPhysReg *	iterator

typedef const MCPhysReg *	const_iterator

typedef const MVT::SimpleValueType *	vt_iterator

typedef const TargetRegisterClass const	sc_iterator

Public Member Functions
unsigned	getID () const

const char *	getName () const

iterator	begin () const

iterator	end () const

unsigned	getNumRegs () const

unsigned	getRegister (unsigned i) const

bool	contains (unsigned Reg) const

bool	contains (unsigned Reg1, unsigned Reg2) const
	contains - Return true if both registers are in this class. More...

unsigned	getSize () const

unsigned	getAlignment () const

int	getCopyCost () const

bool	isAllocatable () const

bool	hasType (EVT vt) const

vt_iterator	vt_begin () const

vt_iterator	vt_end () const

bool	hasSubClass (const TargetRegisterClass *RC) const

bool	hasSubClassEq (const TargetRegisterClass *RC) const

bool	hasSuperClass (const TargetRegisterClass *RC) const

bool	hasSuperClassEq (const TargetRegisterClass *RC) const

const uint32_t *	getSubClassMask () const

const uint16_t *	getSuperRegIndices () const

sc_iterator	getSuperClasses () const

bool	isASubClass () const

ArrayRef< MCPhysReg >	getRawAllocationOrder (const MachineFunction &MF) const

Public Attributes
const MCRegisterClass *	MC

const vt_iterator	VTs

const uint32_t *	SubClassMask

const uint16_t *	SuperRegIndices

const sc_iterator	SuperClasses

ArrayRef< MCPhysReg >(*	OrderFunc )(const MachineFunction &)

Detailed Description

Definition at line 36 of file TargetRegisterInfo.h.

Member Typedef Documentation

typedef const MCPhysReg* llvm::TargetRegisterClass::const_iterator

Definition at line 39 of file TargetRegisterInfo.h.

typedef const MCPhysReg* llvm::TargetRegisterClass::iterator

Definition at line 38 of file TargetRegisterInfo.h.

typedef const TargetRegisterClass* const* llvm::TargetRegisterClass::sc_iterator

Definition at line 41 of file TargetRegisterInfo.h.

typedef const MVT::SimpleValueType* llvm::TargetRegisterClass::vt_iterator

Definition at line 40 of file TargetRegisterInfo.h.

Member Function Documentation

iterator llvm::TargetRegisterClass::begin ( ) const

inline

begin/end - Return all of the registers in this class.

Definition at line 61 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::begin(), and MC.

Referenced by llvm::PPCInstrInfo::DefinesPredicate(), llvm::RegScavenger::FindUnusedReg(), getRawAllocationOrder(), llvm::TargetLowering::getRegForInlineAsmConstraint(), GetRegistersForValue(), llvm::RegScavenger::getRegsAvailable(), and llvm::ARMBaseRegisterInfo::getReservedRegs().

bool llvm::TargetRegisterClass::contains ( unsigned Reg ) const

inline

contains - Return true if the specified register is included in this register class. This does not include virtual registers.

Definition at line 76 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::contains(), and MC.

Referenced by canFoldCopy(), llvm::SystemZInstrInfo::convertToThreeAddress(), copyHint(), llvm::PPCInstrInfo::DefinesPredicate(), llvm::AArch64FrameLowering::emitFrameMemOps(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::PPCInstrInfo::insertSelect(), printModifiedGPRAsmOperand(), and llvm::CoalescerPair::setRegisters().

bool llvm::TargetRegisterClass::contains	(	unsigned	Reg1,
		unsigned	Reg2
	)		const

inline

contains - Return true if both registers are in this class.

Definition at line 81 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::contains(), and MC.

iterator llvm::TargetRegisterClass::end ( ) const

inline

Definition at line 62 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::end(), and MC.

Referenced by llvm::PPCInstrInfo::DefinesPredicate(), llvm::RegScavenger::FindUnusedReg(), llvm::TargetLowering::getRegForInlineAsmConstraint(), GetRegistersForValue(), llvm::RegScavenger::getRegsAvailable(), and llvm::ARMBaseRegisterInfo::getReservedRegs().

unsigned llvm::TargetRegisterClass::getAlignment ( ) const

inline

getAlignment - Return the minimum required alignment for a register of this class.

Definition at line 91 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getAlignment(), and MC.

Referenced by llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::MipsSEFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::XCoreFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::ARMFrameLowering::processFunctionBeforeCalleeSavedScan(), and llvm::AArch64FrameLowering::processFunctionBeforeCalleeSavedScan().

int llvm::TargetRegisterClass::getCopyCost ( ) const

inline

getCopyCost - Return the cost of copying a value between two registers in this class. A negative number means the register class is very expensive to copy e.g. status flag register classes.

Definition at line 96 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getCopyCost(), and MC.

Referenced by CheckForPhysRegDependency().

unsigned llvm::TargetRegisterClass::getID ( ) const

inline

getID() - Return the register class ID number.

Definition at line 53 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getID(), and MC.

Referenced by llvm::ARMBaseRegisterInfo::avoidWriteAfterWrite(), GetCostForDef(), llvm::R600RegisterInfo::getISARegClass(), llvm::SIRegisterInfo::getISARegClass(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::PPCRegisterInfo::getRegPressureLimit(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::X86RegisterInfo::getRegPressureLimit(), llvm::ARMBaseRegisterInfo::getRegPressureLimit(), hasSubClassEq(), INITIALIZE_PASS(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::ResourcePriorityQueue::regPressureDelta(), and llvm::ResourcePriorityQueue::scheduledNode().

const char* llvm::TargetRegisterClass::getName ( ) const

inline

getName() - Return the register class name for debugging.

Definition at line 57 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getName(), and MC.

Referenced by llvm::RegAllocBase::allocatePhysRegs(), llvm::LiveRangeEdit::calculateRegClassAndHint(), llvm::LiveStacks::print(), and llvm::MachineInstr::print().

unsigned llvm::TargetRegisterClass::getNumRegs ( ) const

inline

getNumRegs - Return the number of registers in this class.

Definition at line 66 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getNumRegs(), and MC.

Referenced by llvm::RegisterClassInfo::computePSetLimit(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), getRawAllocationOrder(), and llvm::SIRegisterInfo::getRegPressureLimit().

ArrayRef<MCPhysReg> llvm::TargetRegisterClass::getRawAllocationOrder ( const MachineFunction & MF ) const

inline

getRawAllocationOrder - Returns the preferred order for allocating registers from this register class in MF. The raw order comes directly from the .td file and may include reserved registers that are not allocatable. Register allocators should also make sure to allocate callee-saved registers only after all the volatiles are used. The RegisterClassInfo class provides filtered allocation orders with callee-saved registers moved to the end.

The MachineFunction argument can be used to tune the allocatable registers based on the characteristics of the function, subtarget, or other criteria.

By default, this method returns all registers in the class.

Definition at line 194 of file TargetRegisterInfo.h.

References begin(), getNumRegs(), llvm::makeArrayRef(), and OrderFunc.

Referenced by llvm::PBQPBuilder::build(), and getAllocatableSetForRC().

unsigned llvm::TargetRegisterClass::getRegister ( unsigned i ) const

inline

getRegister - Return the specified register in the class.

Definition at line 70 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getRegister(), and MC.

Referenced by llvm::AMDGPUInstrInfo::expandPostRAPseudo(), and llvm::AMDGPUInstrInfo::getIndirectIndexBegin().

unsigned llvm::TargetRegisterClass::getSize ( ) const

inline

getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a spilled copy of this register.

Definition at line 87 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getSize(), and MC.

Referenced by llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::AArch64FrameLowering::emitFrameMemOps(), llvm::MipsFrameLowering::estimateStackSize(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::TargetRegisterInfo::getCommonSuperRegClass(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), getLoadStoreRegOpcode(), llvm::TargetInstrInfo::getStackSlotRange(), llvm::X86InstrInfo::insertSelect(), llvm::X86InstrInfo::loadRegFromAddr(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::MipsSEFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::XCoreFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::ARMFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::X86InstrInfo::storeRegToAddr(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::ARMBaseInstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::storeRegToStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().

const uint32_t* llvm::TargetRegisterClass::getSubClassMask ( ) const

inline

getSubClassMask - Returns a bit vector of subclasses, including this one. The vector is indexed by class IDs, see hasSubClassEq() above for how to use it.

Definition at line 151 of file TargetRegisterInfo.h.

References SubClassMask.

Referenced by llvm::TargetRegisterInfo::getAllocatableClass(), llvm::TargetRegisterInfo::getCommonSubClass(), and llvm::TargetRegisterInfo::getMatchingSuperRegClass().

sc_iterator llvm::TargetRegisterClass::getSuperClasses ( ) const

inline

getSuperClasses - Returns a NULL terminated list of super-classes. The classes are ordered by ID which is also a topological ordering from large to small classes. The list does NOT include the current class.

Definition at line 170 of file TargetRegisterInfo.h.

References SuperClasses.

Referenced by llvm::X86RegisterInfo::getLargestLegalSuperClass(), and llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass().

const uint16_t* llvm::TargetRegisterClass::getSuperRegIndices ( ) const

inline

getSuperRegIndices - Returns a 0-terminated list of sub-register indices that project some super-register class into this register class. The list has an entry for each Idx such that:

There exists SuperRC where: For all Reg in SuperRC: this->contains(Reg:Idx)

Definition at line 163 of file TargetRegisterInfo.h.

References SuperRegIndices.

bool llvm::TargetRegisterClass::hasSubClass ( const TargetRegisterClass * RC ) const

inline

hasSubClass - return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.

Definition at line 125 of file TargetRegisterInfo.h.

References hasSubClassEq().

Referenced by llvm::TargetRegisterInfo::getMinimalPhysRegClass(), and hasSuperClass().

bool llvm::TargetRegisterClass::hasSubClassEq ( const TargetRegisterClass * RC ) const

inline

hasSubClassEq - Returns true if RC is a sub-class of or equal to this class.