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SystemZMCCodeEmitter.cpp
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1 //===-- SystemZMCCodeEmitter.cpp - Convert SystemZ code to machine code ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SystemZMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mccodeemitter"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 
22 using namespace llvm;
23 
24 namespace {
25 class SystemZMCCodeEmitter : public MCCodeEmitter {
26  const MCInstrInfo &MCII;
27  MCContext &Ctx;
28 
29 public:
30  SystemZMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
31  : MCII(mcii), Ctx(ctx) {
32  }
33 
34  ~SystemZMCCodeEmitter() {}
35 
36  // OVerride MCCodeEmitter.
37  virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
40 
41 private:
42  // Automatically generated by TableGen.
43  uint64_t getBinaryCodeForInstr(const MCInst &MI,
44  SmallVectorImpl<MCFixup> &Fixups) const;
45 
46  // Called by the TableGen code to get the binary encoding of operand
47  // MO in MI. Fixups is the list of fixups against MI.
48  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
49  SmallVectorImpl<MCFixup> &Fixups) const;
50 
51  // Called by the TableGen code to get the binary encoding of an address.
52  // The index or length, if any, is encoded first, followed by the base,
53  // followed by the displacement. In a 20-bit displacement,
54  // the low 12 bits are encoded before the high 8 bits.
55  uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
56  SmallVectorImpl<MCFixup> &Fixups) const;
57  uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
58  SmallVectorImpl<MCFixup> &Fixups) const;
59  uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
60  SmallVectorImpl<MCFixup> &Fixups) const;
61  uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
62  SmallVectorImpl<MCFixup> &Fixups) const;
63  uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
64  SmallVectorImpl<MCFixup> &Fixups) const;
65 
66  // Operand OpNum of MI needs a PC-relative fixup of kind Kind at
67  // Offset bytes from the start of MI. Add the fixup to Fixups
68  // and return the in-place addend, which since we're a RELA target
69  // is always 0.
70  uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
72  unsigned Kind, int64_t Offset) const;
73 
74  uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum,
75  SmallVectorImpl<MCFixup> &Fixups) const {
76  return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2);
77  }
78  uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum,
79  SmallVectorImpl<MCFixup> &Fixups) const {
80  return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2);
81  }
82 };
83 }
84 
86  const MCRegisterInfo &MRI,
87  const MCSubtargetInfo &MCSTI,
88  MCContext &Ctx) {
89  return new SystemZMCCodeEmitter(MCII, Ctx);
90 }
91 
92 void SystemZMCCodeEmitter::
93 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
95  uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
96  unsigned Size = MCII.get(MI.getOpcode()).getSize();
97  // Big-endian insertion of Size bytes.
98  unsigned ShiftValue = (Size * 8) - 8;
99  for (unsigned I = 0; I != Size; ++I) {
100  OS << uint8_t(Bits >> ShiftValue);
101  ShiftValue -= 8;
102  }
103 }
104 
105 uint64_t SystemZMCCodeEmitter::
106 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
107  SmallVectorImpl<MCFixup> &Fixups) const {
108  if (MO.isReg())
109  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
110  if (MO.isImm())
111  return static_cast<uint64_t>(MO.getImm());
112  llvm_unreachable("Unexpected operand type!");
113 }
114 
115 uint64_t SystemZMCCodeEmitter::
116 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
117  SmallVectorImpl<MCFixup> &Fixups) const {
118  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
119  uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
120  assert(isUInt<4>(Base) && isUInt<12>(Disp));
121  return (Base << 12) | Disp;
122 }
123 
124 uint64_t SystemZMCCodeEmitter::
125 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
126  SmallVectorImpl<MCFixup> &Fixups) const {
127  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
128  uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
129  assert(isUInt<4>(Base) && isInt<20>(Disp));
130  return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
131 }
132 
133 uint64_t SystemZMCCodeEmitter::
134 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
135  SmallVectorImpl<MCFixup> &Fixups) const {
136  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
137  uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
138  uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups);
139  assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
140  return (Index << 16) | (Base << 12) | Disp;
141 }
142 
143 uint64_t SystemZMCCodeEmitter::
144 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
145  SmallVectorImpl<MCFixup> &Fixups) const {
146  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
147  uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
148  uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups);
149  assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
150  return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8)
151  | ((Disp & 0xff000) >> 12);
152 }
153 
154 uint64_t SystemZMCCodeEmitter::
155 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
156  SmallVectorImpl<MCFixup> &Fixups) const {
157  uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
158  uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
159  uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups) - 1;
160  assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len));
161  return (Len << 16) | (Base << 12) | Disp;
162 }
163 
164 uint64_t
165 SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
166  SmallVectorImpl<MCFixup> &Fixups,
167  unsigned Kind, int64_t Offset) const {
168  const MCOperand &MO = MI.getOperand(OpNum);
169  const MCExpr *Expr;
170  if (MO.isImm())
171  Expr = MCConstantExpr::Create(MO.getImm() + Offset, Ctx);
172  else {
173  Expr = MO.getExpr();
174  if (Offset) {
175  // The operand value is relative to the start of MI, but the fixup
176  // is relative to the operand field itself, which is Offset bytes
177  // into MI. Add Offset to the relocation value to cancel out
178  // this difference.
179  const MCExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx);
180  Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx);
181  }
182  }
183  Fixups.push_back(MCFixup::Create(Offset, Expr, (MCFixupKind)Kind));
184  return 0;
185 }
186 
187 #include "SystemZGenMCCodeEmitter.inc"
bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:294
bool isReg() const
Definition: MCInst.h:56
static const MCConstantExpr * Create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:152
#define llvm_unreachable(msg)
unsigned getReg() const
getReg - Returns the register number.
Definition: MCInst.h:63
bool isImm() const
Definition: MCInst.h:57
const MCExpr * getExpr() const
Definition: MCInst.h:93
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:22
MCFixupKind
MCFixupKind - Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
MCCodeEmitter * createSystemZMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx)
unsigned getOpcode() const
Definition: MCInst.h:158
int64_t getImm() const
Definition: MCInst.h:74
static const MCBinaryExpr * CreateAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:396
#define I(x, y, z)
Definition: MD5.cpp:54
static MCFixup Create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:77
const MCRegisterInfo & MRI
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:163
#define LLVM_OVERRIDE
Definition: Compiler.h:155