14 #ifndef LLVM_TARGET_AARCH64REGISTERINFO_H
15 #define LLVM_TARGET_AARCH64REGISTERINFO_H
19 #define GET_REGINFO_HEADER
20 #include "AArch64GenRegisterInfo.inc"
24 class AArch64InstrInfo;
25 class AArch64Subtarget;
39 unsigned FIOperandNum,
52 if (RC == &AArch64::tcGPR64RegClass)
53 return &AArch64::GPR64RegClass;
71 #endif // LLVM_TARGET_AARCH64REGISTERINFO_H
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC) const
const uint16_t * getCalleeSavedRegs(const MachineFunction *MF=0) const
const uint32_t * getCallPreservedMask(CallingConv::ID) const
unsigned getFrameRegister(const MachineFunction &MF) const
ID
LLVM Calling Convention Representation.
BitVector getReservedRegs(const MachineFunction &MF) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const
const uint32_t * getTLSDescCallPreservedMask() const
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *Rs=NULL) const
bundle_iterator< MachineInstr, instr_iterator > iterator
bool requiresRegisterScavenging(const MachineFunction &MF) const
bool useFPForScavengingIndex(const MachineFunction &MF) const
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const