30 : CallingConv(CC), IsVarArg(isVarArg),
TM(tm), Locs(locs), Context(c) {
46 if (MinSize > (
int)Size)
48 if (MinAlign > (
int)Align)
57 void Hexagon_CCState::MarkAllocated(
unsigned Reg) {
60 UsedRegs[*AI/32] |= 1 << (*AI&31);
69 unsigned SretValueInRegs) {
70 unsigned NumArgs = Ins.
size();
75 if (SretValueInRegs != 0) {
80 for (; i != NumArgs; ++i) {
81 EVT ArgVT = Ins[i].VT;
84 dbgs() <<
"Formal argument #" << i <<
" has unhandled type "
96 unsigned SretValueInRegs) {
99 if (SretValueInRegs != 0) {
100 if (SretValueInRegs <= 32) {
101 unsigned Reg = Hexagon::R0;
106 if (SretValueInRegs <= 64) {
107 unsigned Reg = Hexagon::D0;
116 for (
unsigned i = 0, e = Outs.
size(); i != e; ++i) {
120 dbgs() <<
"Return operand #" << i <<
" has unhandled type "
134 int NonVarArgsParams,
135 unsigned SretValueSize) {
136 unsigned NumOps = Outs.
size();
142 if (SretValueSize != 0) {
146 for (; i != NumOps; ++i) {
147 EVT ArgVT = Outs[i].VT;
150 NonVarArgsParams, i+1,
false)) {
151 dbgs() <<
"Call operand #" << i <<
" has unhandled type "
164 unsigned NumOps = ArgVTs.
size();
165 for (
unsigned i = 0; i != NumOps; ++i) {
166 EVT ArgVT = ArgVTs[i];
170 dbgs() <<
"Call operand #" << i <<
" has unhandled type "
182 unsigned SretValueInRegs) {
184 for (
unsigned i = 0, e = Ins.
size(); i != e; ++i) {
188 dbgs() <<
"Call result #" << i <<
" has unhandled type "
200 dbgs() <<
"Call result has unhandled type "
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, Hexagon_CCAssignFn Fn, unsigned SretValueInRegs)
bool Hexagon_CCAssignFn(unsigned ValNo, EVT ValVT, EVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Hexagon_CCState &State, int NonVarArgsParams, int CurrentParam, bool ForceMem)
void addLoc(const CCValAssign &V)
unsigned getByValSize() const
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, Hexagon_CCAssignFn Fn, unsigned SretValueInRegs)
std::string getEVTString() const
getEVTString - This function returns value type as a string, e.g. "i32".
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, Hexagon_CCAssignFn Fn, unsigned SretValueInRegs)
ID
LLVM Calling Convention Representation.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
unsigned AllocateStack(unsigned Size, unsigned Align)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
void HandleByVal(unsigned ValNo, EVT ValVT, EVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags)
Hexagon_CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM, SmallVectorImpl< CCValAssign > &locs, LLVMContext &c)
unsigned getByValAlign() const
raw_ostream & dbgs()
dbgs - Return a circular-buffered debug stream.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(DefaultAlign), cl::values(clEnumValN(DefaultAlign,"arm-default-align","Generate unaligned accesses only on hardware/OS ""combinations that are known to support them"), clEnumValN(StrictAlign,"arm-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"arm-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
uint64_t MinAlign(uint64_t A, uint64_t B)
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, Hexagon_CCAssignFn Fn, int NonVarArgsParams, unsigned SretValueSize)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
virtual const TargetRegisterInfo * getRegisterInfo() const