16 #ifndef SIREGISTERINFO_H_
17 #define SIREGISTERINFO_H_
23 class AMDGPUTargetMachine;
65 unsigned SubIdx)
const;
70 #endif // SIREGISTERINFO_H_
bool hasVGPRs(const TargetRegisterClass *RC) const
virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
virtual const TargetRegisterClass * getISARegClass(const TargetRegisterClass *RC) const
TargetRegisterInfo interface that is implemented by all hw codegen targets.
SIRegisterInfo(AMDGPUTargetMachine &tm)
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
virtual BitVector getReservedRegs(const MachineFunction &MF) const
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
bool isSGPRClass(const TargetRegisterClass *RC) const
virtual unsigned getHWRegIndex(unsigned Reg) const
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the 'base' register class for this register. e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR...