LLVM API Documentation

 All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Groups Pages
SIRegisterInfo.h
Go to the documentation of this file.
1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for SIRegisterInfo
12 //
13 //===----------------------------------------------------------------------===//
14 
15 
16 #ifndef SIREGISTERINFO_H_
17 #define SIREGISTERINFO_H_
18 
19 #include "AMDGPURegisterInfo.h"
20 
21 namespace llvm {
22 
23 class AMDGPUTargetMachine;
24 
27 
29 
30  virtual BitVector getReservedRegs(const MachineFunction &MF) const;
31 
32  virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
33  MachineFunction &MF) const;
34 
35  /// \param RC is an AMDIL reg class.
36  ///
37  /// \returns the SI register class that is equivalent to \p RC.
38  virtual const TargetRegisterClass *
39  getISARegClass(const TargetRegisterClass *RC) const;
40 
41  /// \brief get the register class of the specified type to use in the
42  /// CFGStructurizer
43  virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
44 
45  virtual unsigned getHWRegIndex(unsigned Reg) const;
46 
47  /// \brief Return the 'base' register class for this register.
48  /// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.
49  const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
50 
51  /// \returns true if this class contains only SGPR registers
52  bool isSGPRClass(const TargetRegisterClass *RC) const;
53 
54  /// \returns true if this class contains VGPR registers.
55  bool hasVGPRs(const TargetRegisterClass *RC) const;
56 
57  /// \returns A VGPR reg class with the same width as \p SRC
59  const TargetRegisterClass *SRC) const;
60 
61  /// \returns The register class that is used for a sub-register of \p RC for
62  /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
63  /// be returned.
65  unsigned SubIdx) const;
66 };
67 
68 } // End namespace llvm
69 
70 #endif // SIREGISTERINFO_H_
bool hasVGPRs(const TargetRegisterClass *RC) const
virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
virtual const TargetRegisterClass * getISARegClass(const TargetRegisterClass *RC) const
TargetRegisterInfo interface that is implemented by all hw codegen targets.
SIRegisterInfo(AMDGPUTargetMachine &tm)
AMDGPUTargetMachine & TM
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
virtual BitVector getReservedRegs(const MachineFunction &MF) const
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
bool isSGPRClass(const TargetRegisterClass *RC) const
virtual unsigned getHWRegIndex(unsigned Reg) const
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the 'base' register class for this register. e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR...