#include <SIRegisterInfo.h>

Inheritance diagram for llvm::SIRegisterInfo:

Collaboration diagram for llvm::SIRegisterInfo:

Public Member Functions
	SIRegisterInfo (AMDGPUTargetMachine &tm)

virtual BitVector	getReservedRegs (const MachineFunction &MF) const

virtual unsigned	getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const

virtual const TargetRegisterClass *	getISARegClass (const TargetRegisterClass *RC) const

virtual const TargetRegisterClass *	getCFGStructurizerRegClass (MVT VT) const
	get the register class of the specified type to use in the CFGStructurizer More...

virtual unsigned	getHWRegIndex (unsigned Reg) const

const TargetRegisterClass *	getPhysRegClass (unsigned Reg) const
	Return the 'base' register class for this register. e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc. More...

bool	isSGPRClass (const TargetRegisterClass *RC) const

bool	hasVGPRs (const TargetRegisterClass *RC) const

const TargetRegisterClass *	getEquivalentVGPRClass (const TargetRegisterClass *SRC) const

const TargetRegisterClass *	getSubRegClass (const TargetRegisterClass *RC, unsigned SubIdx) const

Public Member Functions inherited from llvm::AMDGPURegisterInfo
	AMDGPURegisterInfo (TargetMachine &tm)

unsigned	getSubRegFromChannel (unsigned Channel) const

const uint16_t *	getCalleeSavedRegs (const MachineFunction *MF) const

void	eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const

unsigned	getFrameRegister (const MachineFunction &MF) const

unsigned	getIndirectSubReg (unsigned IndirectIndex) const

Public Attributes
AMDGPUTargetMachine &	TM

Public Attributes inherited from llvm::AMDGPURegisterInfo
TargetMachine &	TM

Additional Inherited Members
Static Public Attributes inherited from llvm::AMDGPURegisterInfo
static const uint16_t	CalleeSavedReg = AMDGPU::NoRegister

Detailed Description

Definition at line 25 of file SIRegisterInfo.h.

Constructor & Destructor Documentation

SIRegisterInfo::SIRegisterInfo ( AMDGPUTargetMachine & tm )

Definition at line 22 of file SIRegisterInfo.cpp.

Member Function Documentation

const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass ( MVT VT ) const

virtual

get the register class of the specified type to use in the CFGStructurizer

Reimplemented from llvm::AMDGPURegisterInfo.

Definition at line 50 of file SIRegisterInfo.cpp.

References llvm::MVT::i32, and llvm::MVT::SimpleTy.

const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass ( const TargetRegisterClass * SRC ) const

Returns: A VGPR reg class with the same width as SRC

Definition at line 99 of file SIRegisterInfo.cpp.

References hasVGPRs().

Referenced by llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), and llvm::SIInstrInfo::moveToVALU().

unsigned SIRegisterInfo::getHWRegIndex ( unsigned Reg ) const

virtual

Reimplemented from llvm::AMDGPURegisterInfo.

Definition at line 58 of file SIRegisterInfo.cpp.

const TargetRegisterClass * SIRegisterInfo::getISARegClass ( const TargetRegisterClass * RC ) const

virtual

Parameters

RC	is an AMDIL reg class.

Returns: the SI register class that is equivalent to RC.

Reimplemented from llvm::AMDGPURegisterInfo.

Definition at line 42 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterClass::getID().

const TargetRegisterClass * SIRegisterInfo::getPhysRegClass ( unsigned Reg ) const

Return the 'base' register class for this register. e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.

Definition at line 62 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterInfo::isVirtualRegister().

unsigned SIRegisterInfo::getRegPressureLimit	(	const TargetRegisterClass *	RC,
		MachineFunction &	MF
	)		const

virtual

Definition at line 36 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterClass::getNumRegs().

BitVector SIRegisterInfo::getReservedRegs ( const MachineFunction & MF ) const

virtual

Reimplemented from llvm::AMDGPURegisterInfo.

Definition at line 27 of file SIRegisterInfo.cpp.

References llvm::AMDGPUTargetMachine::getInstrInfo(), llvm::SIInstrInfo::reserveIndirectRegisters(), llvm::BitVector::set(), TII, and TM.

const TargetRegisterClass * SIRegisterInfo::getSubRegClass	(	const TargetRegisterClass *	RC,
		unsigned	SubIdx
	)		const

Returns: The register class that is used for a sub-register of RC for the given SubIdx. If SubIdx equals NoSubRegister, RC will be returned.

Definition at line 119 of file SIRegisterInfo.cpp.

References isSGPRClass().

bool SIRegisterInfo::hasVGPRs ( const TargetRegisterClass * RC ) const