15 #define DEBUG_TYPE "postrapseudos"
60 "Post-RA pseudo instruction expansion pass",
false,
false)
70 for (
unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
90 assert(SubIdx != 0 &&
"Invalid index for insert_subreg");
91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
94 "Insert destination must be in a physical register");
96 "Inserted value must be in a physical register");
98 DEBUG(
dbgs() <<
"subreg: CONVERTING: " << *MI);
102 DEBUG(
dbgs() <<
"subreg: replaced by: " << *MI);
106 if (DstSubReg == InsReg) {
111 if (DstReg != InsReg) {
115 DEBUG(
dbgs() <<
"subreg: replace by: " << *MI);
126 CopyMI->addRegisterDefined(DstReg);
148 DEBUG(
dbgs() <<
"identity copy: " << *MI);
168 TransferImplicitDefs(MI);
171 dbgs() <<
"replaced by: " << *(--dMI);
182 <<
"********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
183 <<
"********** Function: " << MF.
getName() <<
'\n');
187 bool MadeChange =
false;
190 mbbi != mbbe; ++mbbi) {
202 if (
TII->expandPostRAPseudo(MI)) {
210 MadeChange |= LowerSubregToReg(MI);
213 MadeChange |= LowerCopy(MI);
instr_iterator erase(instr_iterator I)
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
bool isPseudo(QueryType Type=IgnoreBundle) const
bool allDefsAreDead() const
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
#define llvm_unreachable(msg)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
ID
LLVM Calling Convention Representation.
unsigned getNumOperands() const
void RemoveOperand(unsigned i)
char & ExpandPostRAPseudosID
AnalysisUsage & addPreservedID(const void *ID)
const MachineBasicBlock * getParent() const
bundle_iterator< MachineInstr, instr_iterator > iterator
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg() const
virtual const TargetInstrInfo * getInstrInfo() const
void setDesc(const MCInstrDesc &tid)
raw_ostream & dbgs()
dbgs - Return a circular-buffered debug stream.
INITIALIZE_PASS(ExpandPostRA,"postrapseudos","Post-RA pseudo instruction expansion pass", false, false) void ExpandPostRA
static bool isPhysicalRegister(unsigned Reg)
virtual void getAnalysisUsage(AnalysisUsage &AU) const
DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
const TargetMachine & getTarget() const
virtual const TargetRegisterInfo * getRegisterInfo() const
unsigned getReg() const
getReg - Returns the register number.
BasicBlockListType::iterator iterator
StringRef getName() const
DebugLoc getDebugLoc() const