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MipsSEInstrInfo.h
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1 //===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef MIPSSEINSTRUCTIONINFO_H
15 #define MIPSSEINSTRUCTIONINFO_H
16 
17 #include "MipsInstrInfo.h"
18 #include "MipsSERegisterInfo.h"
19 
20 namespace llvm {
21 
23  const MipsSERegisterInfo RI;
24  bool IsN64;
25 
26 public:
28 
29  virtual const MipsRegisterInfo &getRegisterInfo() const;
30 
31  /// isLoadFromStackSlot - If the specified machine instruction is a direct
32  /// load from a stack slot, return the virtual or physical register number of
33  /// the destination along with the FrameIndex of the loaded stack slot. If
34  /// not, return 0. This predicate must return 0 if the instruction has
35  /// any side effects other than loading from the stack slot.
36  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
37  int &FrameIndex) const;
38 
39  /// isStoreToStackSlot - If the specified machine instruction is a direct
40  /// store to a stack slot, return the virtual or physical register number of
41  /// the source reg along with the FrameIndex of the loaded stack slot. If
42  /// not, return 0. This predicate must return 0 if the instruction has
43  /// any side effects other than storing to the stack slot.
44  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
45  int &FrameIndex) const;
46 
47  virtual void copyPhysReg(MachineBasicBlock &MBB,
49  unsigned DestReg, unsigned SrcReg,
50  bool KillSrc) const;
51 
52  virtual void storeRegToStack(MachineBasicBlock &MBB,
54  unsigned SrcReg, bool isKill, int FrameIndex,
55  const TargetRegisterClass *RC,
56  const TargetRegisterInfo *TRI,
57  int64_t Offset) const;
58 
59  virtual void loadRegFromStack(MachineBasicBlock &MBB,
61  unsigned DestReg, int FrameIndex,
62  const TargetRegisterClass *RC,
63  const TargetRegisterInfo *TRI,
64  int64_t Offset) const;
65 
66  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
67 
68  virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
69 
70  /// Adjust SP by Amount bytes.
71  void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
73 
74  /// Emit a series of instructions to load an immediate. If NewImm is a
75  /// non-NULL parameter, the last instruction is not emitted, but instead
76  /// its immediate operand is returned in NewImm.
77  unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
79  unsigned *NewImm) const;
80 
81 private:
82  virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
83 
84  void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
85  unsigned Opc) const;
86 
87  std::pair<bool, bool> compareOpndSize(unsigned Opc,
88  const MachineFunction &MF) const;
89 
90  void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
91  unsigned NewOpc) const;
92 
93  void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
94  unsigned LoOpc, unsigned HiOpc,
95  bool HasExplicitDef) const;
96 
97  /// Expand pseudo Int-to-FP conversion instructions.
98  ///
99  /// For example, the following pseudo instruction
100  /// PseudoCVT_D32_W D2, A5
101  /// gets expanded into these two instructions:
102  /// MTC1 F4, A5
103  /// CVT_D32_W D2, F4
104  ///
105  /// We do this expansion post-RA to avoid inserting a floating point copy
106  /// instruction between MTC1 and CVT_D32_W.
107  void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
108  unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
109 
110  void expandExtractElementF64(MachineBasicBlock &MBB,
111  MachineBasicBlock::iterator I, bool FP64) const;
112  void expandBuildPairF64(MachineBasicBlock &MBB,
113  MachineBasicBlock::iterator I, bool FP64) const;
114  void expandEhReturn(MachineBasicBlock &MBB,
116 };
117 
118 }
119 
120 #endif
virtual const MipsRegisterInfo & getRegisterInfo() const
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
Adjust SP by Amount bytes.
virtual unsigned getOppositeBranchOpc(unsigned Opc) const
MipsTargetMachine & TM
Definition: MipsInstrInfo.h:32
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
MipsSEInstrInfo(MipsTargetMachine &TM)
bundle_iterator< MachineInstr, instr_iterator > iterator
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const
#define I(x, y, z)
Definition: MD5.cpp:54
virtual void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, DebugLoc DL, unsigned *NewImm) const
virtual unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const