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PPCAsmParser.cpp
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1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCInstrInfo.h"
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCParser/MCAsmLexer.h"
20 #include "llvm/MC/MCParser/MCAsmParser.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/Support/SourceMgr.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Support/raw_ostream.h"
30 
31 using namespace llvm;
32 
33 namespace {
34 
35 static unsigned RRegs[32] = {
36  PPC::R0, PPC::R1, PPC::R2, PPC::R3,
37  PPC::R4, PPC::R5, PPC::R6, PPC::R7,
38  PPC::R8, PPC::R9, PPC::R10, PPC::R11,
39  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
40  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
41  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
42  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
43  PPC::R28, PPC::R29, PPC::R30, PPC::R31
44 };
45 static unsigned RRegsNoR0[32] = {
46  PPC::ZERO,
47  PPC::R1, PPC::R2, PPC::R3,
48  PPC::R4, PPC::R5, PPC::R6, PPC::R7,
49  PPC::R8, PPC::R9, PPC::R10, PPC::R11,
50  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
51  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
52  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
53  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
54  PPC::R28, PPC::R29, PPC::R30, PPC::R31
55 };
56 static unsigned XRegs[32] = {
57  PPC::X0, PPC::X1, PPC::X2, PPC::X3,
58  PPC::X4, PPC::X5, PPC::X6, PPC::X7,
59  PPC::X8, PPC::X9, PPC::X10, PPC::X11,
60  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
61  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
62  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
63  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
64  PPC::X28, PPC::X29, PPC::X30, PPC::X31
65 };
66 static unsigned XRegsNoX0[32] = {
67  PPC::ZERO8,
68  PPC::X1, PPC::X2, PPC::X3,
69  PPC::X4, PPC::X5, PPC::X6, PPC::X7,
70  PPC::X8, PPC::X9, PPC::X10, PPC::X11,
71  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
72  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
73  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
74  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
75  PPC::X28, PPC::X29, PPC::X30, PPC::X31
76 };
77 static unsigned FRegs[32] = {
78  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
79  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
80  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
81  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
82  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
83  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
84  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
85  PPC::F28, PPC::F29, PPC::F30, PPC::F31
86 };
87 static unsigned VRegs[32] = {
88  PPC::V0, PPC::V1, PPC::V2, PPC::V3,
89  PPC::V4, PPC::V5, PPC::V6, PPC::V7,
90  PPC::V8, PPC::V9, PPC::V10, PPC::V11,
91  PPC::V12, PPC::V13, PPC::V14, PPC::V15,
92  PPC::V16, PPC::V17, PPC::V18, PPC::V19,
93  PPC::V20, PPC::V21, PPC::V22, PPC::V23,
94  PPC::V24, PPC::V25, PPC::V26, PPC::V27,
95  PPC::V28, PPC::V29, PPC::V30, PPC::V31
96 };
97 static unsigned CRBITRegs[32] = {
98  PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
99  PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
100  PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
101  PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
102  PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
103  PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
104  PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
105  PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
106 };
107 static unsigned CRRegs[8] = {
108  PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
109  PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
110 };
111 
112 // Evaluate an expression containing condition register
113 // or condition register field symbols. Returns positive
114 // value on success, or -1 on error.
115 static int64_t
116 EvaluateCRExpr(const MCExpr *E) {
117  switch (E->getKind()) {
118  case MCExpr::Target:
119  return -1;
120 
121  case MCExpr::Constant: {
122  int64_t Res = cast<MCConstantExpr>(E)->getValue();
123  return Res < 0 ? -1 : Res;
124  }
125 
126  case MCExpr::SymbolRef: {
127  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
128  StringRef Name = SRE->getSymbol().getName();
129 
130  if (Name == "lt") return 0;
131  if (Name == "gt") return 1;
132  if (Name == "eq") return 2;
133  if (Name == "so") return 3;
134  if (Name == "un") return 3;
135 
136  if (Name == "cr0") return 0;
137  if (Name == "cr1") return 1;
138  if (Name == "cr2") return 2;
139  if (Name == "cr3") return 3;
140  if (Name == "cr4") return 4;
141  if (Name == "cr5") return 5;
142  if (Name == "cr6") return 6;
143  if (Name == "cr7") return 7;
144 
145  return -1;
146  }
147 
148  case MCExpr::Unary:
149  return -1;
150 
151  case MCExpr::Binary: {
152  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
153  int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
154  int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
155  int64_t Res;
156 
157  if (LHSVal < 0 || RHSVal < 0)
158  return -1;
159 
160  switch (BE->getOpcode()) {
161  default: return -1;
162  case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
163  case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
164  }
165 
166  return Res < 0 ? -1 : Res;
167  }
168  }
169 
170  llvm_unreachable("Invalid expression kind!");
171 }
172 
173 struct PPCOperand;
174 
175 class PPCAsmParser : public MCTargetAsmParser {
176  MCSubtargetInfo &STI;
177  MCAsmParser &Parser;
178  const MCInstrInfo &MII;
179  bool IsPPC64;
180 
181  MCAsmParser &getParser() const { return Parser; }
182  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
183 
184  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
185  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
186 
187  bool isPPC64() const { return IsPPC64; }
188 
189  bool MatchRegisterName(const AsmToken &Tok,
190  unsigned &RegNo, int64_t &IntVal);
191 
192  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
193 
194  const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
195  PPCMCExpr::VariantKind &Variant);
196  const MCExpr *FixupVariantKind(const MCExpr *E);
197  bool ParseExpression(const MCExpr *&EVal);
198 
199  bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
200 
201  bool ParseDirectiveWord(unsigned Size, SMLoc L);
202  bool ParseDirectiveTC(unsigned Size, SMLoc L);
203  bool ParseDirectiveMachine(SMLoc L);
204 
205  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
206  SmallVectorImpl<MCParsedAsmOperand*> &Operands,
207  MCStreamer &Out, unsigned &ErrorInfo,
208  bool MatchingInlineAsm);
209 
210  void ProcessInstruction(MCInst &Inst,
211  const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
212 
213  /// @name Auto-generated Match Functions
214  /// {
215 
216 #define GET_ASSEMBLER_HEADER
217 #include "PPCGenAsmMatcher.inc"
218 
219  /// }
220 
221 
222 public:
223  PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
224  const MCInstrInfo &_MII)
225  : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
226  // Check for 64-bit vs. 32-bit pointer mode.
227  Triple TheTriple(STI.getTargetTriple());
228  IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
229  TheTriple.getArch() == Triple::ppc64le);
230  // Initialize the set of available features.
231  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
232  }
233 
234  virtual bool ParseInstruction(ParseInstructionInfo &Info,
235  StringRef Name, SMLoc NameLoc,
236  SmallVectorImpl<MCParsedAsmOperand*> &Operands);
237 
238  virtual bool ParseDirective(AsmToken DirectiveID);
239 
240  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
241 
242  virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
243  MCSymbolRefExpr::VariantKind,
244  MCContext &Ctx);
245 };
246 
247 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
248 /// instruction.
249 struct PPCOperand : public MCParsedAsmOperand {
250  enum KindTy {
251  Token,
252  Immediate,
253  Expression,
254  TLSRegister
255  } Kind;
256 
257  SMLoc StartLoc, EndLoc;
258  bool IsPPC64;
259 
260  struct TokOp {
261  const char *Data;
262  unsigned Length;
263  };
264 
265  struct ImmOp {
266  int64_t Val;
267  };
268 
269  struct ExprOp {
270  const MCExpr *Val;
271  int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
272  };
273 
274  struct TLSRegOp {
275  const MCSymbolRefExpr *Sym;
276  };
277 
278  union {
279  struct TokOp Tok;
280  struct ImmOp Imm;
281  struct ExprOp Expr;
282  struct TLSRegOp TLSReg;
283  };
284 
285  PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
286 public:
287  PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
288  Kind = o.Kind;
289  StartLoc = o.StartLoc;
290  EndLoc = o.EndLoc;
291  IsPPC64 = o.IsPPC64;
292  switch (Kind) {
293  case Token:
294  Tok = o.Tok;
295  break;
296  case Immediate:
297  Imm = o.Imm;
298  break;
299  case Expression:
300  Expr = o.Expr;
301  break;
302  case TLSRegister:
303  TLSReg = o.TLSReg;
304  break;
305  }
306  }
307 
308  /// getStartLoc - Get the location of the first token of this operand.
309  SMLoc getStartLoc() const { return StartLoc; }
310 
311  /// getEndLoc - Get the location of the last token of this operand.
312  SMLoc getEndLoc() const { return EndLoc; }
313 
314  /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
315  bool isPPC64() const { return IsPPC64; }
316 
317  int64_t getImm() const {
318  assert(Kind == Immediate && "Invalid access!");
319  return Imm.Val;
320  }
321 
322  const MCExpr *getExpr() const {
323  assert(Kind == Expression && "Invalid access!");
324  return Expr.Val;
325  }
326 
327  int64_t getExprCRVal() const {
328  assert(Kind == Expression && "Invalid access!");
329  return Expr.CRVal;
330  }
331 
332  const MCExpr *getTLSReg() const {
333  assert(Kind == TLSRegister && "Invalid access!");
334  return TLSReg.Sym;
335  }
336 
337  unsigned getReg() const {
338  assert(isRegNumber() && "Invalid access!");
339  return (unsigned) Imm.Val;
340  }
341 
342  unsigned getCCReg() const {
343  assert(isCCRegNumber() && "Invalid access!");
344  return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
345  }
346 
347  unsigned getCRBit() const {
348  assert(isCRBitNumber() && "Invalid access!");
349  return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
350  }
351 
352  unsigned getCRBitMask() const {
353  assert(isCRBitMask() && "Invalid access!");
354  return 7 - countTrailingZeros<uint64_t>(Imm.Val);
355  }
356 
357  bool isToken() const { return Kind == Token; }
358  bool isImm() const { return Kind == Immediate || Kind == Expression; }
359  bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
360  bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
361  bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
362  bool isU16Imm() const { return Kind == Expression ||
363  (Kind == Immediate && isUInt<16>(getImm())); }
364  bool isS16Imm() const { return Kind == Expression ||
365  (Kind == Immediate && isInt<16>(getImm())); }
366  bool isS16ImmX4() const { return Kind == Expression ||
367  (Kind == Immediate && isInt<16>(getImm()) &&
368  (getImm() & 3) == 0); }
369  bool isS17Imm() const { return Kind == Expression ||
370  (Kind == Immediate && isInt<17>(getImm())); }
371  bool isTLSReg() const { return Kind == TLSRegister; }
372  bool isDirectBr() const { return Kind == Expression ||
373  (Kind == Immediate && isInt<26>(getImm()) &&
374  (getImm() & 3) == 0); }
375  bool isCondBr() const { return Kind == Expression ||
376  (Kind == Immediate && isInt<16>(getImm()) &&
377  (getImm() & 3) == 0); }
378  bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
379  bool isCCRegNumber() const { return (Kind == Expression
380  && isUInt<3>(getExprCRVal())) ||
381  (Kind == Immediate
382  && isUInt<3>(getImm())); }
383  bool isCRBitNumber() const { return (Kind == Expression
384  && isUInt<5>(getExprCRVal())) ||
385  (Kind == Immediate
386  && isUInt<5>(getImm())); }
387  bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
388  isPowerOf2_32(getImm()); }
389  bool isMem() const { return false; }
390  bool isReg() const { return false; }
391 
392  void addRegOperands(MCInst &Inst, unsigned N) const {
393  llvm_unreachable("addRegOperands");
394  }
395 
396  void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
397  assert(N == 1 && "Invalid number of operands!");
398  Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
399  }
400 
401  void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
402  assert(N == 1 && "Invalid number of operands!");
403  Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
404  }
405 
406  void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
407  assert(N == 1 && "Invalid number of operands!");
408  Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
409  }
410 
411  void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
412  assert(N == 1 && "Invalid number of operands!");
413  Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
414  }
415 
416  void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
417  if (isPPC64())
418  addRegG8RCOperands(Inst, N);
419  else
420  addRegGPRCOperands(Inst, N);
421  }
422 
423  void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
424  if (isPPC64())
425  addRegG8RCNoX0Operands(Inst, N);
426  else
427  addRegGPRCNoR0Operands(Inst, N);
428  }
429 
430  void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
431  assert(N == 1 && "Invalid number of operands!");
432  Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
433  }
434 
435  void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
436  assert(N == 1 && "Invalid number of operands!");
437  Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
438  }
439 
440  void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
441  assert(N == 1 && "Invalid number of operands!");
442  Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
443  }
444 
445  void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
446  assert(N == 1 && "Invalid number of operands!");
447  Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
448  }
449 
450  void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
451  assert(N == 1 && "Invalid number of operands!");
452  Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
453  }
454 
455  void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
456  assert(N == 1 && "Invalid number of operands!");
457  Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
458  }
459 
460  void addImmOperands(MCInst &Inst, unsigned N) const {
461  assert(N == 1 && "Invalid number of operands!");
462  if (Kind == Immediate)
463  Inst.addOperand(MCOperand::CreateImm(getImm()));
464  else
465  Inst.addOperand(MCOperand::CreateExpr(getExpr()));
466  }
467 
468  void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
469  assert(N == 1 && "Invalid number of operands!");
470  if (Kind == Immediate)
471  Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
472  else
473  Inst.addOperand(MCOperand::CreateExpr(getExpr()));
474  }
475 
476  void addTLSRegOperands(MCInst &Inst, unsigned N) const {
477  assert(N == 1 && "Invalid number of operands!");
478  Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
479  }
480 
481  StringRef getToken() const {
482  assert(Kind == Token && "Invalid access!");
483  return StringRef(Tok.Data, Tok.Length);
484  }
485 
486  virtual void print(raw_ostream &OS) const;
487 
488  static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
489  PPCOperand *Op = new PPCOperand(Token);
490  Op->Tok.Data = Str.data();
491  Op->Tok.Length = Str.size();
492  Op->StartLoc = S;
493  Op->EndLoc = S;
494  Op->IsPPC64 = IsPPC64;
495  return Op;
496  }
497 
498  static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S,
499  bool IsPPC64) {
500  // Allocate extra memory for the string and copy it.
501  void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
502  PPCOperand *Op = new (Mem) PPCOperand(Token);
503  Op->Tok.Data = (const char *)(Op + 1);
504  Op->Tok.Length = Str.size();
505  std::memcpy((char *)(Op + 1), Str.data(), Str.size());
506  Op->StartLoc = S;
507  Op->EndLoc = S;
508  Op->IsPPC64 = IsPPC64;
509  return Op;
510  }
511 
512  static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
513  PPCOperand *Op = new PPCOperand(Immediate);
514  Op->Imm.Val = Val;
515  Op->StartLoc = S;
516  Op->EndLoc = E;
517  Op->IsPPC64 = IsPPC64;
518  return Op;
519  }
520 
521  static PPCOperand *CreateExpr(const MCExpr *Val,
522  SMLoc S, SMLoc E, bool IsPPC64) {
523  PPCOperand *Op = new PPCOperand(Expression);
524  Op->Expr.Val = Val;
525  Op->Expr.CRVal = EvaluateCRExpr(Val);
526  Op->StartLoc = S;
527  Op->EndLoc = E;
528  Op->IsPPC64 = IsPPC64;
529  return Op;
530  }
531 
532  static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
533  SMLoc S, SMLoc E, bool IsPPC64) {
534  PPCOperand *Op = new PPCOperand(TLSRegister);
535  Op->TLSReg.Sym = Sym;
536  Op->StartLoc = S;
537  Op->EndLoc = E;
538  Op->IsPPC64 = IsPPC64;
539  return Op;
540  }
541 
542  static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
543  SMLoc S, SMLoc E, bool IsPPC64) {
544  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
545  return CreateImm(CE->getValue(), S, E, IsPPC64);
546 
547  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
548  if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
549  return CreateTLSReg(SRE, S, E, IsPPC64);
550 
551  return CreateExpr(Val, S, E, IsPPC64);
552  }
553 };
554 
555 } // end anonymous namespace.
556 
557 void PPCOperand::print(raw_ostream &OS) const {
558  switch (Kind) {
559  case Token:
560  OS << "'" << getToken() << "'";
561  break;
562  case Immediate:
563  OS << getImm();
564  break;
565  case Expression:
566  getExpr()->print(OS);
567  break;
568  case TLSRegister:
569  getTLSReg()->print(OS);
570  break;
571  }
572 }
573 
574 
575 void PPCAsmParser::
576 ProcessInstruction(MCInst &Inst,
577  const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
578  int Opcode = Inst.getOpcode();
579  switch (Opcode) {
580  case PPC::LAx: {
581  MCInst TmpInst;
582  TmpInst.setOpcode(PPC::LA);
583  TmpInst.addOperand(Inst.getOperand(0));
584  TmpInst.addOperand(Inst.getOperand(2));
585  TmpInst.addOperand(Inst.getOperand(1));
586  Inst = TmpInst;
587  break;
588  }
589  case PPC::SUBI: {
590  MCInst TmpInst;
591  int64_t N = Inst.getOperand(2).getImm();
592  TmpInst.setOpcode(PPC::ADDI);
593  TmpInst.addOperand(Inst.getOperand(0));
594  TmpInst.addOperand(Inst.getOperand(1));
595  TmpInst.addOperand(MCOperand::CreateImm(-N));
596  Inst = TmpInst;
597  break;
598  }
599  case PPC::SUBIS: {
600  MCInst TmpInst;
601  int64_t N = Inst.getOperand(2).getImm();
602  TmpInst.setOpcode(PPC::ADDIS);
603  TmpInst.addOperand(Inst.getOperand(0));
604  TmpInst.addOperand(Inst.getOperand(1));
605  TmpInst.addOperand(MCOperand::CreateImm(-N));
606  Inst = TmpInst;
607  break;
608  }
609  case PPC::SUBIC: {
610  MCInst TmpInst;
611  int64_t N = Inst.getOperand(2).getImm();
612  TmpInst.setOpcode(PPC::ADDIC);
613  TmpInst.addOperand(Inst.getOperand(0));
614  TmpInst.addOperand(Inst.getOperand(1));
615  TmpInst.addOperand(MCOperand::CreateImm(-N));
616  Inst = TmpInst;
617  break;
618  }
619  case PPC::SUBICo: {
620  MCInst TmpInst;
621  int64_t N = Inst.getOperand(2).getImm();
622  TmpInst.setOpcode(PPC::ADDICo);
623  TmpInst.addOperand(Inst.getOperand(0));
624  TmpInst.addOperand(Inst.getOperand(1));
625  TmpInst.addOperand(MCOperand::CreateImm(-N));
626  Inst = TmpInst;
627  break;
628  }
629  case PPC::EXTLWI:
630  case PPC::EXTLWIo: {
631  MCInst TmpInst;
632  int64_t N = Inst.getOperand(2).getImm();
633  int64_t B = Inst.getOperand(3).getImm();
634  TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
635  TmpInst.addOperand(Inst.getOperand(0));
636  TmpInst.addOperand(Inst.getOperand(1));
637  TmpInst.addOperand(MCOperand::CreateImm(B));
638  TmpInst.addOperand(MCOperand::CreateImm(0));
639  TmpInst.addOperand(MCOperand::CreateImm(N - 1));
640  Inst = TmpInst;
641  break;
642  }
643  case PPC::EXTRWI:
644  case PPC::EXTRWIo: {
645  MCInst TmpInst;
646  int64_t N = Inst.getOperand(2).getImm();
647  int64_t B = Inst.getOperand(3).getImm();
648  TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
649  TmpInst.addOperand(Inst.getOperand(0));
650  TmpInst.addOperand(Inst.getOperand(1));
651  TmpInst.addOperand(MCOperand::CreateImm(B + N));
652  TmpInst.addOperand(MCOperand::CreateImm(32 - N));
653  TmpInst.addOperand(MCOperand::CreateImm(31));
654  Inst = TmpInst;
655  break;
656  }
657  case PPC::INSLWI:
658  case PPC::INSLWIo: {
659  MCInst TmpInst;
660  int64_t N = Inst.getOperand(2).getImm();
661  int64_t B = Inst.getOperand(3).getImm();
662  TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
663  TmpInst.addOperand(Inst.getOperand(0));
664  TmpInst.addOperand(Inst.getOperand(0));
665  TmpInst.addOperand(Inst.getOperand(1));
666  TmpInst.addOperand(MCOperand::CreateImm(32 - B));
667  TmpInst.addOperand(MCOperand::CreateImm(B));
668  TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
669  Inst = TmpInst;
670  break;
671  }
672  case PPC::INSRWI:
673  case PPC::INSRWIo: {
674  MCInst TmpInst;
675  int64_t N = Inst.getOperand(2).getImm();
676  int64_t B = Inst.getOperand(3).getImm();
677  TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
678  TmpInst.addOperand(Inst.getOperand(0));
679  TmpInst.addOperand(Inst.getOperand(0));
680  TmpInst.addOperand(Inst.getOperand(1));
681  TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
682  TmpInst.addOperand(MCOperand::CreateImm(B));
683  TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
684  Inst = TmpInst;
685  break;
686  }
687  case PPC::ROTRWI:
688  case PPC::ROTRWIo: {
689  MCInst TmpInst;
690  int64_t N = Inst.getOperand(2).getImm();
691  TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
692  TmpInst.addOperand(Inst.getOperand(0));
693  TmpInst.addOperand(Inst.getOperand(1));
694  TmpInst.addOperand(MCOperand::CreateImm(32 - N));
695  TmpInst.addOperand(MCOperand::CreateImm(0));
696  TmpInst.addOperand(MCOperand::CreateImm(31));
697  Inst = TmpInst;
698  break;
699  }
700  case PPC::SLWI:
701  case PPC::SLWIo: {
702  MCInst TmpInst;
703  int64_t N = Inst.getOperand(2).getImm();
704  TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
705  TmpInst.addOperand(Inst.getOperand(0));
706  TmpInst.addOperand(Inst.getOperand(1));
707  TmpInst.addOperand(MCOperand::CreateImm(N));
708  TmpInst.addOperand(MCOperand::CreateImm(0));
709  TmpInst.addOperand(MCOperand::CreateImm(31 - N));
710  Inst = TmpInst;
711  break;
712  }
713  case PPC::SRWI:
714  case PPC::SRWIo: {
715  MCInst TmpInst;
716  int64_t N = Inst.getOperand(2).getImm();
717  TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
718  TmpInst.addOperand(Inst.getOperand(0));
719  TmpInst.addOperand(Inst.getOperand(1));
720  TmpInst.addOperand(MCOperand::CreateImm(32 - N));
721  TmpInst.addOperand(MCOperand::CreateImm(N));
722  TmpInst.addOperand(MCOperand::CreateImm(31));
723  Inst = TmpInst;
724  break;
725  }
726  case PPC::CLRRWI:
727  case PPC::CLRRWIo: {
728  MCInst TmpInst;
729  int64_t N = Inst.getOperand(2).getImm();
730  TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
731  TmpInst.addOperand(Inst.getOperand(0));
732  TmpInst.addOperand(Inst.getOperand(1));
733  TmpInst.addOperand(MCOperand::CreateImm(0));
734  TmpInst.addOperand(MCOperand::CreateImm(0));
735  TmpInst.addOperand(MCOperand::CreateImm(31 - N));
736  Inst = TmpInst;
737  break;
738  }
739  case PPC::CLRLSLWI:
740  case PPC::CLRLSLWIo: {
741  MCInst TmpInst;
742  int64_t B = Inst.getOperand(2).getImm();
743  int64_t N = Inst.getOperand(3).getImm();
744  TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
745  TmpInst.addOperand(Inst.getOperand(0));
746  TmpInst.addOperand(Inst.getOperand(1));
747  TmpInst.addOperand(MCOperand::CreateImm(N));
748  TmpInst.addOperand(MCOperand::CreateImm(B - N));
749  TmpInst.addOperand(MCOperand::CreateImm(31 - N));
750  Inst = TmpInst;
751  break;
752  }
753  case PPC::EXTLDI:
754  case PPC::EXTLDIo: {
755  MCInst TmpInst;
756  int64_t N = Inst.getOperand(2).getImm();
757  int64_t B = Inst.getOperand(3).getImm();
758  TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
759  TmpInst.addOperand(Inst.getOperand(0));
760  TmpInst.addOperand(Inst.getOperand(1));
761  TmpInst.addOperand(MCOperand::CreateImm(B));
762  TmpInst.addOperand(MCOperand::CreateImm(N - 1));
763  Inst = TmpInst;
764  break;
765  }
766  case PPC::EXTRDI:
767  case PPC::EXTRDIo: {
768  MCInst TmpInst;
769  int64_t N = Inst.getOperand(2).getImm();
770  int64_t B = Inst.getOperand(3).getImm();
771  TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
772  TmpInst.addOperand(Inst.getOperand(0));
773  TmpInst.addOperand(Inst.getOperand(1));
774  TmpInst.addOperand(MCOperand::CreateImm(B + N));
775  TmpInst.addOperand(MCOperand::CreateImm(64 - N));
776  Inst = TmpInst;
777  break;
778  }
779  case PPC::INSRDI:
780  case PPC::INSRDIo: {
781  MCInst TmpInst;
782  int64_t N = Inst.getOperand(2).getImm();
783  int64_t B = Inst.getOperand(3).getImm();
784  TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
785  TmpInst.addOperand(Inst.getOperand(0));
786  TmpInst.addOperand(Inst.getOperand(0));
787  TmpInst.addOperand(Inst.getOperand(1));
788  TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
789  TmpInst.addOperand(MCOperand::CreateImm(B));
790  Inst = TmpInst;
791  break;
792  }
793  case PPC::ROTRDI:
794  case PPC::ROTRDIo: {
795  MCInst TmpInst;
796  int64_t N = Inst.getOperand(2).getImm();
797  TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
798  TmpInst.addOperand(Inst.getOperand(0));
799  TmpInst.addOperand(Inst.getOperand(1));
800  TmpInst.addOperand(MCOperand::CreateImm(64 - N));
801  TmpInst.addOperand(MCOperand::CreateImm(0));
802  Inst = TmpInst;
803  break;
804  }
805  case PPC::SLDI:
806  case PPC::SLDIo: {
807  MCInst TmpInst;
808  int64_t N = Inst.getOperand(2).getImm();
809  TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
810  TmpInst.addOperand(Inst.getOperand(0));
811  TmpInst.addOperand(Inst.getOperand(1));
812  TmpInst.addOperand(MCOperand::CreateImm(N));
813  TmpInst.addOperand(MCOperand::CreateImm(63 - N));
814  Inst = TmpInst;
815  break;
816  }
817  case PPC::SRDI:
818  case PPC::SRDIo: {
819  MCInst TmpInst;
820  int64_t N = Inst.getOperand(2).getImm();
821  TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
822  TmpInst.addOperand(Inst.getOperand(0));
823  TmpInst.addOperand(Inst.getOperand(1));
824  TmpInst.addOperand(MCOperand::CreateImm(64 - N));
825  TmpInst.addOperand(MCOperand::CreateImm(N));
826  Inst = TmpInst;
827  break;
828  }
829  case PPC::CLRRDI:
830  case PPC::CLRRDIo: {
831  MCInst TmpInst;
832  int64_t N = Inst.getOperand(2).getImm();
833  TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
834  TmpInst.addOperand(Inst.getOperand(0));
835  TmpInst.addOperand(Inst.getOperand(1));
836  TmpInst.addOperand(MCOperand::CreateImm(0));
837  TmpInst.addOperand(MCOperand::CreateImm(63 - N));
838  Inst = TmpInst;
839  break;
840  }
841  case PPC::CLRLSLDI:
842  case PPC::CLRLSLDIo: {
843  MCInst TmpInst;
844  int64_t B = Inst.getOperand(2).getImm();
845  int64_t N = Inst.getOperand(3).getImm();
846  TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
847  TmpInst.addOperand(Inst.getOperand(0));
848  TmpInst.addOperand(Inst.getOperand(1));
849  TmpInst.addOperand(MCOperand::CreateImm(N));
850  TmpInst.addOperand(MCOperand::CreateImm(B - N));
851  Inst = TmpInst;
852  break;
853  }
854  }
855 }
856 
857 bool PPCAsmParser::
858 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
859  SmallVectorImpl<MCParsedAsmOperand*> &Operands,
860  MCStreamer &Out, unsigned &ErrorInfo,
861  bool MatchingInlineAsm) {
862  MCInst Inst;
863 
864  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
865  default: break;
866  case Match_Success:
867  // Post-process instructions (typically extended mnemonics)
868  ProcessInstruction(Inst, Operands);
869  Inst.setLoc(IDLoc);
870  Out.EmitInstruction(Inst);
871  return false;
872  case Match_MissingFeature:
873  return Error(IDLoc, "instruction use requires an option to be enabled");
874  case Match_MnemonicFail:
875  return Error(IDLoc, "unrecognized instruction mnemonic");
876  case Match_InvalidOperand: {
877  SMLoc ErrorLoc = IDLoc;
878  if (ErrorInfo != ~0U) {
879  if (ErrorInfo >= Operands.size())
880  return Error(IDLoc, "too few operands for instruction");
881 
882  ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
883  if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
884  }
885 
886  return Error(ErrorLoc, "invalid operand for instruction");
887  }
888  }
889 
890  llvm_unreachable("Implement any new match types added!");
891 }
892 
893 bool PPCAsmParser::
894 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
895  if (Tok.is(AsmToken::Identifier)) {
896  StringRef Name = Tok.getString();
897 
898  if (Name.equals_lower("lr")) {
899  RegNo = isPPC64()? PPC::LR8 : PPC::LR;
900  IntVal = 8;
901  return false;
902  } else if (Name.equals_lower("ctr")) {
903  RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
904  IntVal = 9;
905  return false;
906  } else if (Name.equals_lower("vrsave")) {
907  RegNo = PPC::VRSAVE;
908  IntVal = 256;
909  return false;
910  } else if (Name.startswith_lower("r") &&
911  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
912  RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
913  return false;
914  } else if (Name.startswith_lower("f") &&
915  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
916  RegNo = FRegs[IntVal];
917  return false;
918  } else if (Name.startswith_lower("v") &&
919  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
920  RegNo = VRegs[IntVal];
921  return false;
922  } else if (Name.startswith_lower("cr") &&
923  !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
924  RegNo = CRRegs[IntVal];
925  return false;
926  }
927  }
928 
929  return true;
930 }
931 
932 bool PPCAsmParser::
933 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
934  const AsmToken &Tok = Parser.getTok();
935  StartLoc = Tok.getLoc();
936  EndLoc = Tok.getEndLoc();
937  RegNo = 0;
938  int64_t IntVal;
939 
940  if (!MatchRegisterName(Tok, RegNo, IntVal)) {
941  Parser.Lex(); // Eat identifier token.
942  return false;
943  }
944 
945  return Error(StartLoc, "invalid register name");
946 }
947 
948 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
949 /// the expression and check for VK_PPC_LO/HI/HA
950 /// symbol variants. If all symbols with modifier use the same
951 /// variant, return the corresponding PPCMCExpr::VariantKind,
952 /// and a modified expression using the default symbol variant.
953 /// Otherwise, return NULL.
954 const MCExpr *PPCAsmParser::
955 ExtractModifierFromExpr(const MCExpr *E,
956  PPCMCExpr::VariantKind &Variant) {
957  MCContext &Context = getParser().getContext();
958  Variant = PPCMCExpr::VK_PPC_None;
959 
960  switch (E->getKind()) {
961  case MCExpr::Target:
962  case MCExpr::Constant:
963  return 0;
964 
965  case MCExpr::SymbolRef: {
966  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
967 
968  switch (SRE->getKind()) {
969  case MCSymbolRefExpr::VK_PPC_LO:
970  Variant = PPCMCExpr::VK_PPC_LO;
971  break;
972  case MCSymbolRefExpr::VK_PPC_HI:
973  Variant = PPCMCExpr::VK_PPC_HI;
974  break;
975  case MCSymbolRefExpr::VK_PPC_HA:
976  Variant = PPCMCExpr::VK_PPC_HA;
977  break;
978  case MCSymbolRefExpr::VK_PPC_HIGHER:
979  Variant = PPCMCExpr::VK_PPC_HIGHER;
980  break;
981  case MCSymbolRefExpr::VK_PPC_HIGHERA:
982  Variant = PPCMCExpr::VK_PPC_HIGHERA;
983  break;
984  case MCSymbolRefExpr::VK_PPC_HIGHEST:
985  Variant = PPCMCExpr::VK_PPC_HIGHEST;
986  break;
987  case MCSymbolRefExpr::VK_PPC_HIGHESTA:
988  Variant = PPCMCExpr::VK_PPC_HIGHESTA;
989  break;
990  default:
991  return 0;
992  }
993 
994  return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
995  }
996 
997  case MCExpr::Unary: {
998  const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
999  const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1000  if (!Sub)
1001  return 0;
1002  return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1003  }
1004 
1005  case MCExpr::Binary: {
1006  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1007  PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1008  const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1009  const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1010 
1011  if (!LHS && !RHS)
1012  return 0;
1013 
1014  if (!LHS) LHS = BE->getLHS();
1015  if (!RHS) RHS = BE->getRHS();
1016 
1017  if (LHSVariant == PPCMCExpr::VK_PPC_None)
1018  Variant = RHSVariant;
1019  else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1020  Variant = LHSVariant;
1021  else if (LHSVariant == RHSVariant)
1022  Variant = LHSVariant;
1023  else
1024  return 0;
1025 
1026  return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1027  }
1028  }
1029 
1030  llvm_unreachable("Invalid expression kind!");
1031 }
1032 
1033 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1034 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1035 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1036 /// FIXME: This is a hack.
1037 const MCExpr *PPCAsmParser::
1038 FixupVariantKind(const MCExpr *E) {
1039  MCContext &Context = getParser().getContext();
1040 
1041  switch (E->getKind()) {
1042  case MCExpr::Target:
1043  case MCExpr::Constant:
1044  return E;
1045 
1046  case MCExpr::SymbolRef: {
1047  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1048  MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1049 
1050  switch (SRE->getKind()) {
1051  case MCSymbolRefExpr::VK_TLSGD:
1052  Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1053  break;
1054  case MCSymbolRefExpr::VK_TLSLD:
1055  Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1056  break;
1057  default:
1058  return E;
1059  }
1060  return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1061  }
1062 
1063  case MCExpr::Unary: {
1064  const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1065  const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1066  if (Sub == UE->getSubExpr())
1067  return E;
1068  return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1069  }
1070 
1071  case MCExpr::Binary: {
1072  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1073  const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1074  const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1075  if (LHS == BE->getLHS() && RHS == BE->getRHS())
1076  return E;
1077  return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1078  }
1079  }
1080 
1081  llvm_unreachable("Invalid expression kind!");
1082 }
1083 
1084 /// Parse an expression. This differs from the default "parseExpression"
1085 /// in that it handles complex \code @l/@ha \endcode modifiers.
1086 bool PPCAsmParser::
1087 ParseExpression(const MCExpr *&EVal) {
1088  if (getParser().parseExpression(EVal))
1089  return true;
1090 
1091  EVal = FixupVariantKind(EVal);
1092 
1093  PPCMCExpr::VariantKind Variant;
1094  const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1095  if (E)
1096  EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1097 
1098  return false;
1099 }
1100 
1101 bool PPCAsmParser::
1102 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1103  SMLoc S = Parser.getTok().getLoc();
1104  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1105  const MCExpr *EVal;
1106  PPCOperand *Op;
1107 
1108  // Attempt to parse the next token as an immediate
1109  switch (getLexer().getKind()) {
1110  // Special handling for register names. These are interpreted
1111  // as immediates corresponding to the register number.
1112  case AsmToken::Percent:
1113  Parser.Lex(); // Eat the '%'.
1114  unsigned RegNo;
1115  int64_t IntVal;
1116  if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1117  Parser.Lex(); // Eat the identifier token.
1118  Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1119  Operands.push_back(Op);
1120  return false;
1121  }
1122  return Error(S, "invalid register name");
1123 
1124  // All other expressions
1125  case AsmToken::LParen:
1126  case AsmToken::Plus:
1127  case AsmToken::Minus:
1128  case AsmToken::Integer:
1129  case AsmToken::Identifier:
1130  case AsmToken::Dot:
1131  case AsmToken::Dollar:
1132  if (!ParseExpression(EVal))
1133  break;
1134  /* fall through */
1135  default:
1136  return Error(S, "unknown operand");
1137  }
1138 
1139  // Push the parsed operand into the list of operands
1140  Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1141  Operands.push_back(Op);
1142 
1143  // Check whether this is a TLS call expression
1144  bool TLSCall = false;
1145  if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1146  TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1147 
1148  if (TLSCall && getLexer().is(AsmToken::LParen)) {
1149  const MCExpr *TLSSym;
1150 
1151  Parser.Lex(); // Eat the '('.
1152  S = Parser.getTok().getLoc();
1153  if (ParseExpression(TLSSym))
1154  return Error(S, "invalid TLS call expression");
1155  if (getLexer().isNot(AsmToken::RParen))
1156  return Error(Parser.getTok().getLoc(), "missing ')'");
1157  E = Parser.getTok().getLoc();
1158  Parser.Lex(); // Eat the ')'.
1159 
1160  Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1161  Operands.push_back(Op);
1162  }
1163 
1164  // Otherwise, check for D-form memory operands
1165  if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1166  Parser.Lex(); // Eat the '('.
1167  S = Parser.getTok().getLoc();
1168 
1169  int64_t IntVal;
1170  switch (getLexer().getKind()) {
1171  case AsmToken::Percent:
1172  Parser.Lex(); // Eat the '%'.
1173  unsigned RegNo;
1174  if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1175  return Error(S, "invalid register name");
1176  Parser.Lex(); // Eat the identifier token.
1177  break;
1178 
1179  case AsmToken::Integer:
1180  if (getParser().parseAbsoluteExpression(IntVal) ||
1181  IntVal < 0 || IntVal > 31)
1182  return Error(S, "invalid register number");
1183  break;
1184 
1185  default:
1186  return Error(S, "invalid memory operand");
1187  }
1188 
1189  if (getLexer().isNot(AsmToken::RParen))
1190  return Error(Parser.getTok().getLoc(), "missing ')'");
1191  E = Parser.getTok().getLoc();
1192  Parser.Lex(); // Eat the ')'.
1193 
1194  Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1195  Operands.push_back(Op);
1196  }
1197 
1198  return false;
1199 }
1200 
1201 /// Parse an instruction mnemonic followed by its operands.
1202 bool PPCAsmParser::
1203 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1204  SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1205  // The first operand is the token for the instruction name.
1206  // If the next character is a '+' or '-', we need to add it to the
1207  // instruction name, to match what TableGen is doing.
1208  std::string NewOpcode;
1209  if (getLexer().is(AsmToken::Plus)) {
1210  getLexer().Lex();
1211  NewOpcode = Name;
1212  NewOpcode += '+';
1213  Name = NewOpcode;
1214  }
1215  if (getLexer().is(AsmToken::Minus)) {
1216  getLexer().Lex();
1217  NewOpcode = Name;
1218  NewOpcode += '-';
1219  Name = NewOpcode;
1220  }
1221  // If the instruction ends in a '.', we need to create a separate
1222  // token for it, to match what TableGen is doing.
1223  size_t Dot = Name.find('.');
1224  StringRef Mnemonic = Name.slice(0, Dot);
1225  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1226  Operands.push_back(
1227  PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1228  else
1229  Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1230  if (Dot != StringRef::npos) {
1231  SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1232  StringRef DotStr = Name.slice(Dot, StringRef::npos);
1233  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1234  Operands.push_back(
1235  PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1236  else
1237  Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1238  }
1239 
1240  // If there are no more operands then finish
1241  if (getLexer().is(AsmToken::EndOfStatement))
1242  return false;
1243 
1244  // Parse the first operand
1245  if (ParseOperand(Operands))
1246  return true;
1247 
1248  while (getLexer().isNot(AsmToken::EndOfStatement) &&
1249  getLexer().is(AsmToken::Comma)) {
1250  // Consume the comma token
1251  getLexer().Lex();
1252 
1253  // Parse the next operand
1254  if (ParseOperand(Operands))
1255  return true;
1256  }
1257 
1258  return false;
1259 }
1260 
1261 /// ParseDirective parses the PPC specific directives
1262 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1263  StringRef IDVal = DirectiveID.getIdentifier();
1264  if (IDVal == ".word")
1265  return ParseDirectiveWord(2, DirectiveID.getLoc());
1266  if (IDVal == ".llong")
1267  return ParseDirectiveWord(8, DirectiveID.getLoc());
1268  if (IDVal == ".tc")
1269  return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1270  if (IDVal == ".machine")
1271  return ParseDirectiveMachine(DirectiveID.getLoc());
1272  return true;
1273 }
1274 
1275 /// ParseDirectiveWord
1276 /// ::= .word [ expression (, expression)* ]
1277 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1278  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1279  for (;;) {
1280  const MCExpr *Value;
1281  if (getParser().parseExpression(Value))
1282  return true;
1283 
1284  getParser().getStreamer().EmitValue(Value, Size);
1285 
1286  if (getLexer().is(AsmToken::EndOfStatement))
1287  break;
1288 
1289  if (getLexer().isNot(AsmToken::Comma))
1290  return Error(L, "unexpected token in directive");
1291  Parser.Lex();
1292  }
1293  }
1294 
1295  Parser.Lex();
1296  return false;
1297 }
1298 
1299 /// ParseDirectiveTC
1300 /// ::= .tc [ symbol (, expression)* ]
1301 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1302  // Skip TC symbol, which is only used with XCOFF.
1303  while (getLexer().isNot(AsmToken::EndOfStatement)
1304  && getLexer().isNot(AsmToken::Comma))
1305  Parser.Lex();
1306  if (getLexer().isNot(AsmToken::Comma))
1307  return Error(L, "unexpected token in directive");
1308  Parser.Lex();
1309 
1310  // Align to word size.
1311  getParser().getStreamer().EmitValueToAlignment(Size);
1312 
1313  // Emit expressions.
1314  return ParseDirectiveWord(Size, L);
1315 }
1316 
1317 /// ParseDirectiveMachine
1318 /// ::= .machine [ cpu | "push" | "pop" ]
1319 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1320  if (getLexer().isNot(AsmToken::Identifier) &&
1321  getLexer().isNot(AsmToken::String))
1322  return Error(L, "unexpected token in directive");
1323 
1324  StringRef CPU = Parser.getTok().getIdentifier();
1325  Parser.Lex();
1326 
1327  // FIXME: Right now, the parser always allows any available
1328  // instruction, so the .machine directive is not useful.
1329  // Implement ".machine any" (by doing nothing) for the benefit
1330  // of existing assembler code. Likewise, we can then implement
1331  // ".machine push" and ".machine pop" as no-op.
1332  if (CPU != "any" && CPU != "push" && CPU != "pop")
1333  return Error(L, "unrecognized machine type");
1334 
1335  if (getLexer().isNot(AsmToken::EndOfStatement))
1336  return Error(L, "unexpected token in directive");
1337 
1338  return false;
1339 }
1340 
1341 /// Force static initialization.
1342 extern "C" void LLVMInitializePowerPCAsmParser() {
1343  RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1344  RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1345  RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1346 }
1347 
1348 #define GET_REGISTER_MATCHER
1349 #define GET_MATCHER_IMPLEMENTATION
1350 #include "PPCGenAsmMatcher.inc"
1351 
1352 // Define this matcher function after the auto-generated include so we
1353 // have the match class enum definitions.
1354 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1355  unsigned Kind) {
1356  // If the kind is a token for a literal immediate, check if our asm
1357  // operand matches. This is for InstAliases which have a fixed-value
1358  // immediate in the syntax.
1359  int64_t ImmVal;
1360  switch (Kind) {
1361  case MCK_0: ImmVal = 0; break;
1362  case MCK_1: ImmVal = 1; break;
1363  case MCK_2: ImmVal = 2; break;
1364  case MCK_3: ImmVal = 3; break;
1365  default: return Match_InvalidOperand;
1366  }
1367 
1368  PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1369  if (Op->isImm() && Op->getImm() == ImmVal)
1370  return Match_Success;
1371 
1372  return Match_InvalidOperand;
1373 }
1374 
1375 const MCExpr *
1376 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1377  MCSymbolRefExpr::VariantKind Variant,
1378  MCContext &Ctx) {
1379  switch (Variant) {
1380  case MCSymbolRefExpr::VK_PPC_LO:
1381  return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1382  case MCSymbolRefExpr::VK_PPC_HI:
1383  return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1384  case MCSymbolRefExpr::VK_PPC_HA:
1385  return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1386  case MCSymbolRefExpr::VK_PPC_HIGHER:
1387  return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1388  case MCSymbolRefExpr::VK_PPC_HIGHERA:
1389  return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1390  case MCSymbolRefExpr::VK_PPC_HIGHEST:
1391  return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1392  case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1393  return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1394  default:
1395  return 0;
1396  }
1397 }
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:30
llvm::isUInt< 8 >
bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:294
llvm::ARM_PROC::A
Definition: ARMBaseInfo.h:98
R4
#define R4(n)
llvm::MCSymbolRefExpr::getSymbol
const MCSymbol & getSymbol() const
Definition: MCExpr.h:283
llvm::SMLoc::getPointer
const char * getPointer() const
Definition: SMLoc.h:33
llvm::StringRef::size
size_t size() const
size - Get the string size.
Definition: StringRef.h:113
MatchRegisterName
static unsigned MatchRegisterName(StringRef Name)
llvm::MCOperand::CreateReg
static MCOperand CreateReg(unsigned Reg)
Definition: MCInst.h:111
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MCTargetAsmParser - Generic interface to target specific assembly parsers.
Definition: MCTargetAsmParser.h:74
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size_t find(char C, size_t From=0) const
Definition: StringRef.h:233
llvm::MCBinaryExpr::Mul
Multiplication.
Definition: MCExpr.h:374
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:61
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static MCOperand CreateExpr(const MCExpr *Val)
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virtual void EmitInstruction(const MCInst &Inst)=0
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#define R2(n)
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std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
Definition: StringExtras.cpp:38
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#define llvm_unreachable(msg)
Definition: ErrorHandling.h:103
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AsmToken - Target independent representation for an assembler token.
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const char * data() const
Definition: StringRef.h:107
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Definition: MCExpr.h:303
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Unary expressions.
Definition: MCExpr.h:37
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static const MCSymbolRefExpr * Create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:270
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const MCExpr * getLHS() const
getLHS - Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:477
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static const PPCMCExpr * Create(VariantKind Kind, const MCExpr *Expr, bool isDarwin, MCContext &Ctx)
Definition: PPCMCExpr.cpp:19
llvm::MCBinaryExpr::Create
static const MCBinaryExpr * Create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.cpp:142
MII
const MCInstrInfo & MII
Definition: MCModuleYAML.cpp:55
llvm::AsmToken::getLoc
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
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static const MCUnaryExpr * Create(Opcode Op, const MCExpr *Expr, MCContext &Ctx)
Definition: MCExpr.cpp:147
LLVMInitializePowerPCAsmParser
void LLVMInitializePowerPCAsmParser()
Force static initialization.
Definition: PPCAsmParser.cpp:1342
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enable_if_c< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Definition: StringRef.h:337
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MCBinaryExpr - Binary assembler expressions.
Definition: MCExpr.h:356
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void setLoc(SMLoc loc)
Definition: MCInst.h:160
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Definition: MCInst.h:157
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#define R6(n)
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Target ThePPC32Target
Definition: PowerPCTargetInfo.cpp:15
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Target ThePPC64LETarget
Definition: PowerPCTargetInfo.cpp:15
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bool is(TokenKind K) const
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unsigned getOpcode() const
Definition: MCInst.h:158
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int64_t getImm() const
Definition: MCInst.h:74
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static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:35
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const MCExpr * getRHS() const
getRHS - Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:480
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StringRef getIdentifier() const
Definition: MCAsmLexer.h:84
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const MCExpr * getSubExpr() const
getSubExpr - Get the child of this unary expression.
Definition: MCExpr.h:346
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StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:70
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static const size_t npos
Definition: StringRef.h:45
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bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:135
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static MCOperand CreateImm(int64_t Val)
Definition: MCInst.h:117
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#define N
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Opcode getOpcode() const
getOpcode - Get the kind of this binary expression.
Definition: MCExpr.h:474
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static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: AArch64Disassembler.cpp:295
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References to labels and assigned expressions.
Definition: MCExpr.h:36
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static bool isMem(const MachineInstr *MI, unsigned Op)
Definition: X86InstrInfo.h:123
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Definition: MathExtras.h:272
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VariantKind getKind() const
Definition: MCExpr.h:285
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LLVM Value Representation.
Definition: Value.h:66
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SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:30
llvm::MCExpr::Constant
Constant expressions.
Definition: MCExpr.h:35
llvm::MCExpr::Binary
Binary expressions.
Definition: MCExpr.h:34
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bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:298
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Target ThePPC64Target
Definition: PowerPCTargetInfo.cpp:15
llvm::raw_ostream
Definition: raw_ostream.h:31
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bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:354
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void addOperand(const MCOperand &Op)
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Target specific expression.
Definition: MCExpr.h:38
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StringRef slice(size_t Start, size_t End) const
Definition: StringRef.h:421
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
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bool startswith_lower(StringRef Prefix) const
Check if this string starts with the given Prefix, ignoring case.
Definition: StringRef.cpp:62
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const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:163
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Opcode getOpcode() const
getOpcode - Get the kind of this unary expression.
Definition: MCExpr.h:343

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