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LegalizeIntegerTypes.cpp
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1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
17 // targets).
18 //
19 //===----------------------------------------------------------------------===//
20 
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
25 using namespace llvm;
26 
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
30 
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36  DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37  SDValue Res = SDValue();
38 
39  // See if the target wants to custom expand this node.
40  if (CustomLowerNode(N, N->getValueType(ResNo), true))
41  return;
42 
43  switch (N->getOpcode()) {
44  default:
45 #ifndef NDEBUG
46  dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47  N->dump(&DAG); dbgs() << "\n";
48 #endif
49  llvm_unreachable("Do not know how to promote this operator!");
50  case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
51  case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
52  case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
53  case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
54  case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
55  case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
56  case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
58  Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
60  case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
61  case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
63  case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
65  Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
66  case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
67  case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
68  case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
69  case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
70  case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
71  case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
73  Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
74  case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
75  case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
76  case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
77  case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
78  case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
79 
81  Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
83  Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
85  Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
86  case ISD::BUILD_VECTOR:
87  Res = PromoteIntRes_BUILD_VECTOR(N); break;
89  Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
91  Res = PromoteIntRes_CONCAT_VECTORS(N); break;
92 
93  case ISD::SIGN_EXTEND:
94  case ISD::ZERO_EXTEND:
95  case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
96 
97  case ISD::FP_TO_SINT:
98  case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
99 
100  case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
101 
102  case ISD::AND:
103  case ISD::OR:
104  case ISD::XOR:
105  case ISD::ADD:
106  case ISD::SUB:
107  case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
108 
109  case ISD::SDIV:
110  case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
111 
112  case ISD::UDIV:
113  case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
114 
115  case ISD::SADDO:
116  case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
117  case ISD::UADDO:
118  case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
119  case ISD::SMULO:
120  case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
121 
122  case ISD::ATOMIC_LOAD:
123  Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
124 
128  case ISD::ATOMIC_LOAD_OR:
135  case ISD::ATOMIC_SWAP:
136  Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
137 
139  Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
140  }
141 
142  // If the result is null then the sub-method took care of registering it.
143  if (Res.getNode())
144  SetPromotedInteger(SDValue(N, ResNo), Res);
145 }
146 
147 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
148  unsigned ResNo) {
149  SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
150  return GetPromotedInteger(Op);
151 }
152 
153 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
154  // Sign-extend the new bits, and continue the assertion.
155  SDValue Op = SExtPromotedInteger(N->getOperand(0));
156  return DAG.getNode(ISD::AssertSext, SDLoc(N),
157  Op.getValueType(), Op, N->getOperand(1));
158 }
159 
160 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
161  // Zero the new bits, and continue the assertion.
162  SDValue Op = ZExtPromotedInteger(N->getOperand(0));
163  return DAG.getNode(ISD::AssertZext, SDLoc(N),
164  Op.getValueType(), Op, N->getOperand(1));
165 }
166 
167 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
168  EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
169  SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
170  N->getMemoryVT(), ResVT,
171  N->getChain(), N->getBasePtr(),
172  N->getMemOperand(), N->getOrdering(),
173  N->getSynchScope());
174  // Legalized the chain result - switch anything that used the old chain to
175  // use the new one.
176  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
177  return Res;
178 }
179 
180 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
181  SDValue Op2 = GetPromotedInteger(N->getOperand(2));
182  SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
183  N->getMemoryVT(),
184  N->getChain(), N->getBasePtr(),
185  Op2, N->getMemOperand(), N->getOrdering(),
186  N->getSynchScope());
187  // Legalized the chain result - switch anything that used the old chain to
188  // use the new one.
189  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
190  return Res;
191 }
192 
193 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
194  SDValue Op2 = GetPromotedInteger(N->getOperand(2));
195  SDValue Op3 = GetPromotedInteger(N->getOperand(3));
196  SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
197  N->getMemoryVT(), N->getChain(), N->getBasePtr(),
198  Op2, Op3, N->getMemOperand(), N->getOrdering(),
199  N->getSynchScope());
200  // Legalized the chain result - switch anything that used the old chain to
201  // use the new one.
202  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
203  return Res;
204 }
205 
206 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
207  SDValue InOp = N->getOperand(0);
208  EVT InVT = InOp.getValueType();
209  EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
210  EVT OutVT = N->getValueType(0);
211  EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
212  SDLoc dl(N);
213 
214  switch (getTypeAction(InVT)) {
216  break;
218  if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
219  // The input promotes to the same size. Convert the promoted value.
220  return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
221  break;
223  // Promote the integer operand by hand.
224  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
227  break;
229  // Convert the element to an integer and promote it by hand.
230  if (!NOutVT.isVector())
231  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
232  BitConvertToInteger(GetScalarizedVector(InOp)));
233  break;
235  // For example, i32 = BITCAST v2i16 on alpha. Convert the split
236  // pieces of the input into integers and reassemble in the final type.
237  SDValue Lo, Hi;
238  GetSplitVector(N->getOperand(0), Lo, Hi);
239  Lo = BitConvertToInteger(Lo);
240  Hi = BitConvertToInteger(Hi);
241 
242  if (TLI.isBigEndian())
243  std::swap(Lo, Hi);
244 
245  InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
247  NOutVT.getSizeInBits()),
248  JoinIntegers(Lo, Hi));
249  return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
250  }
252  // The input is widened to the same size. Convert to the widened value.
253  // Make sure that the outgoing value is not a vector, because this would
254  // make us bitcast between two vectors which are legalized in different ways.
255  if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
256  return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
257  }
258 
259  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
260  CreateStackStoreLoad(InOp, OutVT));
261 }
262 
263 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
264  SDValue Op = GetPromotedInteger(N->getOperand(0));
265  EVT OVT = N->getValueType(0);
266  EVT NVT = Op.getValueType();
267  SDLoc dl(N);
268 
269  unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
270  return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
271  DAG.getConstant(DiffBits, TLI.getPointerTy()));
272 }
273 
274 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
275  // The pair element type may be legal, or may not promote to the same type as
276  // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
277  return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
278  TLI.getTypeToTransformTo(*DAG.getContext(),
279  N->getValueType(0)), JoinIntegers(N->getOperand(0),
280  N->getOperand(1)));
281 }
282 
283 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
284  EVT VT = N->getValueType(0);
285  // FIXME there is no actual debug info here
286  SDLoc dl(N);
287  // Zero extend things like i1, sign extend everything else. It shouldn't
288  // matter in theory which one we pick, but this tends to give better code?
289  unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
290  SDValue Result = DAG.getNode(Opc, dl,
291  TLI.getTypeToTransformTo(*DAG.getContext(), VT),
292  SDValue(N, 0));
293  assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
294  return Result;
295 }
296 
297 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
298  ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
299  assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
300  CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
301  CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
302  "can only promote integers");
303  EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
304  return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
305  N->getOperand(1), N->getOperand(2),
306  N->getOperand(3), N->getOperand(4), CvtCode);
307 }
308 
309 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
310  // Zero extend to the promoted type and do the count there.
311  SDValue Op = ZExtPromotedInteger(N->getOperand(0));
312  SDLoc dl(N);
313  EVT OVT = N->getValueType(0);
314  EVT NVT = Op.getValueType();
315  Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
316  // Subtract off the extra leading bits in the bigger type.
317  return DAG.getNode(ISD::SUB, dl, NVT, Op,
318  DAG.getConstant(NVT.getSizeInBits() -
319  OVT.getSizeInBits(), NVT));
320 }
321 
322 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
323  // Zero extend to the promoted type and do the count there.
324  SDValue Op = ZExtPromotedInteger(N->getOperand(0));
325  return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
326 }
327 
328 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
329  SDValue Op = GetPromotedInteger(N->getOperand(0));
330  EVT OVT = N->getValueType(0);
331  EVT NVT = Op.getValueType();
332  SDLoc dl(N);
333  if (N->getOpcode() == ISD::CTTZ) {
334  // The count is the same in the promoted type except if the original
335  // value was zero. This can be handled by setting the bit just off
336  // the top of the original type.
337  APInt TopBit(NVT.getSizeInBits(), 0);
338  TopBit.setBit(OVT.getSizeInBits());
339  Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
340  }
341  return DAG.getNode(N->getOpcode(), dl, NVT, Op);
342 }
343 
344 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
345  SDLoc dl(N);
346  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
347  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
348  N->getOperand(1));
349 }
350 
351 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
352  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
353  unsigned NewOpc = N->getOpcode();
354  SDLoc dl(N);
355 
356  // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
357  // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
358  // and SINT conversions are Custom, there is no way to tell which is
359  // preferable. We choose SINT because that's the right thing on PPC.)
360  if (N->getOpcode() == ISD::FP_TO_UINT &&
361  !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
363  NewOpc = ISD::FP_TO_SINT;
364 
365  SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
366 
367  // Assert that the converted value fits in the original type. If it doesn't
368  // (eg: because the value being converted is too big), then the result of the
369  // original operation was undefined anyway, so the assert is still correct.
370  return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
371  ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
373 }
374 
375 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
376  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
377  SDLoc dl(N);
378 
379  SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
380 
381  return DAG.getNode(ISD::AssertZext, dl,
382  NVT, Res, DAG.getValueType(N->getValueType(0)));
383 }
384 
385 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
386  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
387  SDLoc dl(N);
388 
389  if (getTypeAction(N->getOperand(0).getValueType())
391  SDValue Res = GetPromotedInteger(N->getOperand(0));
392  assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
393 
394  // If the result and operand types are the same after promotion, simplify
395  // to an in-register extension.
396  if (NVT == Res.getValueType()) {
397  // The high bits are not guaranteed to be anything. Insert an extend.
398  if (N->getOpcode() == ISD::SIGN_EXTEND)
399  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
400  DAG.getValueType(N->getOperand(0).getValueType()));
401  if (N->getOpcode() == ISD::ZERO_EXTEND)
402  return DAG.getZeroExtendInReg(Res, dl,
404  assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
405  return Res;
406  }
407  }
408 
409  // Otherwise, just extend the original operand all the way to the larger type.
410  return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
411 }
412 
413 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
414  assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
415  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
416  ISD::LoadExtType ExtType =
418  SDLoc dl(N);
419  SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
420  N->getMemoryVT(), N->getMemOperand());
421 
422  // Legalized the chain result - switch anything that used the old chain to
423  // use the new one.
424  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
425  return Res;
426 }
427 
428 /// Promote the overflow flag of an overflowing arithmetic node.
429 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
430  // Simply change the return type of the boolean result.
431  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
432  EVT ValueVTs[] = { N->getValueType(0), NVT };
433  SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
434  SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
435  DAG.getVTList(ValueVTs, 2), Ops, 2);
436 
437  // Modified the sum result - switch anything that used the old sum to use
438  // the new one.
439  ReplaceValueWith(SDValue(N, 0), Res);
440 
441  return SDValue(Res.getNode(), 1);
442 }
443 
444 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
445  if (ResNo == 1)
446  return PromoteIntRes_Overflow(N);
447 
448  // The operation overflowed iff the result in the larger type is not the
449  // sign extension of its truncation to the original type.
450  SDValue LHS = SExtPromotedInteger(N->getOperand(0));
451  SDValue RHS = SExtPromotedInteger(N->getOperand(1));
452  EVT OVT = N->getOperand(0).getValueType();
453  EVT NVT = LHS.getValueType();
454  SDLoc dl(N);
455 
456  // Do the arithmetic in the larger type.
457  unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
458  SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
459 
460  // Calculate the overflow flag: sign extend the arithmetic result from
461  // the original type.
462  SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
463  DAG.getValueType(OVT));
464  // Overflowed if and only if this is not equal to Res.
465  Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
466 
467  // Use the calculated overflow everywhere.
468  ReplaceValueWith(SDValue(N, 1), Ofl);
469 
470  return Res;
471 }
472 
473 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
474  // Sign extend the input.
475  SDValue LHS = SExtPromotedInteger(N->getOperand(0));
476  SDValue RHS = SExtPromotedInteger(N->getOperand(1));
477  return DAG.getNode(N->getOpcode(), SDLoc(N),
478  LHS.getValueType(), LHS, RHS);
479 }
480 
481 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
482  SDValue LHS = GetPromotedInteger(N->getOperand(1));
483  SDValue RHS = GetPromotedInteger(N->getOperand(2));
484  return DAG.getSelect(SDLoc(N),
485  LHS.getValueType(), N->getOperand(0), LHS, RHS);
486 }
487 
488 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
489  SDValue Mask = N->getOperand(0);
490  EVT OpTy = N->getOperand(1).getValueType();
491 
492  // Promote all the way up to the canonical SetCC type.
493  Mask = PromoteTargetBoolean(Mask, getSetCCResultType(OpTy));
494  SDValue LHS = GetPromotedInteger(N->getOperand(1));
495  SDValue RHS = GetPromotedInteger(N->getOperand(2));
496  return DAG.getNode(ISD::VSELECT, SDLoc(N),
497  LHS.getValueType(), Mask, LHS, RHS);
498 }
499 
500 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
501  SDValue LHS = GetPromotedInteger(N->getOperand(2));
502  SDValue RHS = GetPromotedInteger(N->getOperand(3));
503  return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
504  LHS.getValueType(), N->getOperand(0),
505  N->getOperand(1), LHS, RHS, N->getOperand(4));
506 }
507 
508 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
509  EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
510 
511  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
512 
513  // Only use the result of getSetCCResultType if it is legal,
514  // otherwise just use the promoted result type (NVT).
515  if (!TLI.isTypeLegal(SVT))
516  SVT = NVT;
517 
518  SDLoc dl(N);
519  assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
520  "Vector compare must return a vector result!");
521 
522  SDValue LHS = N->getOperand(0);
523  SDValue RHS = N->getOperand(1);
524  if (LHS.getValueType() != RHS.getValueType()) {
525  if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
526  !LHS.getValueType().isVector())
527  LHS = GetPromotedInteger(LHS);
528  if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
529  !RHS.getValueType().isVector())
530  RHS = GetPromotedInteger(RHS);
531  }
532 
533  // Get the SETCC result using the canonical SETCC type.
534  SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
535  N->getOperand(2));
536 
537  assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
538  // Convert to the expected type.
539  return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
540 }
541 
542 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
543  SDValue Res = GetPromotedInteger(N->getOperand(0));
544  SDValue Amt = N->getOperand(1);
545  Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
546  return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
547 }
548 
549 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
550  SDValue Op = GetPromotedInteger(N->getOperand(0));
551  return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
552  Op.getValueType(), Op, N->getOperand(1));
553 }
554 
555 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
556  // The input may have strange things in the top bits of the registers, but
557  // these operations don't care. They may have weird bits going out, but
558  // that too is okay if they are integer operations.
559  SDValue LHS = GetPromotedInteger(N->getOperand(0));
560  SDValue RHS = GetPromotedInteger(N->getOperand(1));
561  return DAG.getNode(N->getOpcode(), SDLoc(N),
562  LHS.getValueType(), LHS, RHS);
563 }
564 
565 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
566  // The input value must be properly sign extended.
567  SDValue Res = SExtPromotedInteger(N->getOperand(0));
568  SDValue Amt = N->getOperand(1);
569  Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
570  return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
571 }
572 
573 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
574  // The input value must be properly zero extended.
575  SDValue Res = ZExtPromotedInteger(N->getOperand(0));
576  SDValue Amt = N->getOperand(1);
577  Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
578  return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
579 }
580 
581 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
582  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
583  SDValue Res;
584  SDValue InOp = N->getOperand(0);
585  SDLoc dl(N);
586 
587  switch (getTypeAction(InOp.getValueType())) {
588  default: llvm_unreachable("Unknown type action!");
591  Res = InOp;
592  break;
594  Res = GetPromotedInteger(InOp);
595  break;
597  EVT InVT = InOp.getValueType();
598  assert(InVT.isVector() && "Cannot split scalar types");
599  unsigned NumElts = InVT.getVectorNumElements();
600  assert(NumElts == NVT.getVectorNumElements() &&
601  "Dst and Src must have the same number of elements");
602  assert(isPowerOf2_32(NumElts) &&
603  "Promoted vector type must be a power of two");
604 
605  SDValue EOp1, EOp2;
606  GetSplitVector(InOp, EOp1, EOp2);
607 
608  EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
609  NumElts/2);
610  EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
611  EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
612 
613  return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
614  }
615 
616  // Truncate to NVT instead of VT
617  return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
618 }
619 
620 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
621  if (ResNo == 1)
622  return PromoteIntRes_Overflow(N);
623 
624  // The operation overflowed iff the result in the larger type is not the
625  // zero extension of its truncation to the original type.
626  SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
627  SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
628  EVT OVT = N->getOperand(0).getValueType();
629  EVT NVT = LHS.getValueType();
630  SDLoc dl(N);
631 
632  // Do the arithmetic in the larger type.
633  unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
634  SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
635 
636  // Calculate the overflow flag: zero extend the arithmetic result from
637  // the original type.
638  SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
639  // Overflowed if and only if this is not equal to Res.
640  Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
641 
642  // Use the calculated overflow everywhere.
643  ReplaceValueWith(SDValue(N, 1), Ofl);
644 
645  return Res;
646 }
647 
648 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
649  // Promote the overflow bit trivially.
650  if (ResNo == 1)
651  return PromoteIntRes_Overflow(N);
652 
653  SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
654  SDLoc DL(N);
655  EVT SmallVT = LHS.getValueType();
656 
657  // To determine if the result overflowed in a larger type, we extend the
658  // input to the larger type, do the multiply (checking if it overflows),
659  // then also check the high bits of the result to see if overflow happened
660  // there.
661  if (N->getOpcode() == ISD::SMULO) {
662  LHS = SExtPromotedInteger(LHS);
663  RHS = SExtPromotedInteger(RHS);
664  } else {
665  LHS = ZExtPromotedInteger(LHS);
666  RHS = ZExtPromotedInteger(RHS);
667  }
668  SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
669  SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
670 
671  // Overflow occurred if it occurred in the larger type, or if the high part
672  // of the result does not zero/sign-extend the low part. Check this second
673  // possibility first.
674  SDValue Overflow;
675  if (N->getOpcode() == ISD::UMULO) {
676  // Unsigned overflow occurred if the high part is non-zero.
677  SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
678  DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
679  Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
680  DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
681  } else {
682  // Signed overflow occurred if the high part does not sign extend the low.
683  SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
684  Mul, DAG.getValueType(SmallVT));
685  Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
686  }
687 
688  // The only other way for overflow to occur is if the multiplication in the
689  // larger type itself overflowed.
690  Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
691  SDValue(Mul.getNode(), 1));
692 
693  // Use the calculated overflow everywhere.
694  ReplaceValueWith(SDValue(N, 1), Overflow);
695  return Mul;
696 }
697 
698 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
699  // Zero extend the input.
700  SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
701  SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
702  return DAG.getNode(N->getOpcode(), SDLoc(N),
703  LHS.getValueType(), LHS, RHS);
704 }
705 
706 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
707  return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
708  N->getValueType(0)));
709 }
710 
711 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
712  SDValue Chain = N->getOperand(0); // Get the chain.
713  SDValue Ptr = N->getOperand(1); // Get the pointer.
714  EVT VT = N->getValueType(0);
715  SDLoc dl(N);
716 
717  MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
718  unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
719  // The argument is passed as NumRegs registers of type RegVT.
720 
721  SmallVector<SDValue, 8> Parts(NumRegs);
722  for (unsigned i = 0; i < NumRegs; ++i) {
723  Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
724  N->getConstantOperandVal(3));
725  Chain = Parts[i].getValue(1);
726  }
727 
728  // Handle endianness of the load.
729  if (TLI.isBigEndian())
730  std::reverse(Parts.begin(), Parts.end());
731 
732  // Assemble the parts in the promoted type.
733  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
734  SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
735  for (unsigned i = 1; i < NumRegs; ++i) {
736  SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
737  // Shift it to the right position and "or" it in.
738  Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
739  DAG.getConstant(i * RegVT.getSizeInBits(),
740  TLI.getPointerTy()));
741  Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
742  }
743 
744  // Modified the chain result - switch anything that used the old chain to
745  // use the new one.
746  ReplaceValueWith(SDValue(N, 1), Chain);
747 
748  return Res;
749 }
750 
751 //===----------------------------------------------------------------------===//
752 // Integer Operand Promotion
753 //===----------------------------------------------------------------------===//
754 
755 /// PromoteIntegerOperand - This method is called when the specified operand of
756 /// the specified node is found to need promotion. At this point, all of the
757 /// result types of the node are known to be legal, but other operands of the
758 /// node may need promotion or expansion as well as the specified one.
759 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
760  DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
761  SDValue Res = SDValue();
762 
763  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
764  return false;
765 
766  switch (N->getOpcode()) {
767  default:
768  #ifndef NDEBUG
769  dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
770  N->dump(&DAG); dbgs() << "\n";
771  #endif
772  llvm_unreachable("Do not know how to promote this operator's operand!");
773 
774  case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
775  case ISD::ATOMIC_STORE:
776  Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
777  break;
778  case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
779  case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
780  case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
781  case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
782  case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
783  case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
784  case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
785  case ISD::CONVERT_RNDSAT:
786  Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
788  Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
790  Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
791  case ISD::VSELECT:
792  case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
793  case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
794  case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
795  case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
796  case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
797  case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
798  OpNo); break;
799  case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
800  case ISD::FP16_TO_FP32:
801  case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
802  case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
803 
804  case ISD::SHL:
805  case ISD::SRA:
806  case ISD::SRL:
807  case ISD::ROTL:
808  case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
809  }
810 
811  // If the result is null, the sub-method took care of registering results etc.
812  if (!Res.getNode()) return false;
813 
814  // If the result is N, the sub-method updated N in place. Tell the legalizer
815  // core about this.
816  if (Res.getNode() == N)
817  return true;
818 
819  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
820  "Invalid operand expansion");
821 
822  ReplaceValueWith(SDValue(N, 0), Res);
823  return false;
824 }
825 
826 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
827 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
828 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
829  ISD::CondCode CCCode) {
830  // We have to insert explicit sign or zero extends. Note that we could
831  // insert sign extends for ALL conditions, but zero extend is cheaper on
832  // many machines (an AND instead of two shifts), so prefer it.
833  switch (CCCode) {
834  default: llvm_unreachable("Unknown integer comparison!");
835  case ISD::SETEQ:
836  case ISD::SETNE:
837  case ISD::SETUGE:
838  case ISD::SETUGT:
839  case ISD::SETULE:
840  case ISD::SETULT:
841  // ALL of these operations will work if we either sign or zero extend
842  // the operands (including the unsigned comparisons!). Zero extend is
843  // usually a simpler/cheaper operation, so prefer it.
844  NewLHS = ZExtPromotedInteger(NewLHS);
845  NewRHS = ZExtPromotedInteger(NewRHS);
846  break;
847  case ISD::SETGE:
848  case ISD::SETGT:
849  case ISD::SETLT:
850  case ISD::SETLE:
851  NewLHS = SExtPromotedInteger(NewLHS);
852  NewRHS = SExtPromotedInteger(NewRHS);
853  break;
854  }
855 }
856 
857 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
858  SDValue Op = GetPromotedInteger(N->getOperand(0));
859  return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
860 }
861 
862 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
863  SDValue Op2 = GetPromotedInteger(N->getOperand(2));
864  return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
865  N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
866  N->getOrdering(), N->getSynchScope());
867 }
868 
869 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
870  // This should only occur in unusual situations like bitcasting to an
871  // x86_fp80, so just turn it into a store+load
872  return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
873 }
874 
875 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
876  assert(OpNo == 2 && "Don't know how to promote this operand!");
877 
878  SDValue LHS = N->getOperand(2);
879  SDValue RHS = N->getOperand(3);
880  PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
881 
882  // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
883  // legal types.
884  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
885  N->getOperand(1), LHS, RHS, N->getOperand(4)),
886  0);
887 }
888 
889 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
890  assert(OpNo == 1 && "only know how to promote condition");
891 
892  // Promote all the way up to the canonical SetCC type.
893  EVT SVT = getSetCCResultType(MVT::Other);
894  SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
895 
896  // The chain (Op#0) and basic block destination (Op#2) are always legal types.
897  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
898  N->getOperand(2)), 0);
899 }
900 
901 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
902  // Since the result type is legal, the operands must promote to it.
903  EVT OVT = N->getOperand(0).getValueType();
904  SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
905  SDValue Hi = GetPromotedInteger(N->getOperand(1));
906  assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
907  SDLoc dl(N);
908 
909  Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
910  DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
911  return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
912 }
913 
914 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
915  // The vector type is legal but the element type is not. This implies
916  // that the vector is a power-of-two in length and that the element
917  // type does not have a strange size (eg: it is not i1).
918  EVT VecVT = N->getValueType(0);
919  unsigned NumElts = VecVT.getVectorNumElements();
920  assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
921  "Legal vector of one illegal element?");
922 
923  // Promote the inserted value. The type does not need to match the
924  // vector element type. Check that any extra bits introduced will be
925  // truncated away.
926  assert(N->getOperand(0).getValueType().getSizeInBits() >=
928  "Type of inserted value narrower than vector element type!");
929 
931  for (unsigned i = 0; i < NumElts; ++i)
932  NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
933 
934  return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
935 }
936 
937 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
938  ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
939  assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
940  CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
941  CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
942  "can only promote integer arguments");
943  SDValue InOp = GetPromotedInteger(N->getOperand(0));
944  return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
945  N->getOperand(1), N->getOperand(2),
946  N->getOperand(3), N->getOperand(4), CvtCode);
947 }
948 
949 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
950  unsigned OpNo) {
951  if (OpNo == 1) {
952  // Promote the inserted value. This is valid because the type does not
953  // have to match the vector element type.
954 
955  // Check that any extra bits introduced will be truncated away.
956  assert(N->getOperand(1).getValueType().getSizeInBits() >=
958  "Type of inserted value narrower than vector element type!");
959  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
960  GetPromotedInteger(N->getOperand(1)),
961  N->getOperand(2)),
962  0);
963  }
964 
965  assert(OpNo == 2 && "Different operand and result vector types?");
966 
967  // Promote the index.
968  SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
969  TLI.getVectorIdxTy());
970  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
971  N->getOperand(1), Idx), 0);
972 }
973 
974 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
975  // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
976  // the operand in place.
977  return SDValue(DAG.UpdateNodeOperands(N,
978  GetPromotedInteger(N->getOperand(0))), 0);
979 }
980 
981 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
982  assert(OpNo == 0 && "Only know how to promote the condition!");
983  SDValue Cond = N->getOperand(0);
984  EVT OpTy = N->getOperand(1).getValueType();
985 
986  // Promote all the way up to the canonical SetCC type.
987  EVT SVT = getSetCCResultType(N->getOpcode() == ISD::SELECT ?
988  OpTy.getScalarType() : OpTy);
989  Cond = PromoteTargetBoolean(Cond, SVT);
990 
991  return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
992  N->getOperand(2)), 0);
993 }
994 
995 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
996  assert(OpNo == 0 && "Don't know how to promote this operand!");
997 
998  SDValue LHS = N->getOperand(0);
999  SDValue RHS = N->getOperand(1);
1000  PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1001 
1002  // The CC (#4) and the possible return values (#2 and #3) have legal types.
1003  return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1004  N->getOperand(3), N->getOperand(4)), 0);
1005 }
1006 
1007 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1008  assert(OpNo == 0 && "Don't know how to promote this operand!");
1009 
1010  SDValue LHS = N->getOperand(0);
1011  SDValue RHS = N->getOperand(1);
1012  PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1013 
1014  // The CC (#2) is always legal.
1015  return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1016 }
1017 
1018 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1019  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1020  ZExtPromotedInteger(N->getOperand(1))), 0);
1021 }
1022 
1023 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1024  SDValue Op = GetPromotedInteger(N->getOperand(0));
1025  SDLoc dl(N);
1026  Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1027  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1028  Op, DAG.getValueType(N->getOperand(0).getValueType()));
1029 }
1030 
1031 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1032  return SDValue(DAG.UpdateNodeOperands(N,
1033  SExtPromotedInteger(N->getOperand(0))), 0);
1034 }
1035 
1036 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1037  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1038  SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1039  SDLoc dl(N);
1040 
1041  SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1042 
1043  // Truncate the value and store the result.
1044  return DAG.getTruncStore(Ch, dl, Val, Ptr,
1045  N->getMemoryVT(), N->getMemOperand());
1046 }
1047 
1048 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1049  SDValue Op = GetPromotedInteger(N->getOperand(0));
1050  return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1051 }
1052 
1053 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1054  return SDValue(DAG.UpdateNodeOperands(N,
1055  ZExtPromotedInteger(N->getOperand(0))), 0);
1056 }
1057 
1058 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1059  SDLoc dl(N);
1060  SDValue Op = GetPromotedInteger(N->getOperand(0));
1061  Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1062  return DAG.getZeroExtendInReg(Op, dl,
1064 }
1065 
1066 
1067 //===----------------------------------------------------------------------===//
1068 // Integer Result Expansion
1069 //===----------------------------------------------------------------------===//
1070 
1071 /// ExpandIntegerResult - This method is called when the specified result of the
1072 /// specified node is found to need expansion. At this point, the node may also
1073 /// have invalid operands or may have other results that need promotion, we just
1074 /// know that (at least) one result needs expansion.
1075 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1076  DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1077  SDValue Lo, Hi;
1078  Lo = Hi = SDValue();
1079 
1080  // See if the target wants to custom expand this node.
1081  if (CustomLowerNode(N, N->getValueType(ResNo), true))
1082  return;
1083 
1084  switch (N->getOpcode()) {
1085  default:
1086 #ifndef NDEBUG
1087  dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1088  N->dump(&DAG); dbgs() << "\n";
1089 #endif
1090  llvm_unreachable("Do not know how to expand the result of this operator!");
1091 
1092  case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1093  case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1094  case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1095  case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1096 
1097  case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1098  case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1099  case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1100  case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1101  case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1102 
1103  case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1104  case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1105  case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1106  case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1107  case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1108  case ISD::CTLZ_ZERO_UNDEF:
1109  case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1110  case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1111  case ISD::CTTZ_ZERO_UNDEF:
1112  case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1113  case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1114  case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1115  case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1116  case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1117  case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1118  case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1119  case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1120  case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1121  case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1122  case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1123  case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1124  case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1125  case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1126 
1127  case ISD::ATOMIC_LOAD_ADD:
1128  case ISD::ATOMIC_LOAD_SUB:
1129  case ISD::ATOMIC_LOAD_AND:
1130  case ISD::ATOMIC_LOAD_OR:
1131  case ISD::ATOMIC_LOAD_XOR:
1132  case ISD::ATOMIC_LOAD_NAND:
1133  case ISD::ATOMIC_LOAD_MIN:
1134  case ISD::ATOMIC_LOAD_MAX:
1135  case ISD::ATOMIC_LOAD_UMIN:
1136  case ISD::ATOMIC_LOAD_UMAX:
1137  case ISD::ATOMIC_SWAP:
1138  case ISD::ATOMIC_CMP_SWAP: {
1139  std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1140  SplitInteger(Tmp.first, Lo, Hi);
1141  ReplaceValueWith(SDValue(N, 1), Tmp.second);
1142  break;
1143  }
1144 
1145  case ISD::AND:
1146  case ISD::OR:
1147  case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1148 
1149  case ISD::ADD:
1150  case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1151 
1152  case ISD::ADDC:
1153  case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1154 
1155  case ISD::ADDE:
1156  case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1157 
1158  case ISD::SHL:
1159  case ISD::SRA:
1160  case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1161 
1162  case ISD::SADDO:
1163  case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1164  case ISD::UADDO:
1165  case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1166  case ISD::UMULO:
1167  case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1168  }
1169 
1170  // If Lo/Hi is null, the sub-method took care of registering results etc.
1171  if (Lo.getNode())
1172  SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1173 }
1174 
1175 /// Lower an atomic node to the appropriate builtin call.
1176 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1177  unsigned Opc = Node->getOpcode();
1178  MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1179  RTLIB::Libcall LC;
1180 
1181  switch (Opc) {
1182  default:
1183  llvm_unreachable("Unhandled atomic intrinsic Expand!");
1184  case ISD::ATOMIC_SWAP:
1185  switch (VT.SimpleTy) {
1186  default: llvm_unreachable("Unexpected value type for atomic!");
1187  case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1188  case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1189  case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1190  case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1192  }
1193  break;
1194  case ISD::ATOMIC_CMP_SWAP:
1195  switch (VT.SimpleTy) {
1196  default: llvm_unreachable("Unexpected value type for atomic!");
1197  case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1198  case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1199  case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1200  case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1202  }
1203  break;
1204  case ISD::ATOMIC_LOAD_ADD:
1205  switch (VT.SimpleTy) {
1206  default: llvm_unreachable("Unexpected value type for atomic!");
1207  case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1208  case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1209  case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1210  case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1211  case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
1212  }
1213  break;
1214  case ISD::ATOMIC_LOAD_SUB:
1215  switch (VT.SimpleTy) {
1216  default: llvm_unreachable("Unexpected value type for atomic!");
1217  case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1218  case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1219  case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1220  case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1221  case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
1222  }
1223  break;
1224  case ISD::ATOMIC_LOAD_AND:
1225  switch (VT.SimpleTy) {
1226  default: llvm_unreachable("Unexpected value type for atomic!");
1227  case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1228  case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1229  case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1230  case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1231  case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
1232  }
1233  break;
1234  case ISD::ATOMIC_LOAD_OR:
1235  switch (VT.SimpleTy) {
1236  default: llvm_unreachable("Unexpected value type for atomic!");
1237  case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1238  case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1239  case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1240  case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1241  case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
1242  }
1243  break;
1244  case ISD::ATOMIC_LOAD_XOR:
1245  switch (VT.SimpleTy) {
1246  default: llvm_unreachable("Unexpected value type for atomic!");
1247  case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1248  case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1249  case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1250  case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1251  case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
1252  }
1253  break;
1254  case ISD::ATOMIC_LOAD_NAND:
1255  switch (VT.SimpleTy) {
1256  default: llvm_unreachable("Unexpected value type for atomic!");
1257  case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1258  case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1259  case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1260  case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1261  case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
1262  }
1263  break;
1264  }
1265 
1266  return ExpandChainLibCall(LC, Node, false);
1267 }
1268 
1269 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1270 /// and the shift amount is a constant 'Amt'. Expand the operation.
1271 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1272  SDValue &Lo, SDValue &Hi) {
1273  SDLoc DL(N);
1274  // Expand the incoming operand to be shifted, so that we have its parts
1275  SDValue InL, InH;
1276  GetExpandedInteger(N->getOperand(0), InL, InH);
1277 
1278  EVT NVT = InL.getValueType();
1279  unsigned VTBits = N->getValueType(0).getSizeInBits();
1280  unsigned NVTBits = NVT.getSizeInBits();
1281  EVT ShTy = N->getOperand(1).getValueType();
1282 
1283  if (N->getOpcode() == ISD::SHL) {
1284  if (Amt > VTBits) {
1285  Lo = Hi = DAG.getConstant(0, NVT);
1286  } else if (Amt > NVTBits) {
1287  Lo = DAG.getConstant(0, NVT);
1288  Hi = DAG.getNode(ISD::SHL, DL,
1289  NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1290  } else if (Amt == NVTBits) {
1291  Lo = DAG.getConstant(0, NVT);
1292  Hi = InL;
1293  } else if (Amt == 1 &&
1295  TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1296  // Emit this X << 1 as X+X.
1297  SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1298  SDValue LoOps[2] = { InL, InL };
1299  Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1300  SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1301  Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1302  } else {
1303  Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1304  Hi = DAG.getNode(ISD::OR, DL, NVT,
1305  DAG.getNode(ISD::SHL, DL, NVT, InH,
1306  DAG.getConstant(Amt, ShTy)),
1307  DAG.getNode(ISD::SRL, DL, NVT, InL,
1308  DAG.getConstant(NVTBits-Amt, ShTy)));
1309  }
1310  return;
1311  }
1312 
1313  if (N->getOpcode() == ISD::SRL) {
1314  if (Amt > VTBits) {
1315  Lo = DAG.getConstant(0, NVT);
1316  Hi = DAG.getConstant(0, NVT);
1317  } else if (Amt > NVTBits) {
1318  Lo = DAG.getNode(ISD::SRL, DL,
1319  NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1320  Hi = DAG.getConstant(0, NVT);
1321  } else if (Amt == NVTBits) {
1322  Lo = InH;
1323  Hi = DAG.getConstant(0, NVT);
1324  } else {
1325  Lo = DAG.getNode(ISD::OR, DL, NVT,
1326  DAG.getNode(ISD::SRL, DL, NVT, InL,
1327  DAG.getConstant(Amt, ShTy)),
1328  DAG.getNode(ISD::SHL, DL, NVT, InH,
1329  DAG.getConstant(NVTBits-Amt, ShTy)));
1330  Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1331  }
1332  return;
1333  }
1334 
1335  assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1336  if (Amt > VTBits) {
1337  Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1338  DAG.getConstant(NVTBits-1, ShTy));
1339  } else if (Amt > NVTBits) {
1340  Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1341  DAG.getConstant(Amt-NVTBits, ShTy));
1342  Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1343  DAG.getConstant(NVTBits-1, ShTy));
1344  } else if (Amt == NVTBits) {
1345  Lo = InH;
1346  Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1347  DAG.getConstant(NVTBits-1, ShTy));
1348  } else {
1349  Lo = DAG.getNode(ISD::OR, DL, NVT,
1350  DAG.getNode(ISD::SRL, DL, NVT, InL,
1351  DAG.getConstant(Amt, ShTy)),
1352  DAG.getNode(ISD::SHL, DL, NVT, InH,
1353  DAG.getConstant(NVTBits-Amt, ShTy)));
1354  Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1355  }
1356 }
1357 
1358 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1359 /// this shift based on knowledge of the high bit of the shift amount. If we
1360 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1361 /// shift amount.
1362 bool DAGTypeLegalizer::
1363 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1364  SDValue Amt = N->getOperand(1);
1365  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1366  EVT ShTy = Amt.getValueType();
1367  unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1368  unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1369  assert(isPowerOf2_32(NVTBits) &&
1370  "Expanded integer type size not a power of two!");
1371  SDLoc dl(N);
1372 
1373  APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1374  APInt KnownZero, KnownOne;
1375  DAG.ComputeMaskedBits(N->getOperand(1), KnownZero, KnownOne);
1376 
1377  // If we don't know anything about the high bits, exit.
1378  if (((KnownZero|KnownOne) & HighBitMask) == 0)
1379  return false;
1380 
1381  // Get the incoming operand to be shifted.
1382  SDValue InL, InH;
1383  GetExpandedInteger(N->getOperand(0), InL, InH);
1384 
1385  // If we know that any of the high bits of the shift amount are one, then we
1386  // can do this as a couple of simple shifts.
1387  if (KnownOne.intersects(HighBitMask)) {
1388  // Mask out the high bit, which we know is set.
1389  Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1390  DAG.getConstant(~HighBitMask, ShTy));
1391 
1392  switch (N->getOpcode()) {
1393  default: llvm_unreachable("Unknown shift");
1394  case ISD::SHL:
1395  Lo = DAG.getConstant(0, NVT); // Low part is zero.
1396  Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1397  return true;
1398  case ISD::SRL:
1399  Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1400  Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1401  return true;
1402  case ISD::SRA:
1403  Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1404  DAG.getConstant(NVTBits-1, ShTy));
1405  Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1406  return true;
1407  }
1408  }
1409 
1410  // If we know that all of the high bits of the shift amount are zero, then we
1411  // can do this as a couple of simple shifts.
1412  if ((KnownZero & HighBitMask) == HighBitMask) {
1413  // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1414  // shift if x is zero. We can use XOR here because x is known to be smaller
1415  // than 32.
1416  SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1417  DAG.getConstant(NVTBits-1, ShTy));
1418 
1419  unsigned Op1, Op2;
1420  switch (N->getOpcode()) {
1421  default: llvm_unreachable("Unknown shift");
1422  case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1423  case ISD::SRL:
1424  case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1425  }
1426 
1427  // When shifting right the arithmetic for Lo and Hi is swapped.
1428  if (N->getOpcode() != ISD::SHL)
1429  std::swap(InL, InH);
1430 
1431  // Use a little trick to get the bits that move from Lo to Hi. First
1432  // shift by one bit.
1433  SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
1434  // Then compute the remaining shift with amount-1.
1435  SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1436 
1437  Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1438  Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1439 
1440  if (N->getOpcode() != ISD::SHL)
1441  std::swap(Hi, Lo);
1442  return true;
1443  }
1444 
1445  return false;
1446 }
1447 
1448 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1449 /// of any size.
1450 bool DAGTypeLegalizer::
1451 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1452  SDValue Amt = N->getOperand(1);
1453  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1454  EVT ShTy = Amt.getValueType();
1455  unsigned NVTBits = NVT.getSizeInBits();
1456  assert(isPowerOf2_32(NVTBits) &&
1457  "Expanded integer type size not a power of two!");
1458  SDLoc dl(N);
1459 
1460  // Get the incoming operand to be shifted.
1461  SDValue InL, InH;
1462  GetExpandedInteger(N->getOperand(0), InL, InH);
1463 
1464  SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1465  SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1466  SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1467  SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1468  Amt, NVBitsNode, ISD::SETULT);
1469 
1470  SDValue LoS, HiS, LoL, HiL;
1471  switch (N->getOpcode()) {
1472  default: llvm_unreachable("Unknown shift");
1473  case ISD::SHL:
1474  // Short: ShAmt < NVTBits
1475  LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1476  HiS = DAG.getNode(ISD::OR, dl, NVT,
1477  DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1478  // FIXME: If Amt is zero, the following shift generates an undefined result
1479  // on some architectures.
1480  DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1481 
1482  // Long: ShAmt >= NVTBits
1483  LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1484  HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1485 
1486  Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1487  Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1488  return true;
1489  case ISD::SRL:
1490  // Short: ShAmt < NVTBits
1491  HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1492  LoS = DAG.getNode(ISD::OR, dl, NVT,
1493  DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1494  // FIXME: If Amt is zero, the following shift generates an undefined result
1495  // on some architectures.
1496  DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1497 
1498  // Long: ShAmt >= NVTBits
1499  HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1500  LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1501 
1502  Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1503  Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1504  return true;
1505  case ISD::SRA:
1506  // Short: ShAmt < NVTBits
1507  HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1508  LoS = DAG.getNode(ISD::OR, dl, NVT,
1509  DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1510  // FIXME: If Amt is zero, the following shift generates an undefined result
1511  // on some architectures.
1512  DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1513 
1514  // Long: ShAmt >= NVTBits
1515  HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1516  DAG.getConstant(NVTBits-1, ShTy));
1517  LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1518 
1519  Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1520  Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1521  return true;
1522  }
1523 }
1524 
1525 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1526  SDValue &Lo, SDValue &Hi) {
1527  SDLoc dl(N);
1528  // Expand the subcomponents.
1529  SDValue LHSL, LHSH, RHSL, RHSH;
1530  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1531  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1532 
1533  EVT NVT = LHSL.getValueType();
1534  SDValue LoOps[2] = { LHSL, RHSL };
1535  SDValue HiOps[3] = { LHSH, RHSH };
1536 
1537  // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1538  // them. TODO: Teach operation legalization how to expand unsupported
1539  // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1540  // a carry of type MVT::Glue, but there doesn't seem to be any way to
1541  // generate a value of this type in the expanded code sequence.
1542  bool hasCarry =
1544  ISD::ADDC : ISD::SUBC,
1545  TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1546 
1547  if (hasCarry) {
1548  SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1549  if (N->getOpcode() == ISD::ADD) {
1550  Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1551  HiOps[2] = Lo.getValue(1);
1552  Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1553  } else {
1554  Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1555  HiOps[2] = Lo.getValue(1);
1556  Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1557  }
1558  return;
1559  }
1560 
1561  if (N->getOpcode() == ISD::ADD) {
1562  Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1563  Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1564  SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1565  ISD::SETULT);
1566  SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1567  DAG.getConstant(1, NVT),
1568  DAG.getConstant(0, NVT));
1569  SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1570  ISD::SETULT);
1571  SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1572  DAG.getConstant(1, NVT), Carry1);
1573  Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1574  } else {
1575  Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1576  Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1577  SDValue Cmp =
1578  DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1579  LoOps[0], LoOps[1], ISD::SETULT);
1580  SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1581  DAG.getConstant(1, NVT),
1582  DAG.getConstant(0, NVT));
1583  Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1584  }
1585 }
1586 
1587 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1588  SDValue &Lo, SDValue &Hi) {
1589  // Expand the subcomponents.
1590  SDValue LHSL, LHSH, RHSL, RHSH;
1591  SDLoc dl(N);
1592  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1593  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1594  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1595  SDValue LoOps[2] = { LHSL, RHSL };
1596  SDValue HiOps[3] = { LHSH, RHSH };
1597 
1598  if (N->getOpcode() == ISD::ADDC) {
1599  Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1600  HiOps[2] = Lo.getValue(1);
1601  Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1602  } else {
1603  Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1604  HiOps[2] = Lo.getValue(1);
1605  Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1606  }
1607 
1608  // Legalized the flag result - switch anything that used the old flag to
1609  // use the new one.
1610  ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1611 }
1612 
1613 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1614  SDValue &Lo, SDValue &Hi) {
1615  // Expand the subcomponents.
1616  SDValue LHSL, LHSH, RHSL, RHSH;
1617  SDLoc dl(N);
1618  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1619  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1620  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1621  SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1622  SDValue HiOps[3] = { LHSH, RHSH };
1623 
1624  Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1625  HiOps[2] = Lo.getValue(1);
1626  Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1627 
1628  // Legalized the flag result - switch anything that used the old flag to
1629  // use the new one.
1630  ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1631 }
1632 
1633 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1634  SDValue &Lo, SDValue &Hi) {
1635  SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1636  SplitInteger(Res, Lo, Hi);
1637 }
1638 
1639 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1640  SDValue &Lo, SDValue &Hi) {
1641  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1642  SDLoc dl(N);
1643  SDValue Op = N->getOperand(0);
1644  if (Op.getValueType().bitsLE(NVT)) {
1645  // The low part is any extension of the input (which degenerates to a copy).
1646  Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1647  Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1648  } else {
1649  // For example, extension of an i48 to an i64. The operand type necessarily
1650  // promotes to the result type, so will end up being expanded too.
1651  assert(getTypeAction(Op.getValueType()) ==
1653  "Only know how to promote this result!");
1654  SDValue Res = GetPromotedInteger(Op);
1655  assert(Res.getValueType() == N->getValueType(0) &&
1656  "Operand over promoted?");
1657  // Split the promoted operand. This will simplify when it is expanded.
1658  SplitInteger(Res, Lo, Hi);
1659  }
1660 }
1661 
1662 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1663  SDValue &Lo, SDValue &Hi) {
1664  SDLoc dl(N);
1665  GetExpandedInteger(N->getOperand(0), Lo, Hi);
1666  EVT NVT = Lo.getValueType();
1667  EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1668  unsigned NVTBits = NVT.getSizeInBits();
1669  unsigned EVTBits = EVT.getSizeInBits();
1670 
1671  if (NVTBits < EVTBits) {
1672  Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1674  EVTBits - NVTBits)));
1675  } else {
1676  Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1677  // The high part replicates the sign bit of Lo, make it explicit.
1678  Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1679  DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1680  }
1681 }
1682 
1683 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1684  SDValue &Lo, SDValue &Hi) {
1685  SDLoc dl(N);
1686  GetExpandedInteger(N->getOperand(0), Lo, Hi);
1687  EVT NVT = Lo.getValueType();
1688  EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1689  unsigned NVTBits = NVT.getSizeInBits();
1690  unsigned EVTBits = EVT.getSizeInBits();
1691 
1692  if (NVTBits < EVTBits) {
1693  Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1695  EVTBits - NVTBits)));
1696  } else {
1697  Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1698  // The high part must be zero, make it explicit.
1699  Hi = DAG.getConstant(0, NVT);
1700  }
1701 }
1702 
1703 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1704  SDValue &Lo, SDValue &Hi) {
1705  SDLoc dl(N);
1706  GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1707  Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1708  Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1709 }
1710 
1711 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1712  SDValue &Lo, SDValue &Hi) {
1713  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1714  unsigned NBitWidth = NVT.getSizeInBits();
1715  const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1716  Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT);
1717  Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1718 }
1719 
1720 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1721  SDValue &Lo, SDValue &Hi) {
1722  SDLoc dl(N);
1723  // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1724  GetExpandedInteger(N->getOperand(0), Lo, Hi);
1725  EVT NVT = Lo.getValueType();
1726 
1727  SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1728  DAG.getConstant(0, NVT), ISD::SETNE);
1729 
1730  SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1731  SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1732 
1733  Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1734  DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1735  DAG.getConstant(NVT.getSizeInBits(), NVT)));
1736  Hi = DAG.getConstant(0, NVT);
1737 }
1738 
1739 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1740  SDValue &Lo, SDValue &Hi) {
1741  SDLoc dl(N);
1742  // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1743  GetExpandedInteger(N->getOperand(0), Lo, Hi);
1744  EVT NVT = Lo.getValueType();
1745  Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1746  DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1747  Hi = DAG.getConstant(0, NVT);
1748 }
1749 
1750 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1751  SDValue &Lo, SDValue &Hi) {
1752  SDLoc dl(N);
1753  // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1754  GetExpandedInteger(N->getOperand(0), Lo, Hi);
1755  EVT NVT = Lo.getValueType();
1756 
1757  SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1758  DAG.getConstant(0, NVT), ISD::SETNE);
1759 
1760  SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1761  SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1762 
1763  Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1764  DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1765  DAG.getConstant(NVT.getSizeInBits(), NVT)));
1766  Hi = DAG.getConstant(0, NVT);
1767 }
1768 
1769 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1770  SDValue &Hi) {
1771  SDLoc dl(N);
1772  EVT VT = N->getValueType(0);
1773  SDValue Op = N->getOperand(0);
1775  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1776  SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,
1777  dl).first,
1778  Lo, Hi);
1779 }
1780 
1781 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1782  SDValue &Hi) {
1783  SDLoc dl(N);
1784  EVT VT = N->getValueType(0);
1785  SDValue Op = N->getOperand(0);
1787  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1788  SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,
1789  dl).first,
1790  Lo, Hi);
1791 }
1792 
1793 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1794  SDValue &Lo, SDValue &Hi) {
1795  if (ISD::isNormalLoad(N)) {
1796  ExpandRes_NormalLoad(N, Lo, Hi);
1797  return;
1798  }
1799 
1800  assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1801 
1802  EVT VT = N->getValueType(0);
1803  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1804  SDValue Ch = N->getChain();
1805  SDValue Ptr = N->getBasePtr();
1806  ISD::LoadExtType ExtType = N->getExtensionType();
1807  unsigned Alignment = N->getAlignment();
1808  bool isVolatile = N->isVolatile();
1809  bool isNonTemporal = N->isNonTemporal();
1810  bool isInvariant = N->isInvariant();
1811  const MDNode *TBAAInfo = N->getTBAAInfo();
1812  SDLoc dl(N);
1813 
1814  assert(NVT.isByteSized() && "Expanded type not byte sized!");
1815 
1816  if (N->getMemoryVT().bitsLE(NVT)) {
1817  EVT MemVT = N->getMemoryVT();
1818 
1819  Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1820  MemVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
1821 
1822  // Remember the chain.
1823  Ch = Lo.getValue(1);
1824 
1825  if (ExtType == ISD::SEXTLOAD) {
1826  // The high part is obtained by SRA'ing all but one of the bits of the
1827  // lo part.
1828  unsigned LoSize = Lo.getValueType().getSizeInBits();
1829  Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1830  DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1831  } else if (ExtType == ISD::ZEXTLOAD) {
1832  // The high part is just a zero.
1833  Hi = DAG.getConstant(0, NVT);
1834  } else {
1835  assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1836  // The high part is undefined.
1837  Hi = DAG.getUNDEF(NVT);
1838  }
1839  } else if (TLI.isLittleEndian()) {
1840  // Little-endian - low bits are at low addresses.
1841  Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1842  isVolatile, isNonTemporal, isInvariant, Alignment,
1843  TBAAInfo);
1844 
1845  unsigned ExcessBits =
1846  N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1847  EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1848 
1849  // Increment the pointer to the other half.
1850  unsigned IncrementSize = NVT.getSizeInBits()/8;
1851  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1852  DAG.getConstant(IncrementSize, Ptr.getValueType()));
1853  Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1854  N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1855  isVolatile, isNonTemporal,
1856  MinAlign(Alignment, IncrementSize), TBAAInfo);
1857 
1858  // Build a factor node to remember that this load is independent of the
1859  // other one.
1860  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1861  Hi.getValue(1));
1862  } else {
1863  // Big-endian - high bits are at low addresses. Favor aligned loads at
1864  // the cost of some bit-fiddling.
1865  EVT MemVT = N->getMemoryVT();
1866  unsigned EBytes = MemVT.getStoreSize();
1867  unsigned IncrementSize = NVT.getSizeInBits()/8;
1868  unsigned ExcessBits = (EBytes - IncrementSize)*8;
1869 
1870  // Load both the high bits and maybe some of the low bits.
1871  Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1873  MemVT.getSizeInBits() - ExcessBits),
1874  isVolatile, isNonTemporal, Alignment, TBAAInfo);
1875 
1876  // Increment the pointer to the other half.
1877  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1878  DAG.getConstant(IncrementSize, Ptr.getValueType()));
1879  // Load the rest of the low bits.
1880  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1881  N->getPointerInfo().getWithOffset(IncrementSize),
1882  EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1883  isVolatile, isNonTemporal,
1884  MinAlign(Alignment, IncrementSize), TBAAInfo);
1885 
1886  // Build a factor node to remember that this load is independent of the
1887  // other one.
1888  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1889  Hi.getValue(1));
1890 
1891  if (ExcessBits < NVT.getSizeInBits()) {
1892  // Transfer low bits from the bottom of Hi to the top of Lo.
1893  Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1894  DAG.getNode(ISD::SHL, dl, NVT, Hi,
1895  DAG.getConstant(ExcessBits,
1896  TLI.getPointerTy())));
1897  // Move high bits to the right position in Hi.
1898  Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1899  NVT, Hi,
1900  DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1901  TLI.getPointerTy()));
1902  }
1903  }
1904 
1905  // Legalized the chain result - switch anything that used the old chain to
1906  // use the new one.
1907  ReplaceValueWith(SDValue(N, 1), Ch);
1908 }
1909 
1910 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1911  SDValue &Lo, SDValue &Hi) {
1912  SDLoc dl(N);
1913  SDValue LL, LH, RL, RH;
1914  GetExpandedInteger(N->getOperand(0), LL, LH);
1915  GetExpandedInteger(N->getOperand(1), RL, RH);
1916  Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1917  Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1918 }
1919 
1920 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1921  SDValue &Lo, SDValue &Hi) {
1922  EVT VT = N->getValueType(0);
1923  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1924  SDLoc dl(N);
1925 
1926  bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1927  bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1928  bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1929  bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1930  if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1931  SDValue LL, LH, RL, RH;
1932  GetExpandedInteger(N->getOperand(0), LL, LH);
1933  GetExpandedInteger(N->getOperand(1), RL, RH);
1934  unsigned OuterBitSize = VT.getSizeInBits();
1935  unsigned InnerBitSize = NVT.getSizeInBits();
1936  unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1937  unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1938 
1939  APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1940  if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1941  DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1942  // The inputs are both zero-extended.
1943  if (HasUMUL_LOHI) {
1944  // We can emit a umul_lohi.
1945  Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1946  Hi = SDValue(Lo.getNode(), 1);
1947  return;
1948  }
1949  if (HasMULHU) {
1950  // We can emit a mulhu+mul.
1951  Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1952  Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1953  return;
1954  }
1955  }
1956  if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1957  // The input values are both sign-extended.
1958  if (HasSMUL_LOHI) {
1959  // We can emit a smul_lohi.
1960  Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1961  Hi = SDValue(Lo.getNode(), 1);
1962  return;
1963  }
1964  if (HasMULHS) {
1965  // We can emit a mulhs+mul.
1966  Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1967  Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1968  return;
1969  }
1970  }
1971  if (HasUMUL_LOHI) {
1972  // Lo,Hi = umul LHS, RHS.
1973  SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1974  DAG.getVTList(NVT, NVT), LL, RL);
1975  Lo = UMulLOHI;
1976  Hi = UMulLOHI.getValue(1);
1977  RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1978  LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1979  Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1980  Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1981  return;
1982  }
1983  if (HasMULHU) {
1984  Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1985  Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1986  RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1987  LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1988  Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1989  Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1990  return;
1991  }
1992  }
1993 
1994  // If nothing else, we can make a libcall.
1996  if (VT == MVT::i16)
1997  LC = RTLIB::MUL_I16;
1998  else if (VT == MVT::i32)
1999  LC = RTLIB::MUL_I32;
2000  else if (VT == MVT::i64)
2001  LC = RTLIB::MUL_I64;
2002  else if (VT == MVT::i128)
2003  LC = RTLIB::MUL_I128;
2004  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2005 
2006  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2007  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/,
2008  dl).first,
2009  Lo, Hi);
2010 }
2011 
2012 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2013  SDValue &Lo, SDValue &Hi) {
2014  SDValue LHS = Node->getOperand(0);
2015  SDValue RHS = Node->getOperand(1);
2016  SDLoc dl(Node);
2017 
2018  // Expand the result by simply replacing it with the equivalent
2019  // non-overflow-checking operation.
2020  SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2021  ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2022  LHS, RHS);
2023  SplitInteger(Sum, Lo, Hi);
2024 
2025  // Compute the overflow.
2026  //
2027  // LHSSign -> LHS >= 0
2028  // RHSSign -> RHS >= 0
2029  // SumSign -> Sum >= 0
2030  //
2031  // Add:
2032  // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2033  // Sub:
2034  // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2035  //
2036  EVT OType = Node->getValueType(1);
2037  SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2038 
2039  SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2040  SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2041  SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2042  Node->getOpcode() == ISD::SADDO ?
2044 
2045  SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2046  SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2047 
2048  SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2049 
2050  // Use the calculated overflow everywhere.
2051  ReplaceValueWith(SDValue(Node, 1), Cmp);
2052 }
2053 
2054 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2055  SDValue &Lo, SDValue &Hi) {
2056  EVT VT = N->getValueType(0);
2057  SDLoc dl(N);
2058 
2060  if (VT == MVT::i16)
2061  LC = RTLIB::SDIV_I16;
2062  else if (VT == MVT::i32)
2063  LC = RTLIB::SDIV_I32;
2064  else if (VT == MVT::i64)
2065  LC = RTLIB::SDIV_I64;
2066  else if (VT == MVT::i128)
2067  LC = RTLIB::SDIV_I128;
2068  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2069 
2070  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2071  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2072 }
2073 
2074 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2075  SDValue &Lo, SDValue &Hi) {
2076  EVT VT = N->getValueType(0);
2077  SDLoc dl(N);
2078 
2079  // If we can emit an efficient shift operation, do so now. Check to see if
2080  // the RHS is a constant.
2081  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2082  return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2083 
2084  // If we can determine that the high bit of the shift is zero or one, even if
2085  // the low bits are variable, emit this shift in an optimized form.
2086  if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2087  return;
2088 
2089  // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2090  unsigned PartsOpc;
2091  if (N->getOpcode() == ISD::SHL) {
2092  PartsOpc = ISD::SHL_PARTS;
2093  } else if (N->getOpcode() == ISD::SRL) {
2094  PartsOpc = ISD::SRL_PARTS;
2095  } else {
2096  assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2097  PartsOpc = ISD::SRA_PARTS;
2098  }
2099 
2100  // Next check to see if the target supports this SHL_PARTS operation or if it
2101  // will custom expand it.
2102  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2103  TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2104  if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2105  Action == TargetLowering::Custom) {
2106  // Expand the subcomponents.
2107  SDValue LHSL, LHSH;
2108  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2109  EVT VT = LHSL.getValueType();
2110 
2111  // If the shift amount operand is coming from a vector legalization it may
2112  // have an illegal type. Fix that first by casting the operand, otherwise
2113  // the new SHL_PARTS operation would need further legalization.
2114  SDValue ShiftOp = N->getOperand(1);
2115  EVT ShiftTy = TLI.getShiftAmountTy(VT);
2116  assert(ShiftTy.getScalarType().getSizeInBits() >=
2117  Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2118  "ShiftAmountTy is too small to cover the range of this type!");
2119  if (ShiftOp.getValueType() != ShiftTy)
2120  ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2121 
2122  SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2123  Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
2124  Hi = Lo.getValue(1);
2125  return;
2126  }
2127 
2128  // Otherwise, emit a libcall.
2130  bool isSigned;
2131  if (N->getOpcode() == ISD::SHL) {
2132  isSigned = false; /*sign irrelevant*/
2133  if (VT == MVT::i16)
2134  LC = RTLIB::SHL_I16;
2135  else if (VT == MVT::i32)
2136  LC = RTLIB::SHL_I32;
2137  else if (VT == MVT::i64)
2138  LC = RTLIB::SHL_I64;
2139  else if (VT == MVT::i128)
2140  LC = RTLIB::SHL_I128;
2141  } else if (N->getOpcode() == ISD::SRL) {
2142  isSigned = false;
2143  if (VT == MVT::i16)
2144  LC = RTLIB::SRL_I16;
2145  else if (VT == MVT::i32)
2146  LC = RTLIB::SRL_I32;
2147  else if (VT == MVT::i64)
2148  LC = RTLIB::SRL_I64;
2149  else if (VT == MVT::i128)
2150  LC = RTLIB::SRL_I128;
2151  } else {
2152  assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2153  isSigned = true;
2154  if (VT == MVT::i16)
2155  LC = RTLIB::SRA_I16;
2156  else if (VT == MVT::i32)
2157  LC = RTLIB::SRA_I32;
2158  else if (VT == MVT::i64)
2159  LC = RTLIB::SRA_I64;
2160  else if (VT == MVT::i128)
2161  LC = RTLIB::SRA_I128;
2162  }
2163 
2164  if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2165  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2166  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first, Lo,
2167  Hi);
2168  return;
2169  }
2170 
2171  if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2172  llvm_unreachable("Unsupported shift!");
2173 }
2174 
2175 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2176  SDValue &Lo, SDValue &Hi) {
2177  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2178  SDLoc dl(N);
2179  SDValue Op = N->getOperand(0);
2180  if (Op.getValueType().bitsLE(NVT)) {
2181  // The low part is sign extension of the input (degenerates to a copy).
2182  Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2183  // The high part is obtained by SRA'ing all but one of the bits of low part.
2184  unsigned LoSize = NVT.getSizeInBits();
2185  Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2186  DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2187  } else {
2188  // For example, extension of an i48 to an i64. The operand type necessarily
2189  // promotes to the result type, so will end up being expanded too.
2190  assert(getTypeAction(Op.getValueType()) ==
2192  "Only know how to promote this result!");
2193  SDValue Res = GetPromotedInteger(Op);
2194  assert(Res.getValueType() == N->getValueType(0) &&
2195  "Operand over promoted?");
2196  // Split the promoted operand. This will simplify when it is expanded.
2197  SplitInteger(Res, Lo, Hi);
2198  unsigned ExcessBits =
2199  Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2200  Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2202  ExcessBits)));
2203  }
2204 }
2205 
2206 void DAGTypeLegalizer::
2207 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2208  SDLoc dl(N);
2209  GetExpandedInteger(N->getOperand(0), Lo, Hi);
2210  EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2211 
2212  if (EVT.bitsLE(Lo.getValueType())) {
2213  // sext_inreg the low part if needed.
2214  Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2215  N->getOperand(1));
2216 
2217  // The high part gets the sign extension from the lo-part. This handles
2218  // things like sextinreg V:i64 from i8.
2219  Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2220  DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2221  TLI.getPointerTy()));
2222  } else {
2223  // For example, extension of an i48 to an i64. Leave the low part alone,
2224  // sext_inreg the high part.
2225  unsigned ExcessBits =
2226  EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2227  Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2229  ExcessBits)));
2230  }
2231 }
2232 
2233 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2234  SDValue &Lo, SDValue &Hi) {
2235  EVT VT = N->getValueType(0);
2236  SDLoc dl(N);
2237 
2239  if (VT == MVT::i16)
2240  LC = RTLIB::SREM_I16;
2241  else if (VT == MVT::i32)
2242  LC = RTLIB::SREM_I32;
2243  else if (VT == MVT::i64)
2244  LC = RTLIB::SREM_I64;
2245  else if (VT == MVT::i128)
2246  LC = RTLIB::SREM_I128;
2247  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2248 
2249  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2250  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2251 }
2252 
2253 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2254  SDValue &Lo, SDValue &Hi) {
2255  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2256  SDLoc dl(N);
2257  Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2258  Hi = DAG.getNode(ISD::SRL, dl,
2259  N->getOperand(0).getValueType(), N->getOperand(0),
2260  DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2261  Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2262 }
2263 
2264 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2265  SDValue &Lo, SDValue &Hi) {
2266  SDValue LHS = N->getOperand(0);
2267  SDValue RHS = N->getOperand(1);
2268  SDLoc dl(N);
2269 
2270  // Expand the result by simply replacing it with the equivalent
2271  // non-overflow-checking operation.
2272  SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2273  ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2274  LHS, RHS);
2275  SplitInteger(Sum, Lo, Hi);
2276 
2277  // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2278  // overflows iff a - b > a.
2279  SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2280  N->getOpcode () == ISD::UADDO ?
2282 
2283  // Use the calculated overflow everywhere.
2284  ReplaceValueWith(SDValue(N, 1), Ofl);
2285 }
2286 
2287 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2288  SDValue &Lo, SDValue &Hi) {
2289  EVT VT = N->getValueType(0);
2290  SDLoc dl(N);
2291 
2292  // A divide for UMULO should be faster than a function call.
2293  if (N->getOpcode() == ISD::UMULO) {
2294  SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2295 
2296  SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2297  SplitInteger(MUL, Lo, Hi);
2298 
2299  // A divide for UMULO will be faster than a function call. Select to
2300  // make sure we aren't using 0.
2301  SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2302  RHS, DAG.getConstant(0, VT), ISD::SETEQ);
2303  SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2304  DAG.getConstant(1, VT), RHS);
2305  SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2306  SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2307  ISD::SETNE);
2308  Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2309  DAG.getConstant(0, N->getValueType(1)),
2310  Overflow);
2311  ReplaceValueWith(SDValue(N, 1), Overflow);
2312  return;
2313  }
2314 
2315  Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2316  EVT PtrVT = TLI.getPointerTy();
2317  Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2318 
2319  // Replace this with a libcall that will check overflow.
2321  if (VT == MVT::i32)
2322  LC = RTLIB::MULO_I32;
2323  else if (VT == MVT::i64)
2324  LC = RTLIB::MULO_I64;
2325  else if (VT == MVT::i128)
2326  LC = RTLIB::MULO_I128;
2327  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2328 
2329  SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2330  // Temporary for the overflow value, default it to zero.
2331  SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2332  DAG.getConstant(0, PtrVT), Temp,
2333  MachinePointerInfo(), false, false, 0);
2334 
2337  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2338  EVT ArgVT = N->getOperand(i).getValueType();
2339  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2340  Entry.Node = N->getOperand(i);
2341  Entry.Ty = ArgTy;
2342  Entry.isSExt = true;
2343  Entry.isZExt = false;
2344  Args.push_back(Entry);
2345  }
2346 
2347  // Also pass the address of the overflow check.
2348  Entry.Node = Temp;
2349  Entry.Ty = PtrTy->getPointerTo();
2350  Entry.isSExt = true;
2351  Entry.isZExt = false;
2352  Args.push_back(Entry);
2353 
2354  SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2356  CallLoweringInfo CLI(Chain, RetTy, true, false, false, false,
2357  0, TLI.getLibcallCallingConv(LC),
2358  /*isTailCall=*/false,
2359  /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2360  Func, Args, DAG, dl);
2361  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2362 
2363  SplitInteger(CallInfo.first, Lo, Hi);
2364  SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2365  MachinePointerInfo(), false, false, false, 0);
2366  SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2367  DAG.getConstant(0, PtrVT),
2368  ISD::SETNE);
2369  // Use the overflow from the libcall everywhere.
2370  ReplaceValueWith(SDValue(N, 1), Ofl);
2371 }
2372 
2373 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2374  SDValue &Lo, SDValue &Hi) {
2375  EVT VT = N->getValueType(0);
2376  SDLoc dl(N);
2377 
2379  if (VT == MVT::i16)
2380  LC = RTLIB::UDIV_I16;
2381  else if (VT == MVT::i32)
2382  LC = RTLIB::UDIV_I32;
2383  else if (VT == MVT::i64)
2384  LC = RTLIB::UDIV_I64;
2385  else if (VT == MVT::i128)
2386  LC = RTLIB::UDIV_I128;
2387  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2388 
2389  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2390  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2391 }
2392 
2393 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2394  SDValue &Lo, SDValue &Hi) {
2395  EVT VT = N->getValueType(0);
2396  SDLoc dl(N);
2397 
2399  if (VT == MVT::i16)
2400  LC = RTLIB::UREM_I16;
2401  else if (VT == MVT::i32)
2402  LC = RTLIB::UREM_I32;
2403  else if (VT == MVT::i64)
2404  LC = RTLIB::UREM_I64;
2405  else if (VT == MVT::i128)
2406  LC = RTLIB::UREM_I128;
2407  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2408 
2409  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2410  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2411 }
2412 
2413 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2414  SDValue &Lo, SDValue &Hi) {
2415  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2416  SDLoc dl(N);
2417  SDValue Op = N->getOperand(0);
2418  if (Op.getValueType().bitsLE(NVT)) {
2419  // The low part is zero extension of the input (degenerates to a copy).
2420  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2421  Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2422  } else {
2423  // For example, extension of an i48 to an i64. The operand type necessarily
2424  // promotes to the result type, so will end up being expanded too.
2425  assert(getTypeAction(Op.getValueType()) ==
2427  "Only know how to promote this result!");
2428  SDValue Res = GetPromotedInteger(Op);
2429  assert(Res.getValueType() == N->getValueType(0) &&
2430  "Operand over promoted?");
2431  // Split the promoted operand. This will simplify when it is expanded.
2432  SplitInteger(Res, Lo, Hi);
2433  unsigned ExcessBits =
2434  Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2435  Hi = DAG.getZeroExtendInReg(Hi, dl,
2436  EVT::getIntegerVT(*DAG.getContext(),
2437  ExcessBits));
2438  }
2439 }
2440 
2441 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2442  SDValue &Lo, SDValue &Hi) {
2443  SDLoc dl(N);
2444  EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2445  SDValue Zero = DAG.getConstant(0, VT);
2446  SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
2447  N->getOperand(0),
2448  N->getOperand(1), Zero, Zero,
2449  cast<AtomicSDNode>(N)->getMemOperand(),
2450  cast<AtomicSDNode>(N)->getOrdering(),
2451  cast<AtomicSDNode>(N)->getSynchScope());
2452  ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2453  ReplaceValueWith(SDValue(N, 1), Swap.getValue(1));
2454 }
2455 
2456 //===----------------------------------------------------------------------===//
2457 // Integer Operand Expansion
2458 //===----------------------------------------------------------------------===//
2459 
2460 /// ExpandIntegerOperand - This method is called when the specified operand of
2461 /// the specified node is found to need expansion. At this point, all of the
2462 /// result types of the node are known to be legal, but other operands of the
2463 /// node may need promotion or expansion as well as the specified one.
2464 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2465  DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2466  SDValue Res = SDValue();
2467 
2468  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2469  return false;
2470 
2471  switch (N->getOpcode()) {
2472  default:
2473  #ifndef NDEBUG
2474  dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2475  N->dump(&DAG); dbgs() << "\n";
2476  #endif
2477  llvm_unreachable("Do not know how to expand this operator's operand!");
2478 
2479  case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2480  case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2481  case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2482  case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2483  case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2484  case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2485  case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2486  case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2487  case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2488  case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2489  case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2490  case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2491 
2492  case ISD::SHL:
2493  case ISD::SRA:
2494  case ISD::SRL:
2495  case ISD::ROTL:
2496  case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2497  case ISD::RETURNADDR:
2498  case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2499 
2500  case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2501  }
2502 
2503  // If the result is null, the sub-method took care of registering results etc.
2504  if (!Res.getNode()) return false;
2505 
2506  // If the result is N, the sub-method updated N in place. Tell the legalizer
2507  // core about this.
2508  if (Res.getNode() == N)
2509  return true;
2510 
2511  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2512  "Invalid operand expansion");
2513 
2514  ReplaceValueWith(SDValue(N, 0), Res);
2515  return false;
2516 }
2517 
2518 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2519 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2520 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2521  SDValue &NewRHS,
2522  ISD::CondCode &CCCode,
2523  SDLoc dl) {
2524  SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2525  GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2526  GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2527 
2528  if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2529  if (RHSLo == RHSHi) {
2530  if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2531  if (RHSCST->isAllOnesValue()) {
2532  // Equality comparison to -1.
2533  NewLHS = DAG.getNode(ISD::AND, dl,
2534  LHSLo.getValueType(), LHSLo, LHSHi);
2535  NewRHS = RHSLo;
2536  return;
2537  }
2538  }
2539  }
2540 
2541  NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2542  NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2543  NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2544  NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2545  return;
2546  }
2547 
2548  // If this is a comparison of the sign bit, just look at the top part.
2549  // X > -1, x < 0
2550  if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2551  if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2552  (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2553  NewLHS = LHSHi;
2554  NewRHS = RHSHi;
2555  return;
2556  }
2557 
2558  // FIXME: This generated code sucks.
2559  ISD::CondCode LowCC;
2560  switch (CCCode) {
2561  default: llvm_unreachable("Unknown integer setcc!");
2562  case ISD::SETLT:
2563  case ISD::SETULT: LowCC = ISD::SETULT; break;
2564  case ISD::SETGT:
2565  case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2566  case ISD::SETLE:
2567  case ISD::SETULE: LowCC = ISD::SETULE; break;
2568  case ISD::SETGE:
2569  case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2570  }
2571 
2572  // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2573  // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2574  // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2575 
2576  // NOTE: on targets without efficient SELECT of bools, we can always use
2577  // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2578  TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true, NULL);
2579  SDValue Tmp1, Tmp2;
2580  Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2581  LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2582  if (!Tmp1.getNode())
2583  Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2584  LHSLo, RHSLo, LowCC);
2585  Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2586  LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2587  if (!Tmp2.getNode())
2588  Tmp2 = DAG.getNode(ISD::SETCC, dl,
2589  getSetCCResultType(LHSHi.getValueType()),
2590  LHSHi, RHSHi, DAG.getCondCode(CCCode));
2591 
2592  ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2593  ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2594  if ((Tmp1C && Tmp1C->isNullValue()) ||
2595  (Tmp2C && Tmp2C->isNullValue() &&
2596  (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2597  CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2598  (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2599  (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2600  CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2601  // low part is known false, returns high part.
2602  // For LE / GE, if high part is known false, ignore the low part.
2603  // For LT / GT, if high part is known true, ignore the low part.
2604  NewLHS = Tmp2;
2605  NewRHS = SDValue();
2606  return;
2607  }
2608 
2609  NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2610  LHSHi, RHSHi, ISD::SETEQ, false,
2611  DagCombineInfo, dl);
2612  if (!NewLHS.getNode())
2613  NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2614  LHSHi, RHSHi, ISD::SETEQ);
2615  NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2616  NewLHS, Tmp1, Tmp2);
2617  NewRHS = SDValue();
2618 }
2619 
2620 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2621  SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2622  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2623  IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2624 
2625  // If ExpandSetCCOperands returned a scalar, we need to compare the result
2626  // against zero to select between true and false values.
2627  if (NewRHS.getNode() == 0) {
2628  NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2629  CCCode = ISD::SETNE;
2630  }
2631 
2632  // Update N to have the operands specified.
2633  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2634  DAG.getCondCode(CCCode), NewLHS, NewRHS,
2635  N->getOperand(4)), 0);
2636 }
2637 
2638 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2639  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2640  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2641  IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2642 
2643  // If ExpandSetCCOperands returned a scalar, we need to compare the result
2644  // against zero to select between true and false values.
2645  if (NewRHS.getNode() == 0) {
2646  NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2647  CCCode = ISD::SETNE;
2648  }
2649 
2650  // Update N to have the operands specified.
2651  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2652  N->getOperand(2), N->getOperand(3),
2653  DAG.getCondCode(CCCode)), 0);
2654 }
2655 
2656 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2657  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2658  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2659  IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2660 
2661  // If ExpandSetCCOperands returned a scalar, use it.
2662  if (NewRHS.getNode() == 0) {
2663  assert(NewLHS.getValueType() == N->getValueType(0) &&
2664  "Unexpected setcc expansion!");
2665  return NewLHS;
2666  }
2667 
2668  // Otherwise, update N to have the operands specified.
2669  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2670  DAG.getCondCode(CCCode)), 0);
2671 }
2672 
2673 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2674  // The value being shifted is legal, but the shift amount is too big.
2675  // It follows that either the result of the shift is undefined, or the
2676  // upper half of the shift amount is zero. Just use the lower half.
2677  SDValue Lo, Hi;
2678  GetExpandedInteger(N->getOperand(1), Lo, Hi);
2679  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2680 }
2681 
2682 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2683  // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2684  // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2685  // constant to valid type.
2686  SDValue Lo, Hi;
2687  GetExpandedInteger(N->getOperand(0), Lo, Hi);
2688  return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2689 }
2690 
2691 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2692  SDValue Op = N->getOperand(0);
2693  EVT DstVT = N->getValueType(0);
2695  assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2696  "Don't know how to expand this SINT_TO_FP!");
2697  return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first;
2698 }
2699 
2700 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2701  if (ISD::isNormalStore(N))
2702  return ExpandOp_NormalStore(N, OpNo);
2703 
2704  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2705  assert(OpNo == 1 && "Can only expand the stored value so far");
2706 
2707  EVT VT = N->getOperand(1).getValueType();
2708  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2709  SDValue Ch = N->getChain();
2710  SDValue Ptr = N->getBasePtr();
2711  unsigned Alignment = N->getAlignment();
2712  bool isVolatile = N->isVolatile();
2713  bool isNonTemporal = N->isNonTemporal();
2714  const MDNode *TBAAInfo = N->getTBAAInfo();
2715  SDLoc dl(N);
2716  SDValue Lo, Hi;
2717 
2718  assert(NVT.isByteSized() && "Expanded type not byte sized!");
2719 
2720  if (N->getMemoryVT().bitsLE(NVT)) {
2721  GetExpandedInteger(N->getValue(), Lo, Hi);
2722  return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2723  N->getMemoryVT(), isVolatile, isNonTemporal,
2724  Alignment, TBAAInfo);
2725  }
2726 
2727  if (TLI.isLittleEndian()) {
2728  // Little-endian - low bits are at low addresses.
2729  GetExpandedInteger(N->getValue(), Lo, Hi);
2730 
2731  Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2732  isVolatile, isNonTemporal, Alignment, TBAAInfo);
2733 
2734  unsigned ExcessBits =
2735  N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2736  EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2737 
2738  // Increment the pointer to the other half.
2739  unsigned IncrementSize = NVT.getSizeInBits()/8;
2740  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2741  DAG.getConstant(IncrementSize, Ptr.getValueType()));
2742  Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2743  N->getPointerInfo().getWithOffset(IncrementSize),
2744  NEVT, isVolatile, isNonTemporal,
2745  MinAlign(Alignment, IncrementSize), TBAAInfo);
2746  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2747  }
2748 
2749  // Big-endian - high bits are at low addresses. Favor aligned stores at
2750  // the cost of some bit-fiddling.
2751  GetExpandedInteger(N->getValue(), Lo, Hi);
2752 
2753  EVT ExtVT = N->getMemoryVT();
2754  unsigned EBytes = ExtVT.getStoreSize();
2755  unsigned IncrementSize = NVT.getSizeInBits()/8;
2756  unsigned ExcessBits = (EBytes - IncrementSize)*8;
2757  EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2758  ExtVT.getSizeInBits() - ExcessBits);
2759 
2760  if (ExcessBits < NVT.getSizeInBits()) {
2761  // Transfer high bits from the top of Lo to the bottom of Hi.
2762  Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2763  DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2764  TLI.getPointerTy()));
2765  Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2766  DAG.getNode(ISD::SRL, dl, NVT, Lo,
2767  DAG.getConstant(ExcessBits,
2768  TLI.getPointerTy())));
2769  }
2770 
2771  // Store both the high bits and maybe some of the low bits.
2772  Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2773  HiVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
2774 
2775  // Increment the pointer to the other half.
2776  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2777  DAG.getConstant(IncrementSize, Ptr.getValueType()));
2778  // Store the lowest ExcessBits bits in the second half.
2779  Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2780  N->getPointerInfo().getWithOffset(IncrementSize),
2781  EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2782  isVolatile, isNonTemporal,
2783  MinAlign(Alignment, IncrementSize), TBAAInfo);
2784  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2785 }
2786 
2787 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2788  SDValue InL, InH;
2789  GetExpandedInteger(N->getOperand(0), InL, InH);
2790  // Just truncate the low part of the source.
2791  return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2792 }
2793 
2794 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2795  SDValue Op = N->getOperand(0);
2796  EVT SrcVT = Op.getValueType();
2797  EVT DstVT = N->getValueType(0);
2798  SDLoc dl(N);
2799 
2800  // The following optimization is valid only if every value in SrcVT (when
2801  // treated as signed) is representable in DstVT. Check that the mantissa
2802  // size of DstVT is >= than the number of bits in SrcVT -1.
2803  const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2804  if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2806  // Do a signed conversion then adjust the result.
2807  SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2808  SignedConv = TLI.LowerOperation(SignedConv, DAG);
2809 
2810  // The result of the signed conversion needs adjusting if the 'sign bit' of
2811  // the incoming integer was set. To handle this, we dynamically test to see
2812  // if it is set, and, if so, add a fudge factor.
2813 
2814  const uint64_t F32TwoE32 = 0x4F800000ULL;
2815  const uint64_t F32TwoE64 = 0x5F800000ULL;
2816  const uint64_t F32TwoE128 = 0x7F800000ULL;
2817 
2818  APInt FF(32, 0);
2819  if (SrcVT == MVT::i32)
2820  FF = APInt(32, F32TwoE32);
2821  else if (SrcVT == MVT::i64)
2822  FF = APInt(32, F32TwoE64);
2823  else if (SrcVT == MVT::i128)
2824  FF = APInt(32, F32TwoE128);
2825  else
2826  llvm_unreachable("Unsupported UINT_TO_FP!");
2827 
2828  // Check whether the sign bit is set.
2829  SDValue Lo, Hi;
2830  GetExpandedInteger(Op, Lo, Hi);
2831  SDValue SignSet = DAG.getSetCC(dl,
2832  getSetCCResultType(Hi.getValueType()),
2833  Hi, DAG.getConstant(0, Hi.getValueType()),
2834  ISD::SETLT);
2835 
2836  // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2837  SDValue FudgePtr = DAG.getConstantPool(
2838  ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2839  TLI.getPointerTy());
2840 
2841  // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2842  SDValue Zero = DAG.getIntPtrConstant(0);
2843  SDValue Four = DAG.getIntPtrConstant(4);
2844  if (TLI.isBigEndian()) std::swap(Zero, Four);
2845  SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
2846  Zero, Four);
2847  unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2848  FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2849  FudgePtr, Offset);
2850  Alignment = std::min(Alignment, 4u);
2851 
2852  // Load the value out, extending it from f32 to the destination float type.
2853  // FIXME: Avoid the extend by constructing the right constant pool?
2854  SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2855  FudgePtr,
2857  MVT::f32,
2858  false, false, Alignment);
2859  return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2860  }
2861 
2862  // Otherwise, use a libcall.
2863  RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2864  assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2865  "Don't know how to expand this UINT_TO_FP!");
2866  return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first;
2867 }
2868 
2869 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2870  SDLoc dl(N);
2871  SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2872  cast<AtomicSDNode>(N)->getMemoryVT(),
2873  N->getOperand(0),
2874  N->getOperand(1), N->getOperand(2),
2875  cast<AtomicSDNode>(N)->getMemOperand(),
2876  cast<AtomicSDNode>(N)->getOrdering(),
2877  cast<AtomicSDNode>(N)->getSynchScope());
2878  return Swap.getValue(1);
2879 }
2880 
2881 
2882 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2883  SDValue InOp0 = N->getOperand(0);
2884  EVT InVT = InOp0.getValueType();
2885 
2886  EVT OutVT = N->getValueType(0);
2887  EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2888  assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2889  unsigned OutNumElems = OutVT.getVectorNumElements();
2890  EVT NOutVTElem = NOutVT.getVectorElementType();
2891 
2892  SDLoc dl(N);
2893  SDValue BaseIdx = N->getOperand(1);
2894 
2896  Ops.reserve(OutNumElems);
2897  for (unsigned i = 0; i != OutNumElems; ++i) {
2898 
2899  // Extract the element from the original vector.
2900  SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2901  BaseIdx, DAG.getConstant(i, BaseIdx.getValueType()));
2902  SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2903  InVT.getVectorElementType(), N->getOperand(0), Index);
2904 
2905  SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2906  // Insert the converted element to the new vector.
2907  Ops.push_back(Op);
2908  }
2909 
2910  return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2911 }
2912 
2913 
2914 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2915  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2916  EVT VT = N->getValueType(0);
2917  SDLoc dl(N);
2918 
2919  unsigned NumElts = VT.getVectorNumElements();
2920  SmallVector<int, 8> NewMask;
2921  for (unsigned i = 0; i != NumElts; ++i) {
2922  NewMask.push_back(SV->getMaskElt(i));
2923  }
2924 
2925  SDValue V0 = GetPromotedInteger(N->getOperand(0));
2926  SDValue V1 = GetPromotedInteger(N->getOperand(1));
2927  EVT OutVT = V0.getValueType();
2928 
2929  return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2930 }
2931 
2932 
2933 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2934  EVT OutVT = N->getValueType(0);
2935  EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2936  assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2937  unsigned NumElems = N->getNumOperands();
2938  EVT NOutVTElem = NOutVT.getVectorElementType();
2939 
2940  SDLoc dl(N);
2941 
2943  Ops.reserve(NumElems);
2944  for (unsigned i = 0; i != NumElems; ++i) {
2945  SDValue Op;
2946  // BUILD_VECTOR integer operand types are allowed to be larger than the
2947  // result's element type. This may still be true after the promotion. For
2948  // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
2949  // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
2950  if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
2951  Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2952  else
2953  Op = N->getOperand(i);
2954  Ops.push_back(Op);
2955  }
2956 
2957  return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2958 }
2959 
2960 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2961 
2962  SDLoc dl(N);
2963 
2964  assert(!N->getOperand(0).getValueType().isVector() &&
2965  "Input must be a scalar");
2966 
2967  EVT OutVT = N->getValueType(0);
2968  EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2969  assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2970  EVT NOutVTElem = NOutVT.getVectorElementType();
2971 
2972  SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2973 
2974  return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2975 }
2976 
2977 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
2978  SDLoc dl(N);
2979 
2980  EVT OutVT = N->getValueType(0);
2981  EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2982  assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2983 
2984  EVT InElemTy = OutVT.getVectorElementType();
2985  EVT OutElemTy = NOutVT.getVectorElementType();
2986 
2987  unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
2988  unsigned NumOutElem = NOutVT.getVectorNumElements();
2989  unsigned NumOperands = N->getNumOperands();
2990  assert(NumElem * NumOperands == NumOutElem &&
2991  "Unexpected number of elements");
2992 
2993  // Take the elements from the first vector.
2994  SmallVector<SDValue, 8> Ops(NumOutElem);
2995  for (unsigned i = 0; i < NumOperands; ++i) {
2996  SDValue Op = N->getOperand(i);
2997  for (unsigned j = 0; j < NumElem; ++j) {
2998  SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2999  InElemTy, Op, DAG.getConstant(j,
3000  TLI.getVectorIdxTy()));
3001  Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3002  }
3003  }
3004 
3005  return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
3006 }
3007 
3008 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3009  EVT OutVT = N->getValueType(0);
3010  EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3011  assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3012 
3013  EVT NOutVTElem = NOutVT.getVectorElementType();
3014 
3015  SDLoc dl(N);
3016  SDValue V0 = GetPromotedInteger(N->getOperand(0));
3017 
3018  SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3019  NOutVTElem, N->getOperand(1));
3020  return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3021  V0, ConvElem, N->getOperand(2));
3022 }
3023 
3024 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3025  SDLoc dl(N);
3026  SDValue V0 = GetPromotedInteger(N->getOperand(0));
3027  SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, TLI.getVectorIdxTy());
3028  SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3029  V0->getValueType(0).getScalarType(), V0, V1);
3030 
3031  // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3032  // element types. If this is the case then we need to expand the outgoing
3033  // value and not truncate it.
3034  return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3035 }
3036 
3037 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3038  SDLoc dl(N);
3039  unsigned NumElems = N->getNumOperands();
3040 
3041  EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3042 
3043  SmallVector<SDValue, 8> NewOps;
3044  NewOps.reserve(NumElems);
3045 
3046  // For each incoming vector
3047  for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3048  SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3049  EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3050  unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3051 
3052  for (unsigned i=0; i<NumElem; ++i) {
3053  // Extract element from incoming vector
3054  SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3055  Incoming, DAG.getConstant(i, TLI.getVectorIdxTy()));
3056  SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3057  NewOps.push_back(Tr);
3058  }
3059  }
3060 
3061  return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0),
3062  &NewOps[0], NewOps.size());
3063  }
void push_back(const T &Elt)
Definition: SmallVector.h:236
unsigned Log2_32_Ceil(uint32_t Value)
Definition: MathExtras.h:456
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false)
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
SDValue getValue(unsigned R) const
void reserve(unsigned N)
Definition: SmallVector.h:425
LLVMContext * getContext() const
Definition: SelectionDAG.h:285
void dump() const
dump - Dump this node, for debugging.
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
SDValue getVAArg(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
void setBit(unsigned bitPosition)
Set a given bit to 1.
Definition: APInt.cpp:583
enable_if_c<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:266
unsigned getOpcode() const
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
unsigned getSizeInBits() const
Definition: ValueTypes.h:359
SDValue getZeroExtendInReg(SDValue Op, SDLoc DL, EVT SrcTy)
unsigned getNumOperands() const
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
MDNode - a tuple of other values.
Definition: Metadata.h:69
const SDValue & getOperand(unsigned Num) const
static MachinePointerInfo getConstantPool()
void ComputeMaskedBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Same for subtraction.
Definition: ISDOpcodes.h:216
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
const SDValue & getBasePtr() const
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
Definition: ValueTypes.h:735
SDValue getExternalSymbol(const char *Sym, EVT VT)
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=0, const MDNode *Ranges=0)
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:661
EVT getShiftAmountTy(EVT LHSTy) const
bool isLittleEndian() const
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=0)
bool isNormalStore(const SDNode *N)
#define llvm_unreachable(msg)
EVT getValueType(unsigned ResNo) const
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1127
MachinePointerInfo getWithOffset(int64_t O) const
SimpleValueType SimpleTy
Definition: ValueTypes.h:161
EVT getScalarType() const
Definition: ValueTypes.h:756
int getMaskElt(unsigned Idx) const
SDVTList getVTList(EVT VT)
virtual MVT getPointerTy(uint32_t=0) const
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const
EVT getVectorElementType() const
Definition: ValueTypes.h:762
SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope)
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
bool isUNINDEXEDStore(const SDNode *N)
unsigned getNumValues() const
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:176
AtomicOrdering getOrdering() const
static unsigned int semanticsPrecision(const fltSemantics &)
Definition: APFloat.cpp:826
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:585
EVT getMemoryVT() const
getMemoryVT - Return the type of the in-memory value.
virtual MVT getVectorIdxTy() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
Definition: ValueTypes.h:741
UNDEF - An undefined node.
Definition: ISDOpcodes.h:154
const SDValue & getBasePtr() const
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:510
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getStoreSize() const
Definition: ValueTypes.h:787
bool isTypeLegal(EVT VT) const
bool isNormalLoad(const SDNode *N)
Float from Float.
Definition: ISDOpcodes.h:802
SynchronizationScope getSynchScope() const
bool intersects(const APInt &RHS) const
Definition: APInt.h:1144
APInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:919
Simple binary floating point operators.
Definition: ISDOpcodes.h:222
bool isNonTemporal() const
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Signed from Signed.
Definition: ISDOpcodes.h:807
bool isVolatile() const
const SDValue & getValue() const
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:312
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
std::vector< ArgListEntry > ArgListTy
bool bitsEq(EVT VT) const
bitsEq - Return true if this has the same number of bits as VT.
Definition: ValueTypes.h:717
PointerType * getPointerTo(unsigned AddrSpace=0)
Definition: Type.cpp:756
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:616
uint64_t getConstantOperandVal(unsigned Num) const
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
const MachinePointerInfo & getPointerInfo() const
bool isUNINDEXEDLoad(const SDNode *N)
static bool isZero(Value *V, DataLayout *DL)
Definition: Lint.cpp:507
SDValue getConvertRndSat(EVT VT, SDLoc dl, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code)
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
bool isInvariant() const
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=0)
Signed from Float.
Definition: ISDOpcodes.h:805
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
const SDValue & getChain() const
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:309
MachineMemOperand * getMemOperand() const
Unsigned from Signed.
Definition: ISDOpcodes.h:809
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
Definition: Constants.cpp:492
raw_ostream & dbgs()
dbgs - Return a circular-buffered debug stream.
Definition: Debug.cpp:101
unsigned Log2_32(uint32_t Value)
Definition: MathExtras.h:443
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:591
const MDNode * getTBAAInfo() const
Returns the TBAAInfo that describes the dereference.
ISD::LoadExtType getExtensionType() const
Class for arbitrary precision integers.
Definition: APInt.h:75
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:357
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:360
uint64_t MinAlign(uint64_t A, uint64_t B)
Definition: MathExtras.h:535
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:295
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:779
#define N
SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, bool isNonTemporal, bool isVolatile, unsigned Alignment, const MDNode *TBAAInfo=0)
Same for multiplication.
Definition: ISDOpcodes.h:219
bool isNON_EXTLoad(const SDNode *N)
EVT getValueType() const
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
bool isByteSized() const
isByteSized - Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:706
SDValue getSelect(SDLoc DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Definition: SelectionDAG.h:666
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
SDValue getValueType(EVT)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
#define DEBUG(X)
Definition: Debug.h:97
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:354
Signed from Unsigned.
Definition: ISDOpcodes.h:808
Float from Signed.
Definition: ISDOpcodes.h:803
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Definition: SelectionDAG.h:653
SDValue getEntryNode() const
Definition: SelectionDAG.h:332
Unsigned from Float.
Definition: ISDOpcodes.h:806
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:363
unsigned getAlignment() const
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:607
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
Float from Unsigned.
Definition: ISDOpcodes.h:804
MVT getSimpleVT() const
Definition: ValueTypes.h:749
unsigned getVectorNumElements() const
Definition: ValueTypes.h:771