LLVM API Documentation

 All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Groups Pages
TargetLoweringBase.cpp
Go to the documentation of this file.
1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the TargetLoweringBase class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/CodeGen/Analysis.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Target/TargetLoweringObjectFile.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
33 #include <cctype>
34 using namespace llvm;
35 
36 /// InitLibcallNames - Set default libcall names.
37 ///
38 static void InitLibcallNames(const char **Names, const TargetMachine &TM) {
39  Names[RTLIB::SHL_I16] = "__ashlhi3";
40  Names[RTLIB::SHL_I32] = "__ashlsi3";
41  Names[RTLIB::SHL_I64] = "__ashldi3";
42  Names[RTLIB::SHL_I128] = "__ashlti3";
43  Names[RTLIB::SRL_I16] = "__lshrhi3";
44  Names[RTLIB::SRL_I32] = "__lshrsi3";
45  Names[RTLIB::SRL_I64] = "__lshrdi3";
46  Names[RTLIB::SRL_I128] = "__lshrti3";
47  Names[RTLIB::SRA_I16] = "__ashrhi3";
48  Names[RTLIB::SRA_I32] = "__ashrsi3";
49  Names[RTLIB::SRA_I64] = "__ashrdi3";
50  Names[RTLIB::SRA_I128] = "__ashrti3";
51  Names[RTLIB::MUL_I8] = "__mulqi3";
52  Names[RTLIB::MUL_I16] = "__mulhi3";
53  Names[RTLIB::MUL_I32] = "__mulsi3";
54  Names[RTLIB::MUL_I64] = "__muldi3";
55  Names[RTLIB::MUL_I128] = "__multi3";
56  Names[RTLIB::MULO_I32] = "__mulosi4";
57  Names[RTLIB::MULO_I64] = "__mulodi4";
58  Names[RTLIB::MULO_I128] = "__muloti4";
59  Names[RTLIB::SDIV_I8] = "__divqi3";
60  Names[RTLIB::SDIV_I16] = "__divhi3";
61  Names[RTLIB::SDIV_I32] = "__divsi3";
62  Names[RTLIB::SDIV_I64] = "__divdi3";
63  Names[RTLIB::SDIV_I128] = "__divti3";
64  Names[RTLIB::UDIV_I8] = "__udivqi3";
65  Names[RTLIB::UDIV_I16] = "__udivhi3";
66  Names[RTLIB::UDIV_I32] = "__udivsi3";
67  Names[RTLIB::UDIV_I64] = "__udivdi3";
68  Names[RTLIB::UDIV_I128] = "__udivti3";
69  Names[RTLIB::SREM_I8] = "__modqi3";
70  Names[RTLIB::SREM_I16] = "__modhi3";
71  Names[RTLIB::SREM_I32] = "__modsi3";
72  Names[RTLIB::SREM_I64] = "__moddi3";
73  Names[RTLIB::SREM_I128] = "__modti3";
74  Names[RTLIB::UREM_I8] = "__umodqi3";
75  Names[RTLIB::UREM_I16] = "__umodhi3";
76  Names[RTLIB::UREM_I32] = "__umodsi3";
77  Names[RTLIB::UREM_I64] = "__umoddi3";
78  Names[RTLIB::UREM_I128] = "__umodti3";
79 
80  // These are generally not available.
81  Names[RTLIB::SDIVREM_I8] = 0;
82  Names[RTLIB::SDIVREM_I16] = 0;
83  Names[RTLIB::SDIVREM_I32] = 0;
84  Names[RTLIB::SDIVREM_I64] = 0;
85  Names[RTLIB::SDIVREM_I128] = 0;
86  Names[RTLIB::UDIVREM_I8] = 0;
87  Names[RTLIB::UDIVREM_I16] = 0;
88  Names[RTLIB::UDIVREM_I32] = 0;
89  Names[RTLIB::UDIVREM_I64] = 0;
90  Names[RTLIB::UDIVREM_I128] = 0;
91 
92  Names[RTLIB::NEG_I32] = "__negsi2";
93  Names[RTLIB::NEG_I64] = "__negdi2";
94  Names[RTLIB::ADD_F32] = "__addsf3";
95  Names[RTLIB::ADD_F64] = "__adddf3";
96  Names[RTLIB::ADD_F80] = "__addxf3";
97  Names[RTLIB::ADD_F128] = "__addtf3";
98  Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
99  Names[RTLIB::SUB_F32] = "__subsf3";
100  Names[RTLIB::SUB_F64] = "__subdf3";
101  Names[RTLIB::SUB_F80] = "__subxf3";
102  Names[RTLIB::SUB_F128] = "__subtf3";
103  Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
104  Names[RTLIB::MUL_F32] = "__mulsf3";
105  Names[RTLIB::MUL_F64] = "__muldf3";
106  Names[RTLIB::MUL_F80] = "__mulxf3";
107  Names[RTLIB::MUL_F128] = "__multf3";
108  Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
109  Names[RTLIB::DIV_F32] = "__divsf3";
110  Names[RTLIB::DIV_F64] = "__divdf3";
111  Names[RTLIB::DIV_F80] = "__divxf3";
112  Names[RTLIB::DIV_F128] = "__divtf3";
113  Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
114  Names[RTLIB::REM_F32] = "fmodf";
115  Names[RTLIB::REM_F64] = "fmod";
116  Names[RTLIB::REM_F80] = "fmodl";
117  Names[RTLIB::REM_F128] = "fmodl";
118  Names[RTLIB::REM_PPCF128] = "fmodl";
119  Names[RTLIB::FMA_F32] = "fmaf";
120  Names[RTLIB::FMA_F64] = "fma";
121  Names[RTLIB::FMA_F80] = "fmal";
122  Names[RTLIB::FMA_F128] = "fmal";
123  Names[RTLIB::FMA_PPCF128] = "fmal";
124  Names[RTLIB::POWI_F32] = "__powisf2";
125  Names[RTLIB::POWI_F64] = "__powidf2";
126  Names[RTLIB::POWI_F80] = "__powixf2";
127  Names[RTLIB::POWI_F128] = "__powitf2";
128  Names[RTLIB::POWI_PPCF128] = "__powitf2";
129  Names[RTLIB::SQRT_F32] = "sqrtf";
130  Names[RTLIB::SQRT_F64] = "sqrt";
131  Names[RTLIB::SQRT_F80] = "sqrtl";
132  Names[RTLIB::SQRT_F128] = "sqrtl";
133  Names[RTLIB::SQRT_PPCF128] = "sqrtl";
134  Names[RTLIB::LOG_F32] = "logf";
135  Names[RTLIB::LOG_F64] = "log";
136  Names[RTLIB::LOG_F80] = "logl";
137  Names[RTLIB::LOG_F128] = "logl";
138  Names[RTLIB::LOG_PPCF128] = "logl";
139  Names[RTLIB::LOG2_F32] = "log2f";
140  Names[RTLIB::LOG2_F64] = "log2";
141  Names[RTLIB::LOG2_F80] = "log2l";
142  Names[RTLIB::LOG2_F128] = "log2l";
143  Names[RTLIB::LOG2_PPCF128] = "log2l";
144  Names[RTLIB::LOG10_F32] = "log10f";
145  Names[RTLIB::LOG10_F64] = "log10";
146  Names[RTLIB::LOG10_F80] = "log10l";
147  Names[RTLIB::LOG10_F128] = "log10l";
148  Names[RTLIB::LOG10_PPCF128] = "log10l";
149  Names[RTLIB::EXP_F32] = "expf";
150  Names[RTLIB::EXP_F64] = "exp";
151  Names[RTLIB::EXP_F80] = "expl";
152  Names[RTLIB::EXP_F128] = "expl";
153  Names[RTLIB::EXP_PPCF128] = "expl";
154  Names[RTLIB::EXP2_F32] = "exp2f";
155  Names[RTLIB::EXP2_F64] = "exp2";
156  Names[RTLIB::EXP2_F80] = "exp2l";
157  Names[RTLIB::EXP2_F128] = "exp2l";
158  Names[RTLIB::EXP2_PPCF128] = "exp2l";
159  Names[RTLIB::SIN_F32] = "sinf";
160  Names[RTLIB::SIN_F64] = "sin";
161  Names[RTLIB::SIN_F80] = "sinl";
162  Names[RTLIB::SIN_F128] = "sinl";
163  Names[RTLIB::SIN_PPCF128] = "sinl";
164  Names[RTLIB::COS_F32] = "cosf";
165  Names[RTLIB::COS_F64] = "cos";
166  Names[RTLIB::COS_F80] = "cosl";
167  Names[RTLIB::COS_F128] = "cosl";
168  Names[RTLIB::COS_PPCF128] = "cosl";
169  Names[RTLIB::POW_F32] = "powf";
170  Names[RTLIB::POW_F64] = "pow";
171  Names[RTLIB::POW_F80] = "powl";
172  Names[RTLIB::POW_F128] = "powl";
173  Names[RTLIB::POW_PPCF128] = "powl";
174  Names[RTLIB::CEIL_F32] = "ceilf";
175  Names[RTLIB::CEIL_F64] = "ceil";
176  Names[RTLIB::CEIL_F80] = "ceill";
177  Names[RTLIB::CEIL_F128] = "ceill";
178  Names[RTLIB::CEIL_PPCF128] = "ceill";
179  Names[RTLIB::TRUNC_F32] = "truncf";
180  Names[RTLIB::TRUNC_F64] = "trunc";
181  Names[RTLIB::TRUNC_F80] = "truncl";
182  Names[RTLIB::TRUNC_F128] = "truncl";
183  Names[RTLIB::TRUNC_PPCF128] = "truncl";
184  Names[RTLIB::RINT_F32] = "rintf";
185  Names[RTLIB::RINT_F64] = "rint";
186  Names[RTLIB::RINT_F80] = "rintl";
187  Names[RTLIB::RINT_F128] = "rintl";
188  Names[RTLIB::RINT_PPCF128] = "rintl";
189  Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
190  Names[RTLIB::NEARBYINT_F64] = "nearbyint";
191  Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
192  Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
193  Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
194  Names[RTLIB::ROUND_F32] = "roundf";
195  Names[RTLIB::ROUND_F64] = "round";
196  Names[RTLIB::ROUND_F80] = "roundl";
197  Names[RTLIB::ROUND_F128] = "roundl";
198  Names[RTLIB::ROUND_PPCF128] = "roundl";
199  Names[RTLIB::FLOOR_F32] = "floorf";
200  Names[RTLIB::FLOOR_F64] = "floor";
201  Names[RTLIB::FLOOR_F80] = "floorl";
202  Names[RTLIB::FLOOR_F128] = "floorl";
203  Names[RTLIB::FLOOR_PPCF128] = "floorl";
204  Names[RTLIB::COPYSIGN_F32] = "copysignf";
205  Names[RTLIB::COPYSIGN_F64] = "copysign";
206  Names[RTLIB::COPYSIGN_F80] = "copysignl";
207  Names[RTLIB::COPYSIGN_F128] = "copysignl";
208  Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
209  Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
210  Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
211  Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
212  Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
213  Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
214  Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
215  Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
216  Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
217  Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
218  Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
219  Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
220  Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
221  Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
222  Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
223  Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
224  Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
225  Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
226  Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
227  Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
228  Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
229  Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
230  Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
231  Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
232  Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
233  Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
234  Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
235  Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
236  Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
237  Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
238  Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
239  Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
240  Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
241  Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
242  Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
243  Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
244  Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
245  Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
246  Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
247  Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
248  Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
249  Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
250  Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
251  Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
252  Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
253  Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
254  Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
255  Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
256  Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
257  Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
258  Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
259  Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
260  Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
261  Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
262  Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
263  Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
264  Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
265  Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
266  Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
267  Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
268  Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
269  Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
270  Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
271  Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
272  Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
273  Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
274  Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
275  Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
276  Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
277  Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
278  Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
279  Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
280  Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
281  Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
282  Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
283  Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
284  Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
285  Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
286  Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
287  Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
288  Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
289  Names[RTLIB::OEQ_F32] = "__eqsf2";
290  Names[RTLIB::OEQ_F64] = "__eqdf2";
291  Names[RTLIB::OEQ_F128] = "__eqtf2";
292  Names[RTLIB::UNE_F32] = "__nesf2";
293  Names[RTLIB::UNE_F64] = "__nedf2";
294  Names[RTLIB::UNE_F128] = "__netf2";
295  Names[RTLIB::OGE_F32] = "__gesf2";
296  Names[RTLIB::OGE_F64] = "__gedf2";
297  Names[RTLIB::OGE_F128] = "__getf2";
298  Names[RTLIB::OLT_F32] = "__ltsf2";
299  Names[RTLIB::OLT_F64] = "__ltdf2";
300  Names[RTLIB::OLT_F128] = "__lttf2";
301  Names[RTLIB::OLE_F32] = "__lesf2";
302  Names[RTLIB::OLE_F64] = "__ledf2";
303  Names[RTLIB::OLE_F128] = "__letf2";
304  Names[RTLIB::OGT_F32] = "__gtsf2";
305  Names[RTLIB::OGT_F64] = "__gtdf2";
306  Names[RTLIB::OGT_F128] = "__gttf2";
307  Names[RTLIB::UO_F32] = "__unordsf2";
308  Names[RTLIB::UO_F64] = "__unorddf2";
309  Names[RTLIB::UO_F128] = "__unordtf2";
310  Names[RTLIB::O_F32] = "__unordsf2";
311  Names[RTLIB::O_F64] = "__unorddf2";
312  Names[RTLIB::O_F128] = "__unordtf2";
313  Names[RTLIB::MEMCPY] = "memcpy";
314  Names[RTLIB::MEMMOVE] = "memmove";
315  Names[RTLIB::MEMSET] = "memset";
316  Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
317  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
318  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
319  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
320  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
321  Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
322  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
323  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
324  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
325  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
326  Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
327  Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
328  Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
329  Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
330  Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
331  Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
332  Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
333  Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
334  Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
335  Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
336  Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
337  Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
338  Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
339  Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
340  Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
341  Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
342  Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
343  Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
344  Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
345  Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
346  Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
347  Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
348  Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
349  Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
350  Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
351  Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
352  Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
353  Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
354  Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
355  Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
356  Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
357  Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
358  Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
359  Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
360  Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
361  Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
362  Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
363  Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
364  Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
365  Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
366  Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
367  Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
368  Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
369  Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
370  Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
371  Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
372  Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
373  Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
374  Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
375  Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
376  Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
377 
378  if (Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU) {
379  Names[RTLIB::SINCOS_F32] = "sincosf";
380  Names[RTLIB::SINCOS_F64] = "sincos";
381  Names[RTLIB::SINCOS_F80] = "sincosl";
382  Names[RTLIB::SINCOS_F128] = "sincosl";
383  Names[RTLIB::SINCOS_PPCF128] = "sincosl";
384  } else {
385  // These are generally not available.
386  Names[RTLIB::SINCOS_F32] = 0;
387  Names[RTLIB::SINCOS_F64] = 0;
388  Names[RTLIB::SINCOS_F80] = 0;
389  Names[RTLIB::SINCOS_F128] = 0;
390  Names[RTLIB::SINCOS_PPCF128] = 0;
391  }
392 
393  if (Triple(TM.getTargetTriple()).getOS() != Triple::OpenBSD) {
394  Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
395  } else {
396  // These are generally not available.
397  Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = 0;
398  }
399 }
400 
401 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
402 ///
403 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
404  for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
405  CCs[i] = CallingConv::C;
406  }
407 }
408 
409 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
410 /// UNKNOWN_LIBCALL if there is none.
411 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
412  if (OpVT == MVT::f32) {
413  if (RetVT == MVT::f64)
414  return FPEXT_F32_F64;
415  if (RetVT == MVT::f128)
416  return FPEXT_F32_F128;
417  } else if (OpVT == MVT::f64) {
418  if (RetVT == MVT::f128)
419  return FPEXT_F64_F128;
420  }
421 
422  return UNKNOWN_LIBCALL;
423 }
424 
425 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
426 /// UNKNOWN_LIBCALL if there is none.
427 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
428  if (RetVT == MVT::f32) {
429  if (OpVT == MVT::f64)
430  return FPROUND_F64_F32;
431  if (OpVT == MVT::f80)
432  return FPROUND_F80_F32;
433  if (OpVT == MVT::f128)
434  return FPROUND_F128_F32;
435  if (OpVT == MVT::ppcf128)
436  return FPROUND_PPCF128_F32;
437  } else if (RetVT == MVT::f64) {
438  if (OpVT == MVT::f80)
439  return FPROUND_F80_F64;
440  if (OpVT == MVT::f128)
441  return FPROUND_F128_F64;
442  if (OpVT == MVT::ppcf128)
443  return FPROUND_PPCF128_F64;
444  }
445 
446  return UNKNOWN_LIBCALL;
447 }
448 
449 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
450 /// UNKNOWN_LIBCALL if there is none.
451 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
452  if (OpVT == MVT::f32) {
453  if (RetVT == MVT::i8)
454  return FPTOSINT_F32_I8;
455  if (RetVT == MVT::i16)
456  return FPTOSINT_F32_I16;
457  if (RetVT == MVT::i32)
458  return FPTOSINT_F32_I32;
459  if (RetVT == MVT::i64)
460  return FPTOSINT_F32_I64;
461  if (RetVT == MVT::i128)
462  return FPTOSINT_F32_I128;
463  } else if (OpVT == MVT::f64) {
464  if (RetVT == MVT::i8)
465  return FPTOSINT_F64_I8;
466  if (RetVT == MVT::i16)
467  return FPTOSINT_F64_I16;
468  if (RetVT == MVT::i32)
469  return FPTOSINT_F64_I32;
470  if (RetVT == MVT::i64)
471  return FPTOSINT_F64_I64;
472  if (RetVT == MVT::i128)
473  return FPTOSINT_F64_I128;
474  } else if (OpVT == MVT::f80) {
475  if (RetVT == MVT::i32)
476  return FPTOSINT_F80_I32;
477  if (RetVT == MVT::i64)
478  return FPTOSINT_F80_I64;
479  if (RetVT == MVT::i128)
480  return FPTOSINT_F80_I128;
481  } else if (OpVT == MVT::f128) {
482  if (RetVT == MVT::i32)
483  return FPTOSINT_F128_I32;
484  if (RetVT == MVT::i64)
485  return FPTOSINT_F128_I64;
486  if (RetVT == MVT::i128)
487  return FPTOSINT_F128_I128;
488  } else if (OpVT == MVT::ppcf128) {
489  if (RetVT == MVT::i32)
490  return FPTOSINT_PPCF128_I32;
491  if (RetVT == MVT::i64)
492  return FPTOSINT_PPCF128_I64;
493  if (RetVT == MVT::i128)
494  return FPTOSINT_PPCF128_I128;
495  }
496  return UNKNOWN_LIBCALL;
497 }
498 
499 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
500 /// UNKNOWN_LIBCALL if there is none.
501 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
502  if (OpVT == MVT::f32) {
503  if (RetVT == MVT::i8)
504  return FPTOUINT_F32_I8;
505  if (RetVT == MVT::i16)
506  return FPTOUINT_F32_I16;
507  if (RetVT == MVT::i32)
508  return FPTOUINT_F32_I32;
509  if (RetVT == MVT::i64)
510  return FPTOUINT_F32_I64;
511  if (RetVT == MVT::i128)
512  return FPTOUINT_F32_I128;
513  } else if (OpVT == MVT::f64) {
514  if (RetVT == MVT::i8)
515  return FPTOUINT_F64_I8;
516  if (RetVT == MVT::i16)
517  return FPTOUINT_F64_I16;
518  if (RetVT == MVT::i32)
519  return FPTOUINT_F64_I32;
520  if (RetVT == MVT::i64)
521  return FPTOUINT_F64_I64;
522  if (RetVT == MVT::i128)
523  return FPTOUINT_F64_I128;
524  } else if (OpVT == MVT::f80) {
525  if (RetVT == MVT::i32)
526  return FPTOUINT_F80_I32;
527  if (RetVT == MVT::i64)
528  return FPTOUINT_F80_I64;
529  if (RetVT == MVT::i128)
530  return FPTOUINT_F80_I128;
531  } else if (OpVT == MVT::f128) {
532  if (RetVT == MVT::i32)
533  return FPTOUINT_F128_I32;
534  if (RetVT == MVT::i64)
535  return FPTOUINT_F128_I64;
536  if (RetVT == MVT::i128)
537  return FPTOUINT_F128_I128;
538  } else if (OpVT == MVT::ppcf128) {
539  if (RetVT == MVT::i32)
540  return FPTOUINT_PPCF128_I32;
541  if (RetVT == MVT::i64)
542  return FPTOUINT_PPCF128_I64;
543  if (RetVT == MVT::i128)
544  return FPTOUINT_PPCF128_I128;
545  }
546  return UNKNOWN_LIBCALL;
547 }
548 
549 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
550 /// UNKNOWN_LIBCALL if there is none.
551 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
552  if (OpVT == MVT::i32) {
553  if (RetVT == MVT::f32)
554  return SINTTOFP_I32_F32;
555  if (RetVT == MVT::f64)
556  return SINTTOFP_I32_F64;
557  if (RetVT == MVT::f80)
558  return SINTTOFP_I32_F80;
559  if (RetVT == MVT::f128)
560  return SINTTOFP_I32_F128;
561  if (RetVT == MVT::ppcf128)
562  return SINTTOFP_I32_PPCF128;
563  } else if (OpVT == MVT::i64) {
564  if (RetVT == MVT::f32)
565  return SINTTOFP_I64_F32;
566  if (RetVT == MVT::f64)
567  return SINTTOFP_I64_F64;
568  if (RetVT == MVT::f80)
569  return SINTTOFP_I64_F80;
570  if (RetVT == MVT::f128)
571  return SINTTOFP_I64_F128;
572  if (RetVT == MVT::ppcf128)
573  return SINTTOFP_I64_PPCF128;
574  } else if (OpVT == MVT::i128) {
575  if (RetVT == MVT::f32)
576  return SINTTOFP_I128_F32;
577  if (RetVT == MVT::f64)
578  return SINTTOFP_I128_F64;
579  if (RetVT == MVT::f80)
580  return SINTTOFP_I128_F80;
581  if (RetVT == MVT::f128)
582  return SINTTOFP_I128_F128;
583  if (RetVT == MVT::ppcf128)
584  return SINTTOFP_I128_PPCF128;
585  }
586  return UNKNOWN_LIBCALL;
587 }
588 
589 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
590 /// UNKNOWN_LIBCALL if there is none.
591 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
592  if (OpVT == MVT::i32) {
593  if (RetVT == MVT::f32)
594  return UINTTOFP_I32_F32;
595  if (RetVT == MVT::f64)
596  return UINTTOFP_I32_F64;
597  if (RetVT == MVT::f80)
598  return UINTTOFP_I32_F80;
599  if (RetVT == MVT::f128)
600  return UINTTOFP_I32_F128;
601  if (RetVT == MVT::ppcf128)
602  return UINTTOFP_I32_PPCF128;
603  } else if (OpVT == MVT::i64) {
604  if (RetVT == MVT::f32)
605  return UINTTOFP_I64_F32;
606  if (RetVT == MVT::f64)
607  return UINTTOFP_I64_F64;
608  if (RetVT == MVT::f80)
609  return UINTTOFP_I64_F80;
610  if (RetVT == MVT::f128)
611  return UINTTOFP_I64_F128;
612  if (RetVT == MVT::ppcf128)
613  return UINTTOFP_I64_PPCF128;
614  } else if (OpVT == MVT::i128) {
615  if (RetVT == MVT::f32)
616  return UINTTOFP_I128_F32;
617  if (RetVT == MVT::f64)
618  return UINTTOFP_I128_F64;
619  if (RetVT == MVT::f80)
620  return UINTTOFP_I128_F80;
621  if (RetVT == MVT::f128)
622  return UINTTOFP_I128_F128;
623  if (RetVT == MVT::ppcf128)
624  return UINTTOFP_I128_PPCF128;
625  }
626  return UNKNOWN_LIBCALL;
627 }
628 
629 /// InitCmpLibcallCCs - Set default comparison libcall CC.
630 ///
631 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
632  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
633  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
634  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
635  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
636  CCs[RTLIB::UNE_F32] = ISD::SETNE;
637  CCs[RTLIB::UNE_F64] = ISD::SETNE;
638  CCs[RTLIB::UNE_F128] = ISD::SETNE;
639  CCs[RTLIB::OGE_F32] = ISD::SETGE;
640  CCs[RTLIB::OGE_F64] = ISD::SETGE;
641  CCs[RTLIB::OGE_F128] = ISD::SETGE;
642  CCs[RTLIB::OLT_F32] = ISD::SETLT;
643  CCs[RTLIB::OLT_F64] = ISD::SETLT;
644  CCs[RTLIB::OLT_F128] = ISD::SETLT;
645  CCs[RTLIB::OLE_F32] = ISD::SETLE;
646  CCs[RTLIB::OLE_F64] = ISD::SETLE;
647  CCs[RTLIB::OLE_F128] = ISD::SETLE;
648  CCs[RTLIB::OGT_F32] = ISD::SETGT;
649  CCs[RTLIB::OGT_F64] = ISD::SETGT;
650  CCs[RTLIB::OGT_F128] = ISD::SETGT;
651  CCs[RTLIB::UO_F32] = ISD::SETNE;
652  CCs[RTLIB::UO_F64] = ISD::SETNE;
653  CCs[RTLIB::UO_F128] = ISD::SETNE;
654  CCs[RTLIB::O_F32] = ISD::SETEQ;
655  CCs[RTLIB::O_F64] = ISD::SETEQ;
656  CCs[RTLIB::O_F128] = ISD::SETEQ;
657 }
658 
659 /// NOTE: The constructor takes ownership of TLOF.
660 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
661  const TargetLoweringObjectFile *tlof)
662  : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) {
663  initActions();
664 
665  // Perform these initializations only once.
666  IsLittleEndian = TD->isLittleEndian();
667  MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
668  MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
669  = MaxStoresPerMemmoveOptSize = 4;
670  UseUnderscoreSetJmp = false;
671  UseUnderscoreLongJmp = false;
672  SelectIsExpensive = false;
673  IntDivIsCheap = false;
674  Pow2DivIsCheap = false;
675  JumpIsExpensive = false;
676  PredictableSelectIsExpensive = false;
677  StackPointerRegisterToSaveRestore = 0;
678  ExceptionPointerRegister = 0;
679  ExceptionSelectorRegister = 0;
680  BooleanContents = UndefinedBooleanContent;
681  BooleanVectorContents = UndefinedBooleanContent;
682  SchedPreferenceInfo = Sched::ILP;
683  JumpBufSize = 0;
684  JumpBufAlignment = 0;
685  MinFunctionAlignment = 0;
686  PrefFunctionAlignment = 0;
687  PrefLoopAlignment = 0;
688  MinStackArgumentAlignment = 1;
689  InsertFencesForAtomic = false;
690  SupportJumpTables = true;
691  MinimumJumpTableEntries = 4;
692 
693  InitLibcallNames(LibcallRoutineNames, TM);
694  InitCmpLibcallCCs(CmpLibcallCCs);
695  InitLibcallCallingConvs(LibcallCallingConvs);
696 }
697 
698 TargetLoweringBase::~TargetLoweringBase() {
699  delete &TLOF;
700 }
701 
702 void TargetLoweringBase::initActions() {
703  // All operations default to being supported.
704  memset(OpActions, 0, sizeof(OpActions));
705  memset(LoadExtActions, 0, sizeof(LoadExtActions));
706  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
707  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
708  memset(CondCodeActions, 0, sizeof(CondCodeActions));
709  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
710  memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
711 
712  // Set default actions for various operations.
713  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
714  // Default all indexed load / store to expand.
715  for (unsigned IM = (unsigned)ISD::PRE_INC;
716  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
717  setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
718  setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
719  }
720 
721  // These operations default to expand.
722  setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
723  setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
724 
725  // These library functions default to expand.
726  setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
727 
728  // These operations default to expand for vector types.
729  if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
730  VT <= MVT::LAST_VECTOR_VALUETYPE)
731  setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
732  }
733 
734  // Most targets ignore the @llvm.prefetch intrinsic.
735  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
736 
737  // ConstantFP nodes default to expand. Targets can either change this to
738  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
739  // to optimize expansions for certain constants.
740  setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
741  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
742  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
743  setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
744  setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
745 
746  // These library functions default to expand.
747  setOperationAction(ISD::FLOG , MVT::f16, Expand);
748  setOperationAction(ISD::FLOG2, MVT::f16, Expand);
749  setOperationAction(ISD::FLOG10, MVT::f16, Expand);
750  setOperationAction(ISD::FEXP , MVT::f16, Expand);
751  setOperationAction(ISD::FEXP2, MVT::f16, Expand);
752  setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
753  setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
754  setOperationAction(ISD::FCEIL, MVT::f16, Expand);
755  setOperationAction(ISD::FRINT, MVT::f16, Expand);
756  setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
757  setOperationAction(ISD::FLOG , MVT::f32, Expand);
758  setOperationAction(ISD::FLOG2, MVT::f32, Expand);
759  setOperationAction(ISD::FLOG10, MVT::f32, Expand);
760  setOperationAction(ISD::FEXP , MVT::f32, Expand);
761  setOperationAction(ISD::FEXP2, MVT::f32, Expand);
762  setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
763  setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
764  setOperationAction(ISD::FCEIL, MVT::f32, Expand);
765  setOperationAction(ISD::FRINT, MVT::f32, Expand);
766  setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
767  setOperationAction(ISD::FLOG , MVT::f64, Expand);
768  setOperationAction(ISD::FLOG2, MVT::f64, Expand);
769  setOperationAction(ISD::FLOG10, MVT::f64, Expand);
770  setOperationAction(ISD::FEXP , MVT::f64, Expand);
771  setOperationAction(ISD::FEXP2, MVT::f64, Expand);
772  setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
773  setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
774  setOperationAction(ISD::FCEIL, MVT::f64, Expand);
775  setOperationAction(ISD::FRINT, MVT::f64, Expand);
776  setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
777  setOperationAction(ISD::FLOG , MVT::f128, Expand);
778  setOperationAction(ISD::FLOG2, MVT::f128, Expand);
779  setOperationAction(ISD::FLOG10, MVT::f128, Expand);
780  setOperationAction(ISD::FEXP , MVT::f128, Expand);
781  setOperationAction(ISD::FEXP2, MVT::f128, Expand);
782  setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
783  setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
784  setOperationAction(ISD::FCEIL, MVT::f128, Expand);
785  setOperationAction(ISD::FRINT, MVT::f128, Expand);
786  setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
787 
788  // Default ISD::TRAP to expand (which turns it into abort).
789  setOperationAction(ISD::TRAP, MVT::Other, Expand);
790 
791  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
792  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
793  //
794  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
795 }
796 
797 MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
798  return MVT::getIntegerVT(getPointerSizeInBits(AS));
799 }
800 
801 unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const {
802  return TD->getPointerSizeInBits(AS);
803 }
804 
805 unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const {
806  assert(Ty->isPointerTy());
807  return getPointerSizeInBits(Ty->getPointerAddressSpace());
808 }
809 
810 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
811  return MVT::getIntegerVT(8*TD->getPointerSize(0));
812 }
813 
814 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const {
815  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
816  if (LHSTy.isVector())
817  return LHSTy;
818  return getScalarShiftAmountTy(LHSTy);
819 }
820 
821 /// canOpTrap - Returns true if the operation can trap for the value type.
822 /// VT must be a legal type.
823 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
824  assert(isTypeLegal(VT));
825  switch (Op) {
826  default:
827  return false;
828  case ISD::FDIV:
829  case ISD::FREM:
830  case ISD::SDIV:
831  case ISD::UDIV:
832  case ISD::SREM:
833  case ISD::UREM:
834  return true;
835  }
836 }
837 
838 
839 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
840  unsigned &NumIntermediates,
841  MVT &RegisterVT,
842  TargetLoweringBase *TLI) {
843  // Figure out the right, legal destination reg to copy into.
844  unsigned NumElts = VT.getVectorNumElements();
845  MVT EltTy = VT.getVectorElementType();
846 
847  unsigned NumVectorRegs = 1;
848 
849  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
850  // could break down into LHS/RHS like LegalizeDAG does.
851  if (!isPowerOf2_32(NumElts)) {
852  NumVectorRegs = NumElts;
853  NumElts = 1;
854  }
855 
856  // Divide the input until we get to a supported size. This will always
857  // end with a scalar if the target doesn't support vectors.
858  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
859  NumElts >>= 1;
860  NumVectorRegs <<= 1;
861  }
862 
863  NumIntermediates = NumVectorRegs;
864 
865  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
866  if (!TLI->isTypeLegal(NewVT))
867  NewVT = EltTy;
868  IntermediateVT = NewVT;
869 
870  unsigned NewVTSize = NewVT.getSizeInBits();
871 
872  // Convert sizes such as i33 to i64.
873  if (!isPowerOf2_32(NewVTSize))
874  NewVTSize = NextPowerOf2(NewVTSize);
875 
876  MVT DestVT = TLI->getRegisterType(NewVT);
877  RegisterVT = DestVT;
878  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
879  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
880 
881  // Otherwise, promotion or legal types use the same number of registers as
882  // the vector decimated to the appropriate level.
883  return NumVectorRegs;
884 }
885 
886 /// isLegalRC - Return true if the value types that can be represented by the
887 /// specified register class are all legal.
888 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
889  for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
890  I != E; ++I) {
891  if (isTypeLegal(*I))
892  return true;
893  }
894  return false;
895 }
896 
897 /// findRepresentativeClass - Return the largest legal super-reg register class
898 /// of the register class for the specified type and its associated "cost".
899 std::pair<const TargetRegisterClass*, uint8_t>
900 TargetLoweringBase::findRepresentativeClass(MVT VT) const {
901  const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
902  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
903  if (!RC)
904  return std::make_pair(RC, 0);
905 
906  // Compute the set of all super-register classes.
907  BitVector SuperRegRC(TRI->getNumRegClasses());
908  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
909  SuperRegRC.setBitsInMask(RCI.getMask());
910 
911  // Find the first legal register class with the largest spill size.
912  const TargetRegisterClass *BestRC = RC;
913  for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
914  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
915  // We want the largest possible spill size.
916  if (SuperRC->getSize() <= BestRC->getSize())
917  continue;
918  if (!isLegalRC(SuperRC))
919  continue;
920  BestRC = SuperRC;
921  }
922  return std::make_pair(BestRC, 1);
923 }
924 
925 /// computeRegisterProperties - Once all of the register classes are added,
926 /// this allows us to compute derived properties we expose.
927 void TargetLoweringBase::computeRegisterProperties() {
928  assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
929  "Too many value types for ValueTypeActions to hold!");
930 
931  // Everything defaults to needing one register.
932  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
933  NumRegistersForVT[i] = 1;
934  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
935  }
936  // ...except isVoid, which doesn't need any registers.
937  NumRegistersForVT[MVT::isVoid] = 0;
938 
939  // Find the largest integer register class.
940  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
941  for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
942  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
943 
944  // Every integer value type larger than this largest register takes twice as
945  // many registers to represent as the previous ValueType.
946  for (unsigned ExpandedReg = LargestIntReg + 1;
947  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
948  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
949  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
950  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
951  ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
952  TypeExpandInteger);
953  }
954 
955  // Inspect all of the ValueType's smaller than the largest integer
956  // register to see which ones need promotion.
957  unsigned LegalIntReg = LargestIntReg;
958  for (unsigned IntReg = LargestIntReg - 1;
959  IntReg >= (unsigned)MVT::i1; --IntReg) {
960  MVT IVT = (MVT::SimpleValueType)IntReg;
961  if (isTypeLegal(IVT)) {
962  LegalIntReg = IntReg;
963  } else {
964  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
965  (const MVT::SimpleValueType)LegalIntReg;
966  ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
967  }
968  }
969 
970  // ppcf128 type is really two f64's.
971  if (!isTypeLegal(MVT::ppcf128)) {
972  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
973  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
974  TransformToType[MVT::ppcf128] = MVT::f64;
975  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
976  }
977 
978  // Decide how to handle f128. If the target does not have native f128 support,
979  // expand it to i128 and we will be generating soft float library calls.
980  if (!isTypeLegal(MVT::f128)) {
981  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
982  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
983  TransformToType[MVT::f128] = MVT::i128;
984  ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
985  }
986 
987  // Decide how to handle f64. If the target does not have native f64 support,
988  // expand it to i64 and we will be generating soft float library calls.
989  if (!isTypeLegal(MVT::f64)) {
990  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
991  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
992  TransformToType[MVT::f64] = MVT::i64;
993  ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
994  }
995 
996  // Decide how to handle f32. If the target does not have native support for
997  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
998  if (!isTypeLegal(MVT::f32)) {
999  if (isTypeLegal(MVT::f64)) {
1000  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
1001  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
1002  TransformToType[MVT::f32] = MVT::f64;
1003  ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
1004  } else {
1005  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1006  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1007  TransformToType[MVT::f32] = MVT::i32;
1008  ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1009  }
1010  }
1011 
1012  // Loop over all of the vector value types to see which need transformations.
1013  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1014  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1015  MVT VT = (MVT::SimpleValueType)i;
1016  if (isTypeLegal(VT)) continue;
1017 
1018  // Determine if there is a legal wider type. If so, we should promote to
1019  // that wider vector type.
1020  MVT EltVT = VT.getVectorElementType();
1021  unsigned NElts = VT.getVectorNumElements();
1022  if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) {
1023  bool IsLegalWiderType = false;
1024  // First try to promote the elements of integer vectors. If no legal
1025  // promotion was found, fallback to the widen-vector method.
1026  for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1027  MVT SVT = (MVT::SimpleValueType)nVT;
1028  // Promote vectors of integers to vectors with the same number
1029  // of elements, with a wider element type.
1030  if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
1031  && SVT.getVectorNumElements() == NElts &&
1032  isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
1033  TransformToType[i] = SVT;
1034  RegisterTypeForVT[i] = SVT;
1035  NumRegistersForVT[i] = 1;
1036  ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1037  IsLegalWiderType = true;
1038  break;
1039  }
1040  }
1041 
1042  if (IsLegalWiderType) continue;
1043 
1044  // Try to widen the vector.
1045  for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1046  MVT SVT = (MVT::SimpleValueType)nVT;
1047  if (SVT.getVectorElementType() == EltVT &&
1048  SVT.getVectorNumElements() > NElts &&
1049  isTypeLegal(SVT)) {
1050  TransformToType[i] = SVT;
1051  RegisterTypeForVT[i] = SVT;
1052  NumRegistersForVT[i] = 1;
1053  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1054  IsLegalWiderType = true;
1055  break;
1056  }
1057  }
1058  if (IsLegalWiderType) continue;
1059  }
1060 
1061  MVT IntermediateVT;
1062  MVT RegisterVT;
1063  unsigned NumIntermediates;
1064  NumRegistersForVT[i] =
1065  getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
1066  RegisterVT, this);
1067  RegisterTypeForVT[i] = RegisterVT;
1068 
1069  MVT NVT = VT.getPow2VectorType();
1070  if (NVT == VT) {
1071  // Type is already a power of 2. The default action is to split.
1072  TransformToType[i] = MVT::Other;
1073  unsigned NumElts = VT.getVectorNumElements();
1074  ValueTypeActions.setTypeAction(VT,
1075  NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
1076  } else {
1077  TransformToType[i] = NVT;
1078  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1079  }
1080  }
1081 
1082  // Determine the 'representative' register class for each value type.
1083  // An representative register class is the largest (meaning one which is
1084  // not a sub-register class / subreg register class) legal register class for
1085  // a group of value types. For example, on i386, i8, i16, and i32
1086  // representative would be GR32; while on x86_64 it's GR64.
1087  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1088  const TargetRegisterClass* RRC;
1089  uint8_t Cost;
1090  tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
1091  RepRegClassForVT[i] = RRC;
1092  RepRegClassCostForVT[i] = Cost;
1093  }
1094 }
1095 
1096 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
1097  assert(!VT.isVector() && "No default SetCC type for vectors!");
1098  return getPointerTy(0).SimpleTy;
1099 }
1100 
1101 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1102  return MVT::i32; // return the default value
1103 }
1104 
1105 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1106 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1107 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1108 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1109 ///
1110 /// This method returns the number of registers needed, and the VT for each
1111 /// register. It also returns the VT and quantity of the intermediate values
1112 /// before they are promoted/expanded.
1113 ///
1114 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1115  EVT &IntermediateVT,
1116  unsigned &NumIntermediates,
1117  MVT &RegisterVT) const {
1118  unsigned NumElts = VT.getVectorNumElements();
1119 
1120  // If there is a wider vector type with the same element type as this one,
1121  // or a promoted vector type that has the same number of elements which
1122  // are wider, then we should convert to that legal vector type.
1123  // This handles things like <2 x float> -> <4 x float> and
1124  // <4 x i1> -> <4 x i32>.
1125  LegalizeTypeAction TA = getTypeAction(Context, VT);
1126  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1127  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1128  if (isTypeLegal(RegisterEVT)) {
1129  IntermediateVT = RegisterEVT;
1130  RegisterVT = RegisterEVT.getSimpleVT();
1131  NumIntermediates = 1;
1132  return 1;
1133  }
1134  }
1135 
1136  // Figure out the right, legal destination reg to copy into.
1137  EVT EltTy = VT.getVectorElementType();
1138 
1139  unsigned NumVectorRegs = 1;
1140 
1141  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1142  // could break down into LHS/RHS like LegalizeDAG does.
1143  if (!isPowerOf2_32(NumElts)) {
1144  NumVectorRegs = NumElts;
1145  NumElts = 1;
1146  }
1147 
1148  // Divide the input until we get to a supported size. This will always
1149  // end with a scalar if the target doesn't support vectors.
1150  while (NumElts > 1 && !isTypeLegal(
1151  EVT::getVectorVT(Context, EltTy, NumElts))) {
1152  NumElts >>= 1;
1153  NumVectorRegs <<= 1;
1154  }
1155 
1156  NumIntermediates = NumVectorRegs;
1157 
1158  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1159  if (!isTypeLegal(NewVT))
1160  NewVT = EltTy;
1161  IntermediateVT = NewVT;
1162 
1163  MVT DestVT = getRegisterType(Context, NewVT);
1164  RegisterVT = DestVT;
1165  unsigned NewVTSize = NewVT.getSizeInBits();
1166 
1167  // Convert sizes such as i33 to i64.
1168  if (!isPowerOf2_32(NewVTSize))
1169  NewVTSize = NextPowerOf2(NewVTSize);
1170 
1171  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1172  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1173 
1174  // Otherwise, promotion or legal types use the same number of registers as
1175  // the vector decimated to the appropriate level.
1176  return NumVectorRegs;
1177 }
1178 
1179 /// Get the EVTs and ArgFlags collections that represent the legalized return
1180 /// type of the given function. This does not require a DAG or a return value,
1181 /// and is suitable for use before any DAGs for the function are constructed.
1182 /// TODO: Move this out of TargetLowering.cpp.
1183 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
1184  SmallVectorImpl<ISD::OutputArg> &Outs,
1185  const TargetLowering &TLI) {
1186  SmallVector<EVT, 4> ValueVTs;
1187  ComputeValueVTs(TLI, ReturnType, ValueVTs);
1188  unsigned NumValues = ValueVTs.size();
1189  if (NumValues == 0) return;
1190 
1191  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1192  EVT VT = ValueVTs[j];
1193  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1194 
1195  if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1196  ExtendKind = ISD::SIGN_EXTEND;
1197  else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1198  ExtendKind = ISD::ZERO_EXTEND;
1199 
1200  // FIXME: C calling convention requires the return type to be promoted to
1201  // at least 32-bit. But this is not necessary for non-C calling
1202  // conventions. The frontend should mark functions whose return values
1203  // require promoting with signext or zeroext attributes.
1204  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1205  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1206  if (VT.bitsLT(MinVT))
1207  VT = MinVT;
1208  }
1209 
1210  unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1211  MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1212 
1213  // 'inreg' on function refers to return value
1214  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1215  if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1216  Flags.setInReg();
1217 
1218  // Propagate extension type if any
1219  if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1220  Flags.setSExt();
1221  else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1222  Flags.setZExt();
1223 
1224  for (unsigned i = 0; i < NumParts; ++i)
1225  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
1226  }
1227 }
1228 
1229 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1230 /// function arguments in the caller parameter area. This is the actual
1231 /// alignment, not its logarithm.
1232 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const {
1233  return TD->getCallFrameTypeAlignment(Ty);
1234 }
1235 
1236 //===----------------------------------------------------------------------===//
1237 // TargetTransformInfo Helpers
1238 //===----------------------------------------------------------------------===//
1239 
1240 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1241  enum InstructionOpcodes {
1242 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1243 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1244 #include "llvm/IR/Instruction.def"
1245  };
1246  switch (static_cast<InstructionOpcodes>(Opcode)) {
1247  case Ret: return 0;
1248  case Br: return 0;
1249  case Switch: return 0;
1250  case IndirectBr: return 0;
1251  case Invoke: return 0;
1252  case Resume: return 0;
1253  case Unreachable: return 0;
1254  case Add: return ISD::ADD;
1255  case FAdd: return ISD::FADD;
1256  case Sub: return ISD::SUB;
1257  case FSub: return ISD::FSUB;
1258  case Mul: return ISD::MUL;
1259  case FMul: return ISD::FMUL;
1260  case UDiv: return ISD::UDIV;
1261  case SDiv: return ISD::UDIV;
1262  case FDiv: return ISD::FDIV;
1263  case URem: return ISD::UREM;
1264  case SRem: return ISD::SREM;
1265  case FRem: return ISD::FREM;
1266  case Shl: return ISD::SHL;
1267  case LShr: return ISD::SRL;
1268  case AShr: return ISD::SRA;
1269  case And: return ISD::AND;
1270  case Or: return ISD::OR;
1271  case Xor: return ISD::XOR;
1272  case Alloca: return 0;
1273  case Load: return ISD::LOAD;
1274  case Store: return ISD::STORE;
1275  case GetElementPtr: return 0;
1276  case Fence: return 0;
1277  case AtomicCmpXchg: return 0;
1278  case AtomicRMW: return 0;
1279  case Trunc: return ISD::TRUNCATE;
1280  case ZExt: return ISD::ZERO_EXTEND;
1281  case SExt: return ISD::SIGN_EXTEND;
1282  case FPToUI: return ISD::FP_TO_UINT;
1283  case FPToSI: return ISD::FP_TO_SINT;
1284  case UIToFP: return ISD::UINT_TO_FP;
1285  case SIToFP: return ISD::SINT_TO_FP;
1286  case FPTrunc: return ISD::FP_ROUND;
1287  case FPExt: return ISD::FP_EXTEND;
1288  case PtrToInt: return ISD::BITCAST;
1289  case IntToPtr: return ISD::BITCAST;
1290  case BitCast: return ISD::BITCAST;
1291  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1292  case ICmp: return ISD::SETCC;
1293  case FCmp: return ISD::SETCC;
1294  case PHI: return 0;
1295  case Call: return 0;
1296  case Select: return ISD::SELECT;
1297  case UserOp1: return 0;
1298  case UserOp2: return 0;
1299  case VAArg: return 0;
1300  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1301  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1302  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1303  case ExtractValue: return ISD::MERGE_VALUES;
1304  case InsertValue: return ISD::MERGE_VALUES;
1305  case LandingPad: return 0;
1306  }
1307 
1308  llvm_unreachable("Unknown instruction type encountered!");
1309 }
1310 
1311 std::pair<unsigned, MVT>
1312 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const {
1313  LLVMContext &C = Ty->getContext();
1314  EVT MTy = getValueType(Ty);
1315 
1316  unsigned Cost = 1;
1317  // We keep legalizing the type until we find a legal kind. We assume that
1318  // the only operation that costs anything is the split. After splitting
1319  // we need to handle two types.
1320  while (true) {
1321  LegalizeKind LK = getTypeConversion(C, MTy);
1322 
1323  if (LK.first == TypeLegal)
1324  return std::make_pair(Cost, MTy.getSimpleVT());
1325 
1326  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1327  Cost *= 2;
1328 
1329  // Keep legalizing the type.
1330  MTy = LK.second;
1331  }
1332 }
1333 
1334 //===----------------------------------------------------------------------===//
1335 // Loop Strength Reduction hooks
1336 //===----------------------------------------------------------------------===//
1337 
1338 /// isLegalAddressingMode - Return true if the addressing mode represented
1339 /// by AM is legal for this target, for a load/store of the specified type.
1340 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM,
1341  Type *Ty) const {
1342  // The default implementation of this implements a conservative RISCy, r+r and
1343  // r+i addr mode.
1344 
1345  // Allows a sign-extended 16-bit immediate field.
1346  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1347  return false;
1348 
1349  // No global is ever allowed as a base.
1350  if (AM.BaseGV)
1351  return false;
1352 
1353  // Only support r+r,
1354  switch (AM.Scale) {
1355  case 0: // "r+i" or just "i", depending on HasBaseReg.
1356  break;
1357  case 1:
1358  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1359  return false;
1360  // Otherwise we have r+r or r+i.
1361  break;
1362  case 2:
1363  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1364  return false;
1365  // Allow 2*r as r+r.
1366  break;
1367  }
1368 
1369  return true;
1370 }
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: ValueTypes.h:481
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition: SmallVector.h:236
llvm::TargetRegisterClass::vt_end
vt_iterator vt_end() const
Definition: TargetRegisterInfo.h:117
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=0, uint64_t StartingOffset=0)
Definition: CodeGen/Analysis.cpp:74
InitLibcallCallingConvs
static void InitLibcallCallingConvs(CallingConv::ID *CCs)
Definition: TargetLoweringBase.cpp:403
llvm::TargetLoweringBase::getTypeAction
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Definition: TargetLowering.h:319
llvm::Attribute::SExt
Sign extended before/after call.
Definition: Attributes.h:97
llvm::TargetLoweringBase::getNumRegisters
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Definition: TargetLowering.h:646
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: ValueTypes.h:500
llvm::Attribute::InReg
Force argument to be passed in register.
Definition: Attributes.h:76
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:145
llvm::MSP430ISD::RRC
Y = RRC X, rotate right via carry.
Definition: MSP430ISelLowering.h:37
llvm::DataLayout::getPointerSize
unsigned getPointerSize(unsigned AS=0) const
Definition: DataLayout.h:261
llvm::TargetLoweringBase::findRepresentativeClass
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(MVT VT) const
Definition: TargetLoweringBase.cpp:900
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: ValueTypes.h:359
llvm::TargetLoweringBase::getPointerTypeSizeInBits
unsigned getPointerTypeSizeInBits(Type *Ty) const
Definition: TargetLoweringBase.cpp:805
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: Type.cpp:218
llvm::TargetLoweringBase::LegalizeKind
std::pair< LegalizeTypeAction, EVT > LegalizeKind
Definition: TargetLowering.h:102
llvm::AttributeSet::hasAttribute
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:818
llvm::TargetLoweringBase::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const
Definition: TargetLoweringBase.cpp:810
llvm::RTLIB::getFPROUND
Libcall getFPROUND(EVT OpVT, EVT RetVT)
Definition: TargetLoweringBase.cpp:427
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
Definition: ValueTypes.h:735
llvm::TargetLoweringBase::getValueType
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
Definition: TargetLowering.h:582
llvm::RTLIB::getUINTTOFP
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
Definition: TargetLoweringBase.cpp:591
llvm::TargetLoweringBase::getPointerSizeInBits
unsigned getPointerSizeInBits(uint32_t AS=0) const
Definition: TargetLoweringBase.cpp:801
llvm::EVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:661
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy) const
Definition: TargetLoweringBase.cpp:814
llvm::TargetLoweringBase::canOpTrap
virtual bool canOpTrap(unsigned Op, EVT VT) const
Definition: TargetLoweringBase.cpp:823
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:553
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:103
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Definition: TargetRegisterInfo.h:559
llvm::TargetLoweringBase::getSetCCResultType
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const
Definition: TargetLoweringBase.cpp:1096
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: ValueTypes.h:161
llvm::MVT::getScalarType
MVT getScalarType() const
Definition: ValueTypes.h:259
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Definition: TargetLowering.h:980
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:797
ExtractElement
static ConstantInt * ExtractElement(Constant *V, Constant *Idx)
Definition: InstCombineCompares.cpp:40
llvm::CallingConv::ID
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
llvm::EVT::isInteger
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:656
llvm::TargetLoweringBase::InstructionOpcodeToISD
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Definition: TargetLoweringBase.cpp:1240
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Definition: ValueTypes.h:762
llvm::Type::getContext
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
llvm::array_lengthof
size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:250
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:176
llvm::DataLayout::isLittleEndian
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:195
llvm::TargetLoweringBase::isLegalRC
bool isLegalRC(const TargetRegisterClass *RC) const
Definition: TargetLoweringBase.cpp:888
llvm::GetReturnInfo
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI)
Definition: TargetLoweringBase.cpp:1183
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:285
InitCmpLibcallCCs
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
Definition: TargetLoweringBase.cpp:631
llvm::MVT::isInteger
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:182
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: ValueTypes.h:311
llvm::ISD::FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:222
llvm::APIntOps::Or
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1845
llvm::APIntOps::Xor
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
Definition: APInt.h:1850
llvm::RTLIB::getFPTOSINT
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
Definition: TargetLoweringBase.cpp:451
llvm::ISD::TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:586
llvm::Attribute::ZExt
Zero extended before/after call.
Definition: Attributes.h:110
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:612
llvm::ISD::DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:589
llvm::TargetLoweringBase::getByValTypeAlignment
virtual unsigned getByValTypeAlignment(Type *Ty) const
Definition: TargetLoweringBase.cpp:1232
InitLibcallNames
static void InitLibcallNames(const char **Names, const TargetMachine &TM)
Definition: TargetLoweringBase.cpp:38
llvm::TargetLoweringBase::getVectorTypeBreakdown
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Definition: TargetLoweringBase.cpp:1114
llvm::TargetLoweringBase::MaxStoresPerMemmove
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Definition: TargetLowering.h:1674
llvm::ISD::FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:411
llvm::Type::isPointerTy
bool isPointerTy() const
Definition: Type.h:220
llvm::NextPowerOf2
uint64_t NextPowerOf2(uint64_t A)
Definition: MathExtras.h:546
getVectorTypeBreakdownMVT
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
Definition: TargetLoweringBase.cpp:839
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:616
llvm::RTLIB::getFPEXT
Libcall getFPEXT(EVT OpVT, EVT RetVT)
Definition: TargetLoweringBase.cpp:411
llvm::TargetLoweringBase::initActions
void initActions()
Initialize all of the actions to default values.
Definition: TargetLoweringBase.cpp:702
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:840
llvm::TargetLoweringBase::shouldSplitVectorElementType
virtual bool shouldSplitVectorElementType(EVT) const
Definition: TargetLowering.h:179
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Definition: TargetLowering.h:1009
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:357
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:360
llvm::TargetMachine::getTargetTriple
const StringRef getTargetTriple() const
Definition: Target/TargetMachine.h:97
llvm::APIntOps::And
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1840
llvm::TargetLoweringBase::getCmpLibcallReturnType
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Definition: TargetLoweringBase.cpp:1101
llvm::DataLayout::getCallFrameTypeAlignment
unsigned getCallFrameTypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:592
llvm::RTLIB::getFPTOUINT
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
Definition: TargetLoweringBase.cpp:501
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:295
llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction
void setTypeAction(MVT VT, LegalizeTypeAction Action)
Definition: TargetLowering.h:305
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:779
I
#define I(x, y, z)
Definition: MD5.cpp:54
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Definition: DataLayout.h:271
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:140
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
Definition: TargetLowering.h:1658
llvm::TargetLoweringBase::getTypeConversion
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Definition: TargetLowering.h:1473
llvm::RTLIB::getSINTTOFP
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
Definition: TargetLoweringBase.cpp:551
llvm::TargetLoweringBase::getTypeToTransformTo
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
Definition: TargetLowering.h:332
llvm::MVT::getPow2VectorType
MVT getPow2VectorType() const
Definition: ValueTypes.h:248
llvm::TargetLoweringBase::isLegalAddressingMode
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
Definition: TargetLoweringBase.cpp:1340
llvm::isPowerOf2_32
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:354
llvm::TargetRegisterClass::vt_begin
vt_iterator vt_begin() const
Definition: TargetRegisterInfo.h:113
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:1641
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: ValueTypes.h:263
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:363
llvm::tie
tier< T1, T2 > tie(T1 &f, T2 &s)
Definition: STLExtras.h:216
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
Definition: BitVector.h:497
TD
INITIALIZE_PASS(GlobalMerge,"global-merge","Global Merge", false, false) bool GlobalMerge const DataLayout * TD
Definition: GlobalMerge.cpp:146
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Definition: ValueTypes.h:749
llvm::TargetLoweringBase::getTypeLegalizationCost
std::pair< unsigned, MVT > getTypeLegalizationCost(Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
Definition: TargetLoweringBase.cpp:1312
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Definition: TargetLowering.h:1023
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: ValueTypes.h:771

Generated on Tue Mar 18 2014 10:39:01 for LLVM by Doxygen1.8.6
Copyright © 2003-2013 University of Illinois at Urbana-Champaign. All Rights Reserved.