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Thumb2InstrInfo.h
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1 //===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef THUMB2INSTRUCTIONINFO_H
15 #define THUMB2INSTRUCTIONINFO_H
16 
17 #include "ARM.h"
18 #include "ARMBaseInstrInfo.h"
19 #include "Thumb2RegisterInfo.h"
20 
21 namespace llvm {
22 class ARMSubtarget;
23 class ScheduleHazardRecognizer;
24 
27 public:
28  explicit Thumb2InstrInfo(const ARMSubtarget &STI);
29 
30  /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
31  void getNoopForMachoTarget(MCInst &NopInst) const;
32 
33  // Return the non-pre/post incrementing version of 'Opc'. Return 0
34  // if there is not such an opcode.
35  unsigned getUnindexedOpcode(unsigned Opc) const;
36 
38  MachineBasicBlock *NewDest) const;
39 
41  MachineBasicBlock::iterator MBBI) const;
42 
45  unsigned DestReg, unsigned SrcReg,
46  bool KillSrc) const;
47 
50  unsigned SrcReg, bool isKill, int FrameIndex,
51  const TargetRegisterClass *RC,
52  const TargetRegisterInfo *TRI) const;
53 
56  unsigned DestReg, int FrameIndex,
57  const TargetRegisterClass *RC,
58  const TargetRegisterInfo *TRI) const;
59 
60  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
61  /// such, whenever a client has an instance of instruction info, it should
62  /// always be able to get register info as well (through this method).
63  ///
64  const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
65 };
66 
67 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
68 /// to llvm::getInstrPredicate except it returns AL for conditional branch
69 /// instructions which are "predicated", but are not in IT blocks.
70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
71 
72 
73 }
74 
75 #endif // THUMB2INSTRUCTIONINFO_H
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg)
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
bundle_iterator< MachineInstr, instr_iterator > iterator
const Thumb2RegisterInfo & getRegisterInfo() const
Thumb2InstrInfo(const ARMSubtarget &STI)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
#define I(x, y, z)
Definition: MD5.cpp:54
void getNoopForMachoTarget(MCInst &NopInst) const
getNoopForMachoTarget - Return the noop instruction to use for a noop.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
unsigned getUnindexedOpcode(unsigned Opc) const