33 class MipsAssemblerOptions {
35 MipsAssemblerOptions() : aTReg(1), reorder(
true), macro(
true) {}
37 unsigned getATRegNum() {
return aTReg; }
38 bool setATReg(
unsigned Reg);
40 bool isReorder() {
return reorder; }
41 void setReorder() { reorder =
true; }
42 void setNoreorder() { reorder =
false; }
44 bool isMacro() {
return macro; }
45 void setMacro() { macro =
true; }
46 void setNomacro() { macro =
false; }
65 MipsAssemblerOptions Options;
66 bool hasConsumedDollar;
68 #define GET_ASSEMBLER_HEADER
69 #include "MipsGenAsmMatcher.inc"
71 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
74 bool MatchingInlineAsm);
76 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc);
82 bool ParseDirective(
AsmToken DirectiveID);
84 MipsAsmParser::OperandMatchResultTy
87 MipsAsmParser::OperandMatchResultTy
90 MipsAsmParser::OperandMatchResultTy
94 MipsAsmParser::OperandMatchResultTy
100 MipsAsmParser::OperandMatchResultTy
103 MipsAsmParser::OperandMatchResultTy
106 MipsAsmParser::OperandMatchResultTy
109 MipsAsmParser::OperandMatchResultTy
112 MipsAsmParser::OperandMatchResultTy
115 MipsAsmParser::OperandMatchResultTy
118 MipsAsmParser::OperandMatchResultTy
121 MipsAsmParser::OperandMatchResultTy
124 MipsAsmParser::OperandMatchResultTy
127 MipsAsmParser::OperandMatchResultTy
130 MipsAsmParser::OperandMatchResultTy
133 MipsAsmParser::OperandMatchResultTy
136 MipsAsmParser::OperandMatchResultTy
139 MipsAsmParser::OperandMatchResultTy
142 MipsAsmParser::OperandMatchResultTy
145 MipsAsmParser::OperandMatchResultTy
148 MipsAsmParser::OperandMatchResultTy
151 MipsAsmParser::OperandMatchResultTy
154 MipsAsmParser::OperandMatchResultTy
157 MipsAsmParser::OperandMatchResultTy
160 MipsAsmParser::OperandMatchResultTy
169 int tryParseRegister(
bool is64BitReg);
174 bool needsExpansion(
MCInst &Inst);
180 void expandLoadAddressImm(
MCInst &Inst,
SMLoc IDLoc,
182 void expandLoadAddressReg(
MCInst &Inst,
SMLoc IDLoc,
187 bool reportParseError(
StringRef ErrorMsg);
189 bool parseMemOffset(
const MCExpr *&Res,
bool isParenExpr);
190 bool parseRelocOperand(
const MCExpr *&Res);
194 bool isEvaluated(
const MCExpr *Expr);
195 bool parseDirectiveSet();
196 bool parseDirectiveMipsHackStocg();
197 bool parseDirectiveMipsHackELFFlags();
199 bool parseSetAtDirective();
200 bool parseSetNoAtDirective();
201 bool parseSetMacroDirective();
202 bool parseSetNoMacroDirective();
203 bool parseSetReorderDirective();
204 bool parseSetNoReorderDirective();
206 bool parseSetAssignment();
208 bool parseDirectiveWord(
unsigned Size,
SMLoc L);
209 bool parseDirectiveGpWord();
213 bool isMips64()
const {
214 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
217 bool isFP64()
const {
218 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
221 bool isN64()
const {
return STI.getFeatureBits() & Mips::FeatureN64; }
227 int matchRegisterByNumber(
unsigned RegNum,
unsigned RegClass);
239 int regKindToRegClass(
int RegKind);
241 unsigned getReg(
int RC,
int RegNo);
251 bool validateMSAIndex(
int Val,
int RegKind);
257 hasConsumedDollar(
false) {
259 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
263 MCAsmLexer &getLexer()
const {
return Parser.getLexer(); }
337 SMLoc StartLoc, EndLoc;
340 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
341 assert(N == 1 &&
"Invalid number of operands!");
345 void addPtrRegOperands(
MCInst &Inst,
unsigned N)
const {
346 assert(N == 1 &&
"Invalid number of operands!");
354 else if (
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
360 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
361 assert(N == 1 &&
"Invalid number of operands!");
362 const MCExpr *Expr = getImm();
366 void addMemOperands(
MCInst &Inst,
unsigned N)
const {
367 assert(N == 2 &&
"Invalid number of operands!");
371 const MCExpr *Expr = getMemOff();
375 bool isReg()
const {
return Kind == k_Register; }
376 bool isImm()
const {
return Kind == k_Immediate; }
377 bool isToken()
const {
return Kind == k_Token; }
378 bool isMem()
const {
return Kind == k_Memory; }
379 bool isPtrReg()
const {
return Kind == k_PtrReg; }
380 bool isInvNum()
const {
return Kind == k_Immediate; }
381 bool isLSAImm()
const {
return Kind == k_LSAImm; }
384 assert(
Kind == k_Token &&
"Invalid access!");
389 assert((
Kind == k_Register) &&
"Invalid access!");
393 unsigned getPtrReg()
const {
394 assert((
Kind == k_PtrReg) &&
"Invalid access!");
399 assert((
Kind == k_Register ||
Kind == k_PtrReg) &&
"Invalid access!");
403 const MCExpr *getImm()
const {
404 assert((
Kind == k_Immediate ||
Kind == k_LSAImm) &&
"Invalid access!");
408 unsigned getMemBase()
const {
409 assert((
Kind == k_Memory) &&
"Invalid access!");
413 const MCExpr *getMemOff()
const {
414 assert((
Kind == k_Memory) &&
"Invalid access!");
419 MipsOperand *Op =
new MipsOperand(k_Token);
420 Op->Tok.Data = Str.
data();
421 Op->Tok.Length = Str.
size();
427 static MipsOperand *CreateReg(
unsigned RegNum,
SMLoc S,
SMLoc E) {
428 MipsOperand *Op =
new MipsOperand(k_Register);
429 Op->Reg.RegNum = RegNum;
435 static MipsOperand *CreatePtrReg(
unsigned RegNum,
SMLoc S,
SMLoc E) {
436 MipsOperand *Op =
new MipsOperand(k_PtrReg);
437 Op->Reg.RegNum = RegNum;
444 MipsOperand *Op =
new MipsOperand(k_Immediate);
452 MipsOperand *Op =
new MipsOperand(k_LSAImm);
459 static MipsOperand *CreateMem(
unsigned Base,
const MCExpr *Off,
461 MipsOperand *Op =
new MipsOperand(k_Memory);
469 bool isGPR32Asm()
const {
470 return Kind == k_Register &&
Reg.Kind == Kind_GPR32;
472 void addRegAsmOperands(
MCInst &Inst,
unsigned N)
const {
476 bool isGPR64Asm()
const {
477 return Kind == k_Register &&
Reg.Kind == Kind_GPR64;
480 bool isHWRegsAsm()
const {
481 assert((
Kind == k_Register) &&
"Invalid access!");
482 return Reg.Kind == Kind_HWRegs;
485 bool isCCRAsm()
const {
486 assert((
Kind == k_Register) &&
"Invalid access!");
487 return Reg.Kind == Kind_CCRRegs;
490 bool isAFGR64Asm()
const {
491 return Kind == k_Register &&
Reg.Kind == Kind_AFGR64Regs;
494 bool isFGR64Asm()
const {
495 return Kind == k_Register &&
Reg.Kind == Kind_FGR64Regs;
498 bool isFGR32Asm()
const {
499 return (
Kind == k_Register) &&
Reg.Kind == Kind_FGR32Regs;
502 bool isFGRH32Asm()
const {
503 return (
Kind == k_Register) &&
Reg.Kind == Kind_FGRH32Regs;
506 bool isFCCRegsAsm()
const {
507 return (
Kind == k_Register) &&
Reg.Kind == Kind_FCCRegs;
510 bool isACC64DSPAsm()
const {
511 return Kind == k_Register &&
Reg.Kind == Kind_ACC64DSP;
514 bool isLO32DSPAsm()
const {
515 return Kind == k_Register &&
Reg.Kind == Kind_LO32DSP;
518 bool isHI32DSPAsm()
const {
519 return Kind == k_Register &&
Reg.Kind == Kind_HI32DSP;
522 bool isCOP2Asm()
const {
return Kind == k_Register &&
Reg.Kind == Kind_COP2; }
524 bool isMSA128BAsm()
const {
525 return Kind == k_Register &&
Reg.Kind == Kind_MSA128BRegs;
528 bool isMSA128HAsm()
const {
529 return Kind == k_Register &&
Reg.Kind == Kind_MSA128HRegs;
532 bool isMSA128WAsm()
const {
533 return Kind == k_Register &&
Reg.Kind == Kind_MSA128WRegs;
536 bool isMSA128DAsm()
const {
537 return Kind == k_Register &&
Reg.Kind == Kind_MSA128DRegs;
540 bool isMSA128CRAsm()
const {
541 return Kind == k_Register &&
Reg.Kind == Kind_MSA128CtrlRegs;
545 SMLoc getStartLoc()
const {
return StartLoc; }
547 SMLoc getEndLoc()
const {
return EndLoc; }
562 bool MipsAsmParser::processInstruction(
MCInst &Inst,
SMLoc IDLoc,
588 int MemOffset = Op.
getImm();
589 if (MemOffset < -32768 || MemOffset > 32767) {
591 expandMemInst(Inst, IDLoc, Instructions, MCID.
mayLoad(),
true);
601 expandMemInst(Inst, IDLoc, Instructions, MCID.
mayLoad(),
false);
604 }
else if (!isEvaluated(Expr)) {
605 expandMemInst(Inst, IDLoc, Instructions, MCID.
mayLoad(),
false);
613 if (needsExpansion(Inst))
614 expandInstruction(Inst, IDLoc, Instructions);
621 bool MipsAsmParser::needsExpansion(
MCInst &Inst) {
624 case Mips::LoadImm32Reg:
625 case Mips::LoadAddr32Imm:
626 case Mips::LoadAddr32Reg:
633 void MipsAsmParser::expandInstruction(
MCInst &Inst,
SMLoc IDLoc,
636 case Mips::LoadImm32Reg:
637 return expandLoadImm(Inst, IDLoc, Instructions);
638 case Mips::LoadAddr32Imm:
639 return expandLoadAddressImm(Inst, IDLoc, Instructions);
640 case Mips::LoadAddr32Reg:
641 return expandLoadAddressReg(Inst, IDLoc, Instructions);
645 void MipsAsmParser::expandLoadImm(
MCInst &Inst,
SMLoc IDLoc,
649 assert(ImmOp.
isImm() &&
"expected immediate operand kind");
651 assert(RegOp.isReg() &&
"expected register operand kind");
653 int ImmValue = ImmOp.
getImm();
655 if (0 <= ImmValue && ImmValue <= 65535) {
663 }
else if (ImmValue < 0 && ImmValue >= -32768) {
690 MipsAsmParser::expandLoadAddressReg(
MCInst &Inst,
SMLoc IDLoc,
694 assert(ImmOp.
isImm() &&
"expected immediate operand kind");
696 assert(SrcRegOp.isReg() &&
"expected register operand kind");
698 assert(DstRegOp.isReg() &&
"expected register operand kind");
699 int ImmValue = ImmOp.
getImm();
700 if (-32768 <= ImmValue && ImmValue <= 65535) {
733 MipsAsmParser::expandLoadAddressImm(
MCInst &Inst,
SMLoc IDLoc,
737 assert(ImmOp.
isImm() &&
"expected immediate operand kind");
739 assert(RegOp.isReg() &&
"expected register operand kind");
740 int ImmValue = ImmOp.
getImm();
741 if (-32768 <= ImmValue && ImmValue <= 65535) {
766 void MipsAsmParser::expandMemInst(
MCInst &Inst,
SMLoc IDLoc,
768 bool isLoad,
bool isImmOpnd) {
771 unsigned ImmOffset, HiOffset, LoOffset;
774 unsigned AtRegNum =
getReg(
775 (isMips64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
777 assert(Inst.
getOperand(0).
isReg() &&
"expected register operand kind");
780 assert(Inst.
getOperand(1).
isReg() &&
"expected register operand kind");
784 assert(Inst.
getOperand(2).
isImm() &&
"expected immediate operand kind");
786 LoOffset = ImmOffset & 0x0000ffff;
787 HiOffset = (ImmOffset & 0xffff0000) >> 16;
789 if (LoOffset & 0x8000)
798 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
811 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset,
"hi");
840 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset,
"lo");
848 bool MipsAsmParser::MatchAndEmitInstruction(
849 SMLoc IDLoc,
unsigned &Opcode,
851 unsigned &ErrorInfo,
bool MatchingInlineAsm) {
854 unsigned MatchResult =
855 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
857 switch (MatchResult) {
860 case Match_Success: {
861 if (processInstruction(Inst, IDLoc, Instructions))
863 for (
unsigned i = 0; i < Instructions.
size(); i++)
867 case Match_MissingFeature:
868 Error(IDLoc,
"instruction requires a CPU feature not currently enabled");
870 case Match_InvalidOperand: {
871 SMLoc ErrorLoc = IDLoc;
872 if (ErrorInfo != ~0U) {
873 if (ErrorInfo >= Operands.
size())
874 return Error(IDLoc,
"too few operands for instruction");
876 ErrorLoc = ((MipsOperand *)Operands[ErrorInfo])->getStartLoc();
877 if (ErrorLoc ==
SMLoc())
881 return Error(ErrorLoc,
"invalid operand for instruction");
883 case Match_MnemonicFail:
884 return Error(IDLoc,
"invalid instruction");
932 if (isMips64() && 8 <= CC && CC <= 11)
935 if (CC == -1 && isMips64())
949 int MipsAsmParser::matchFPURegisterName(
StringRef Name) {
951 if (Name[0] ==
'f') {
963 int MipsAsmParser::matchFCCRegisterName(
StringRef Name) {
977 int MipsAsmParser::matchACRegisterName(
StringRef Name) {
991 int MipsAsmParser::matchMSA128RegisterName(
StringRef Name) {
1003 int MipsAsmParser::matchMSA128CtrlRegisterName(
StringRef Name) {
1009 .
Case(
"msaaccess", 2)
1011 .
Case(
"msamodify", 4)
1012 .
Case(
"msarequest", 5)
1014 .
Case(
"msaunmap", 7)
1020 int MipsAsmParser::matchRegisterName(
StringRef Name,
bool is64BitReg) {
1023 CC = matchCPURegisterName(Name);
1025 return matchRegisterByNumber(CC, is64BitReg ? Mips::GPR64RegClassID
1026 : Mips::GPR32RegClassID);
1027 CC = matchFPURegisterName(Name);
1030 return matchRegisterByNumber(CC, isFP64() ? Mips::FGR64RegClassID
1031 : Mips::FGR32RegClassID);
1032 return matchMSA128RegisterName(Name);
1035 int MipsAsmParser::regKindToRegClass(
int RegKind) {
1038 case MipsOperand::Kind_GPR32:
1039 return Mips::GPR32RegClassID;
1040 case MipsOperand::Kind_GPR64:
1041 return Mips::GPR64RegClassID;
1042 case MipsOperand::Kind_HWRegs:
1043 return Mips::HWRegsRegClassID;
1044 case MipsOperand::Kind_FGR32Regs:
1045 return Mips::FGR32RegClassID;
1046 case MipsOperand::Kind_FGRH32Regs:
1047 return Mips::FGRH32RegClassID;
1048 case MipsOperand::Kind_FGR64Regs:
1049 return Mips::FGR64RegClassID;
1050 case MipsOperand::Kind_AFGR64Regs:
1051 return Mips::AFGR64RegClassID;
1052 case MipsOperand::Kind_CCRRegs:
1053 return Mips::CCRRegClassID;
1054 case MipsOperand::Kind_ACC64DSP:
1055 return Mips::ACC64DSPRegClassID;
1056 case MipsOperand::Kind_FCCRegs:
1057 return Mips::FCCRegClassID;
1058 case MipsOperand::Kind_MSA128BRegs:
1059 return Mips::MSA128BRegClassID;
1060 case MipsOperand::Kind_MSA128HRegs:
1061 return Mips::MSA128HRegClassID;
1062 case MipsOperand::Kind_MSA128WRegs:
1063 return Mips::MSA128WRegClassID;
1064 case MipsOperand::Kind_MSA128DRegs:
1065 return Mips::MSA128DRegClassID;
1066 case MipsOperand::Kind_MSA128CtrlRegs:
1067 return Mips::MSACtrlRegClassID;
1073 bool MipsAssemblerOptions::setATReg(
unsigned Reg) {
1081 int MipsAsmParser::getATReg() {
return Options.getATRegNum(); }
1084 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1087 int MipsAsmParser::matchRegisterByNumber(
unsigned RegNum,
unsigned RegClass) {
1089 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs())
1092 return getReg(RegClass, RegNum);
1095 int MipsAsmParser::tryParseRegister(
bool is64BitReg) {
1096 const AsmToken &Tok = Parser.getTok();
1101 RegNum = matchRegisterName(lowerCase, is64BitReg);
1103 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.
getIntVal()),
1104 is64BitReg ? Mips::GPR64RegClassID
1105 : Mips::GPR32RegClassID);
1109 bool MipsAsmParser::tryParseRegisterOperand(
1112 SMLoc S = Parser.getTok().getLoc();
1115 RegNo = tryParseRegister(is64BitReg);
1120 MipsOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1130 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1131 if (ResTy == MatchOperand_Success)
1136 if (ResTy == MatchOperand_ParseFail)
1139 switch (getLexer().getKind()) {
1141 Error(Parser.getTok().getLoc(),
"unexpected token in operand");
1145 SMLoc S = Parser.getTok().getLoc();
1148 if (!tryParseRegisterOperand(Operands, isMips64())) {
1151 Operands.
push_back(MipsOperand::CreateToken(
"(", S));
1157 if (tryParseRegisterOperand(Operands, isMips64()))
1163 S = Parser.getTok().getLoc();
1164 Operands.
push_back(MipsOperand::CreateToken(
")", S));
1171 if (Parser.parseIdentifier(Identifier))
1175 MCSymbol *Sym = getContext().GetOrCreateSymbol(
"$" + Identifier);
1180 Operands.
push_back(MipsOperand::CreateImm(Res, S, E));
1187 if (hasConsumedDollar) {
1188 hasConsumedDollar =
false;
1189 SMLoc S = Parser.getTok().getLoc();
1191 if (Parser.parseIdentifier(Identifier))
1195 MCSymbol *Sym = getContext().GetOrCreateSymbol(
"$" + Identifier);
1200 Operands.
push_back(MipsOperand::CreateImm(Res, S, E));
1205 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
1215 SMLoc S = Parser.getTok().getLoc();
1216 if (getParser().parseExpression(IdVal))
1219 Operands.
push_back(MipsOperand::CreateImm(IdVal, S, E));
1225 SMLoc S = Parser.getTok().getLoc();
1226 if (parseRelocOperand(IdVal))
1231 Operands.
push_back(MipsOperand::CreateImm(IdVal, S, E));
1238 const MCExpr *MipsAsmParser::evaluateRelocExpr(
const MCExpr *Expr,
1242 if (
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1244 if (RelocStr ==
"lo") {
1245 short Val = MCE->getValue();
1247 }
else if (RelocStr ==
"hi") {
1248 int Val = MCE->getValue();
1249 int LoSign = Val & 0x8000;
1250 Val = (Val & 0xffff0000) >> 16;
1270 if (
const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1271 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1272 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1277 if (
const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1278 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1286 bool MipsAsmParser::isEvaluated(
const MCExpr *Expr) {
1294 if (
const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1295 if (!isEvaluated(BE->getLHS()))
1297 return isEvaluated(BE->getRHS());
1300 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1307 bool MipsAsmParser::parseRelocOperand(
const MCExpr *&Res) {
1309 const AsmToken &Tok = Parser.getTok();
1325 const AsmToken &nextTok = Parser.getTok();
1336 if (getParser().parseParenExpression(IdVal, EndLoc))
1345 Res = evaluateRelocExpr(IdVal, Str);
1349 bool MipsAsmParser::ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
1351 StartLoc = Parser.getTok().getLoc();
1352 RegNo = tryParseRegister(isMips64());
1353 EndLoc = Parser.getTok().getLoc();
1354 return (RegNo == (
unsigned)-1);
1357 bool MipsAsmParser::parseMemOffset(
const MCExpr *&Res,
bool isParenExpr) {
1364 switch (getLexer().getKind()) {
1373 Result = getParser().parseParenExpression(Res, S);
1375 Result = (getParser().parseExpression(Res));
1380 Result = parseRelocOperand(Res);
1385 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1390 bool isParenExpr =
false;
1391 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1393 S = Parser.getTok().getLoc();
1401 if (parseMemOffset(IdVal, isParenExpr))
1402 return MatchOperand_ParseFail;
1404 const AsmToken &Tok = Parser.getTok();
1406 MipsOperand *Mnemonic =
static_cast<MipsOperand *
>(Operands[0]);
1407 if (Mnemonic->getToken() ==
"la") {
1410 Operands.
push_back(MipsOperand::CreateImm(IdVal, S, E));
1411 return MatchOperand_Success;
1418 Operands.
push_back(MipsOperand::CreateMem(
1419 isMips64() ? Mips::ZERO_64 : Mips::ZERO, IdVal, S, E));
1420 return MatchOperand_Success;
1422 Error(Parser.getTok().getLoc(),
"'(' expected");
1423 return MatchOperand_ParseFail;
1429 Res = parseRegs(Operands, isMips64() ? (
int)MipsOperand::Kind_GPR64
1430 : (
int)MipsOperand::Kind_GPR32);
1431 if (Res != MatchOperand_Success)
1435 Error(Parser.getTok().getLoc(),
"')' expected");
1436 return MatchOperand_ParseFail;
1447 MipsOperand *op =
static_cast<MipsOperand *
>(Operands.
back());
1448 int RegNo = op->getReg();
1452 if (
const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1454 if (IdVal->EvaluateAsAbsolute(Imm))
1461 Operands.
push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1463 return MatchOperand_Success;
1472 SMLoc S = Parser.getTok().getLoc();
1478 Reg = matchRegisterByNumber(Parser.getTok().getIntVal(),
1479 regKindToRegClass(RegKind));
1483 if ((Reg = matchCPURegisterName(Parser.getTok().getString().lower())) == -1)
1485 Reg =
getReg(regKindToRegClass(RegKind), Reg);
1490 MipsOperand *Op = MipsOperand::CreatePtrReg(Reg, S, Parser.getTok().getLoc());
1491 Op->setRegKind((MipsOperand::RegisterKind)RegKind);
1497 MipsAsmParser::OperandMatchResultTy
1499 MipsOperand::RegisterKind RegKind =
1500 isN64() ? MipsOperand::Kind_GPR64 : MipsOperand::Kind_GPR32;
1503 if (!parsePtrReg(Operands, RegKind))
1504 return MatchOperand_NoMatch;
1508 return MatchOperand_NoMatch;
1510 Operands.
push_back(MipsOperand::CreateToken(
"(", getLexer().getLoc()));
1514 if (!parsePtrReg(Operands, RegKind))
1515 return MatchOperand_NoMatch;
1519 return MatchOperand_NoMatch;
1521 Operands.
push_back(MipsOperand::CreateToken(
")", getLexer().getLoc()));
1524 return MatchOperand_Success;
1527 MipsAsmParser::OperandMatchResultTy
1532 if (searchSymbolAlias(Operands, Kind))
1533 return MatchOperand_Success;
1534 return MatchOperand_NoMatch;
1536 SMLoc S = Parser.getTok().getLoc();
1539 return MatchOperand_NoMatch;
1540 if (!hasConsumedDollar) {
1542 hasConsumedDollar =
true;
1546 std::string RegName = Parser.getTok().getString().lower();
1549 case MipsOperand::Kind_GPR32:
1550 case MipsOperand::Kind_GPR64:
1551 RegNum = matchCPURegisterName(RegName);
1553 case MipsOperand::Kind_AFGR64Regs:
1554 case MipsOperand::Kind_FGR64Regs:
1555 case MipsOperand::Kind_FGR32Regs:
1556 case MipsOperand::Kind_FGRH32Regs:
1557 RegNum = matchFPURegisterName(RegName);
1558 if (RegKind == MipsOperand::Kind_AFGR64Regs)
1560 else if (RegKind == MipsOperand::Kind_FGRH32Regs && !isFP64())
1561 if (RegNum != -1 && RegNum % 2 != 0)
1562 Warning(S,
"Float register should be even.");
1564 case MipsOperand::Kind_FCCRegs:
1565 RegNum = matchFCCRegisterName(RegName);
1567 case MipsOperand::Kind_ACC64DSP:
1568 RegNum = matchACRegisterName(RegName);
1575 return MatchOperand_NoMatch;
1577 int RegVal =
getReg(regKindToRegClass(Kind), RegNum);
1579 return MatchOperand_NoMatch;
1582 MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1583 Op->setRegKind(Kind);
1585 hasConsumedDollar =
false;
1587 return MatchOperand_Success;
1589 unsigned RegNum = Parser.getTok().getIntVal();
1590 if (Kind == MipsOperand::Kind_HWRegs) {
1592 return MatchOperand_NoMatch;
1596 int Reg = matchRegisterByNumber(RegNum, regKindToRegClass(Kind));
1598 return MatchOperand_NoMatch;
1599 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1600 Op->setRegKind(Kind);
1602 hasConsumedDollar =
false;
1604 if ((RegKind == MipsOperand::Kind_GPR32) &&
1607 Operands.
push_back(MipsOperand::CreateToken(
"(", getLexer().getLoc()));
1609 if (parseRegs(Operands, RegKind) != MatchOperand_Success)
1610 return MatchOperand_NoMatch;
1612 return MatchOperand_NoMatch;
1613 Operands.
push_back(MipsOperand::CreateToken(
")", getLexer().getLoc()));
1616 return MatchOperand_Success;
1618 return MatchOperand_NoMatch;
1621 bool MipsAsmParser::validateMSAIndex(
int Val,
int RegKind) {
1630 case MipsOperand::Kind_MSA128BRegs:
1632 case MipsOperand::Kind_MSA128HRegs:
1634 case MipsOperand::Kind_MSA128WRegs:
1636 case MipsOperand::Kind_MSA128DRegs:
1641 MipsAsmParser::OperandMatchResultTy
1645 SMLoc S = Parser.getTok().getLoc();
1646 std::string RegName;
1649 return MatchOperand_NoMatch;
1653 return MatchOperand_ParseFail;
1654 case MipsOperand::Kind_MSA128BRegs:
1655 case MipsOperand::Kind_MSA128HRegs:
1656 case MipsOperand::Kind_MSA128WRegs:
1657 case MipsOperand::Kind_MSA128DRegs:
1663 RegName = Parser.getTok().getString().lower();
1665 return MatchOperand_ParseFail;
1667 int RegNum = matchMSA128RegisterName(RegName);
1669 if (RegNum < 0 || RegNum > 31)
1670 return MatchOperand_ParseFail;
1672 int RegVal =
getReg(regKindToRegClass(Kind), RegNum);
1674 return MatchOperand_ParseFail;
1676 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1677 Op->setRegKind(Kind);
1690 return MatchOperand_Success;
1692 MipsOperand *Mnemonic =
static_cast<MipsOperand *
>(Operands[0]);
1694 Operands.
push_back(MipsOperand::CreateToken(
"[", Parser.getTok().getLoc()));
1700 SMLoc VIdx = Parser.getTok().getLoc();
1705 unsigned RegNum = Parser.getTok().getIntVal();
1706 int Reg = matchRegisterByNumber(
1707 RegNum, regKindToRegClass(MipsOperand::Kind_GPR32));
1709 Error(VIdx,
"invalid general purpose register");
1710 return MatchOperand_ParseFail;
1713 RegOp = MipsOperand::CreateReg(Reg, VIdx, Parser.getTok().getLoc());
1716 std::string RegName = Parser.getTok().getString().lower();
1718 RegNum = matchCPURegisterName(RegName);
1720 Error(VIdx,
"general purpose register expected");
1721 return MatchOperand_ParseFail;
1723 RegNum =
getReg(regKindToRegClass(MipsOperand::Kind_GPR32), RegNum);
1724 RegOp = MipsOperand::CreateReg(RegNum, VIdx, Parser.getTok().getLoc());
1726 return MatchOperand_ParseFail;
1728 RegOp->setRegKind(MipsOperand::Kind_GPR32);
1733 return MatchOperand_ParseFail;
1735 Operands.
push_back(MipsOperand::CreateToken(
"]", Parser.getTok().getLoc()));
1738 return MatchOperand_Success;
1742 SMLoc VIdx = Parser.getTok().getLoc();
1745 if (getParser().parseExpression(ImmVal))
1746 return MatchOperand_ParseFail;
1749 if (!expr || !validateMSAIndex((
int)expr->
getValue(),
Kind)) {
1750 Error(VIdx,
"invalid immediate value");
1751 return MatchOperand_ParseFail;
1754 SMLoc E = Parser.getTok().getEndLoc();
1757 return MatchOperand_ParseFail;
1760 Mnemonic->getToken() ==
"insve.b" || Mnemonic->getToken() ==
"insve.h" ||
1761 Mnemonic->getToken() ==
"insve.w" || Mnemonic->getToken() ==
"insve.d";
1764 if (insve && Operands.
size() > 6) {
1766 Error(VIdx,
"immediate value must be 0");
1767 return MatchOperand_ParseFail;
1769 Operands.
push_back(MipsOperand::CreateToken(
"0", VIdx));
1771 Operands.
push_back(MipsOperand::CreateImm(expr, VIdx, E));
1773 Operands.
push_back(MipsOperand::CreateToken(
"]", Parser.getTok().getLoc()));
1777 return MatchOperand_Success;
1780 MipsAsmParser::OperandMatchResultTy
1785 if (Kind != MipsOperand::Kind_MSA128CtrlRegs)
1786 return MatchOperand_NoMatch;
1789 return MatchOperand_ParseFail;
1791 SMLoc S = Parser.getTok().getLoc();
1797 RegNum = matchMSA128CtrlRegisterName(Parser.getTok().getString().lower());
1799 RegNum = Parser.getTok().getIntVal();
1801 return MatchOperand_ParseFail;
1803 if (RegNum < 0 || RegNum > 7)
1804 return MatchOperand_ParseFail;
1806 int RegVal =
getReg(regKindToRegClass(Kind), RegNum);
1808 return MatchOperand_ParseFail;
1810 MipsOperand *RegOp =
1811 MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1812 RegOp->setRegKind(MipsOperand::Kind_MSA128CtrlRegs);
1816 return MatchOperand_Success;
1819 MipsAsmParser::OperandMatchResultTy
1823 return MatchOperand_NoMatch;
1824 return parseRegs(Operands, (
int)MipsOperand::Kind_GPR64);
1827 MipsAsmParser::OperandMatchResultTy
1829 return parseRegs(Operands, (
int)MipsOperand::Kind_GPR32);
1832 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseAFGR64Regs(
1836 return MatchOperand_NoMatch;
1837 return parseRegs(Operands, (
int)MipsOperand::Kind_AFGR64Regs);
1840 MipsAsmParser::OperandMatchResultTy
1843 return MatchOperand_NoMatch;
1844 return parseRegs(Operands, (
int)MipsOperand::Kind_FGR64Regs);
1847 MipsAsmParser::OperandMatchResultTy
1849 return parseRegs(Operands, (
int)MipsOperand::Kind_FGR32Regs);
1852 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseFGRH32Regs(
1854 return parseRegs(Operands, (
int)MipsOperand::Kind_FGRH32Regs);
1857 MipsAsmParser::OperandMatchResultTy
1859 return parseRegs(Operands, (
int)MipsOperand::Kind_FCCRegs);
1862 MipsAsmParser::OperandMatchResultTy
1864 return parseRegs(Operands, (
int)MipsOperand::Kind_ACC64DSP);
1867 MipsAsmParser::OperandMatchResultTy
1871 return MatchOperand_NoMatch;
1873 SMLoc S = Parser.getTok().getLoc();
1876 const AsmToken &Tok = Parser.getTok();
1879 return MatchOperand_NoMatch;
1882 return MatchOperand_NoMatch;
1888 return MatchOperand_NoMatch;
1890 unsigned Reg = matchRegisterByNumber(IntVal, Mips::LO32DSPRegClassID);
1892 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1893 Op->setRegKind(MipsOperand::Kind_LO32DSP);
1897 return MatchOperand_Success;
1900 MipsAsmParser::OperandMatchResultTy
1904 return MatchOperand_NoMatch;
1906 SMLoc S = Parser.getTok().getLoc();
1909 const AsmToken &Tok = Parser.getTok();
1912 return MatchOperand_NoMatch;
1915 return MatchOperand_NoMatch;
1921 return MatchOperand_NoMatch;
1923 unsigned Reg = matchRegisterByNumber(IntVal, Mips::HI32DSPRegClassID);
1925 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1926 Op->setRegKind(MipsOperand::Kind_HI32DSP);
1930 return MatchOperand_Success;
1933 MipsAsmParser::OperandMatchResultTy
1937 return MatchOperand_NoMatch;
1939 SMLoc S = Parser.getTok().getLoc();
1942 const AsmToken &Tok = Parser.getTok();
1945 return MatchOperand_NoMatch;
1949 unsigned Reg = matchRegisterByNumber(IntVal, Mips::COP2RegClassID);
1951 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1952 Op->setRegKind(MipsOperand::Kind_COP2);
1956 return MatchOperand_Success;
1959 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128BRegs(
1961 return parseMSARegs(Operands, (
int)MipsOperand::Kind_MSA128BRegs);
1964 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128HRegs(
1966 return parseMSARegs(Operands, (
int)MipsOperand::Kind_MSA128HRegs);
1969 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128WRegs(
1971 return parseMSARegs(Operands, (
int)MipsOperand::Kind_MSA128WRegs);
1974 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128DRegs(
1976 return parseMSARegs(Operands, (
int)MipsOperand::Kind_MSA128DRegs);
1979 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128CtrlRegs(
1981 return parseMSACtrlRegs(Operands, (
int)MipsOperand::Kind_MSA128CtrlRegs);
1984 bool MipsAsmParser::searchSymbolAlias(
1987 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1989 SMLoc S = Parser.getTok().getLoc();
2003 RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
2004 isMips64() ? Mips::GPR64RegClassID
2005 : Mips::GPR32RegClassID);
2009 case MipsOperand::Kind_AFGR64Regs:
2010 case MipsOperand::Kind_FGR64Regs:
2011 RegNum = matchFPURegisterName(DefSymbol.
substr(1));
2013 case MipsOperand::Kind_FGR32Regs:
2014 RegNum = matchFPURegisterName(DefSymbol.
substr(1));
2016 case MipsOperand::Kind_GPR64:
2017 case MipsOperand::Kind_GPR32:
2019 RegNum = matchCPURegisterName(DefSymbol.
substr(1));
2023 RegNum =
getReg(regKindToRegClass(Kind), RegNum);
2028 MipsOperand::CreateReg(RegNum, S, Parser.getTok().getLoc());
2029 op->setRegKind(Kind);
2038 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc());
2046 MipsAsmParser::OperandMatchResultTy
2048 return parseRegs(Operands, (
int)MipsOperand::Kind_HWRegs);
2051 MipsAsmParser::OperandMatchResultTy
2053 return parseRegs(Operands, (
int)MipsOperand::Kind_CCRRegs);
2056 MipsAsmParser::OperandMatchResultTy
2061 return MatchOperand_NoMatch;
2062 SMLoc S = Parser.getTok().getLoc();
2063 if (getParser().parseExpression(IdVal))
2064 return MatchOperand_ParseFail;
2066 assert(MCE &&
"Unexpected MCExpr type.");
2069 Operands.
push_back(MipsOperand::CreateImm(
2071 return MatchOperand_Success;
2074 MipsAsmParser::OperandMatchResultTy
2076 switch (getLexer().getKind()) {
2078 return MatchOperand_NoMatch;
2087 SMLoc S = Parser.getTok().getLoc();
2089 if (getParser().parseExpression(Expr))
2090 return MatchOperand_ParseFail;
2093 if (!Expr->EvaluateAsAbsolute(Val)) {
2094 Error(S,
"expected immediate value");
2095 return MatchOperand_ParseFail;
2103 if (Val < 1 || Val > 4) {
2104 Error(S,
"immediate not in range (1..4)");
2105 return MatchOperand_ParseFail;
2108 Operands.
push_back(MipsOperand::CreateLSAImm(Expr, S,
2109 Parser.getTok().getLoc()));
2110 return MatchOperand_Success;
2139 bool MipsAsmParser::ParseInstruction(
2143 if (!mnemonicIsValid(Name, 0)) {
2144 Parser.eatToEndOfStatement();
2145 return Error(NameLoc,
"Unknown instruction");
2148 Operands.
push_back(MipsOperand::CreateToken(Name, NameLoc));
2153 if (ParseOperand(Operands, Name)) {
2154 SMLoc Loc = getLexer().getLoc();
2155 Parser.eatToEndOfStatement();
2156 return Error(Loc,
"unexpected token in argument list");
2162 if (ParseOperand(Operands, Name)) {
2163 SMLoc Loc = getLexer().getLoc();
2164 Parser.eatToEndOfStatement();
2165 return Error(Loc,
"unexpected token in argument list");
2170 SMLoc Loc = getLexer().getLoc();
2171 Parser.eatToEndOfStatement();
2172 return Error(Loc,
"unexpected token in argument list");
2178 bool MipsAsmParser::reportParseError(
StringRef ErrorMsg) {
2179 SMLoc Loc = getLexer().getLoc();
2180 Parser.eatToEndOfStatement();
2181 return Error(Loc, ErrorMsg);
2184 bool MipsAsmParser::parseSetNoAtDirective() {
2187 Options.setATReg(0);
2192 reportParseError(
"unexpected token in statement");
2199 bool MipsAsmParser::parseSetAtDirective() {
2205 Options.setATReg(1);
2211 reportParseError(
"unexpected token in statement");
2215 const AsmToken &Reg = Parser.getTok();
2221 reportParseError(
"unexpected token in statement");
2225 if (AtRegNo < 1 || AtRegNo > 31) {
2226 reportParseError(
"unexpected token in statement");
2230 if (!Options.setATReg(AtRegNo)) {
2231 reportParseError(
"unexpected token in statement");
2237 reportParseError(
"unexpected token in statement");
2243 reportParseError(
"unexpected token in statement");
2248 bool MipsAsmParser::parseSetReorderDirective() {
2252 reportParseError(
"unexpected token in statement");
2255 Options.setReorder();
2260 bool MipsAsmParser::parseSetNoReorderDirective() {
2264 reportParseError(
"unexpected token in statement");
2267 Options.setNoreorder();
2272 bool MipsAsmParser::parseSetMacroDirective() {
2276 reportParseError(
"unexpected token in statement");
2284 bool MipsAsmParser::parseSetNoMacroDirective() {
2288 reportParseError(
"`noreorder' must be set before `nomacro'");
2291 if (Options.isReorder()) {
2292 reportParseError(
"`noreorder' must be set before `nomacro'");
2295 Options.setNomacro();
2300 bool MipsAsmParser::parseSetAssignment() {
2304 if (Parser.parseIdentifier(Name))
2305 reportParseError(
"expected identifier after .set");
2308 return reportParseError(
"unexpected token in .set directive");
2313 SMLoc DollarLoc = getLexer().getLoc();
2317 if (DollarLoc.
getPointer() + 1 != getTok().getLoc().getPointer())
2321 getTok().getEndLoc().getPointer() - DollarLoc.
getPointer());
2322 Symbol = getContext().GetOrCreateSymbol(Res);
2326 }
else if (Parser.parseExpression(Value))
2327 return reportParseError(
"expected valid expression after comma");
2330 MCSymbol *Sym = getContext().LookupSymbol(Name);
2332 return reportParseError(
"symbol already defined");
2333 Sym = getContext().GetOrCreateSymbol(Name);
2339 bool MipsAsmParser::parseDirectiveSet() {
2342 const AsmToken &Tok = Parser.getTok();
2345 return parseSetNoAtDirective();
2347 return parseSetAtDirective();
2348 }
else if (Tok.
getString() ==
"reorder") {
2349 return parseSetReorderDirective();
2350 }
else if (Tok.
getString() ==
"noreorder") {
2351 return parseSetNoReorderDirective();
2352 }
else if (Tok.
getString() ==
"macro") {
2353 return parseSetMacroDirective();
2354 }
else if (Tok.
getString() ==
"nomacro") {
2355 return parseSetNoMacroDirective();
2356 }
else if (Tok.
getString() ==
"nomips16") {
2358 Parser.eatToEndOfStatement();
2360 }
else if (Tok.
getString() ==
"nomicromips") {
2362 Parser.eatToEndOfStatement();
2366 parseSetAssignment();
2373 bool MipsAsmParser::parseDirectiveMipsHackStocg() {
2377 reportParseError(
"expected identifier");
2379 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2381 return TokError(
"unexpected token");
2386 return TokError(
"unexpected token");
2388 getTargetStreamer().emitMipsHackSTOCG(Sym, Flags);
2392 bool MipsAsmParser::parseDirectiveMipsHackELFFlags() {
2395 return TokError(
"unexpected token");
2397 getTargetStreamer().emitMipsHackELFFlags(Flags);
2403 bool MipsAsmParser::parseDirectiveWord(
unsigned Size,
SMLoc L) {
2407 if (getParser().parseExpression(Value))
2410 getParser().getStreamer().EmitValue(Value, Size);
2417 return Error(L,
"unexpected token in directive");
2428 bool MipsAsmParser::parseDirectiveGpWord() {
2432 if (getParser().parseExpression(Value))
2434 getParser().getStreamer().EmitGPRel32Value(Value);
2437 return Error(getLexer().getLoc(),
"unexpected token in directive");
2442 bool MipsAsmParser::ParseDirective(
AsmToken DirectiveID) {
2446 if (IDVal ==
".ent") {
2452 if (IDVal ==
".end") {
2458 if (IDVal ==
".frame") {
2464 if (IDVal ==
".set") {
2465 return parseDirectiveSet();
2468 if (IDVal ==
".fmask") {
2474 if (IDVal ==
".mask") {
2480 if (IDVal ==
".gpword") {
2482 parseDirectiveGpWord();
2486 if (IDVal ==
".word") {
2487 parseDirectiveWord(4, DirectiveID.
getLoc());
2491 if (IDVal ==
".mips_hack_stocg")
2492 return parseDirectiveMipsHackStocg();
2494 if (IDVal ==
".mips_hack_elf_flags")
2495 return parseDirectiveMipsHackELFFlags();
2507 #define GET_REGISTER_MATCHER
2508 #define GET_MATCHER_IMPLEMENTATION
2509 #include "MipsGenAsmMatcher.inc"
static bool isReg(const MCInst &MI, unsigned OpNo)
void push_back(const T &Elt)
const MCSymbol & getSymbol() const
const char * getPointer() const
size_t size() const
size - Get the string size.
static MCOperand CreateReg(unsigned Reg)
static const MCConstantExpr * Create(int64_t Value, MCContext &Ctx)
MCTargetAsmParser - Generic interface to target specific assembly parsers.
enable_if_c<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
bool mayStore() const
Return true if this instruction could possibly modify memory. Instructions with this flag set are not...
StringRef getString() const
static MCOperand CreateExpr(const MCExpr *Val)
StringRef substr(size_t Start, size_t N=npos) const
virtual const AsmToken & Lex()=0
std::string str() const
str - Get the contents as an std::string.
bool isNot(TokenKind K) const
virtual void EmitInstruction(const MCInst &Inst)=0
static const MCInstrDesc & getInstDesc(unsigned Opcode)
StringSwitch & Case(const char(&S)[N], const T &Value)
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
#define llvm_unreachable(msg)
static MCSymbolRefExpr::VariantKind getVariantKind(unsigned Flags)
const MCExpr * getVariableValue() const
getVariableValue() - Get the value for variable symbols.
AsmToken - Target independent representation for an assembler token.
This file implements a class to represent arbitrary precision integral constant values and operations...
uint8_t OperandType
OperandType - Information about the type of the operand.
unsigned getReg() const
getReg - Returns the register number.
const char * data() const
MCUnaryExpr - Unary assembler expressions.
int64_t getIntVal() const
virtual void eatToEndOfStatement()=0
static const MCSymbolRefExpr * Create(const MCSymbol *Symbol, MCContext &Ctx)
const MCExpr * getExpr() const
A switch()-like statement whose cases are string literals.
static const MCBinaryExpr * Create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCUnaryExpr * Create(Opcode Op, const MCExpr *Expr, MCContext &Ctx)
enable_if_c< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
MCBinaryExpr - Binary assembler expressions.
void setOpcode(unsigned Op)
bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
StringRef drop_front(size_t N=1) const
bool mayLoad() const
Return true if this instruction could possibly read memory. Instructions with this flag set are not n...
bool is(TokenKind K) const
void setVariableValue(const MCExpr *Value)
R Default(const T &Value) const
unsigned getOpcode() const
Class for arbitrary precision integers.
static SMLoc getFromPointer(const char *Ptr)
StringRef getIdentifier() const
StringRef getName() const
getName - Get the symbol name.
static MCOperand CreateImm(int64_t Val)
bool hasDelaySlot() const
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
virtual bool parseAbsoluteExpression(int64_t &Res)=0
References to labels and assigned expressions.
static bool isMem(const MachineInstr *MI, unsigned Op)
const MCInstrDesc MipsInsts[]
bool isVariable() const
isVariable - Check if this is a variable symbol.
VariantKind getKind() const
char front() const
front - Get the first character in the string.
LLVM Value Representation.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction. Note that variadic (isVari...
const MCOperandInfo * OpInfo
void addOperand(const MCOperand &Op)
virtual bool parseIdentifier(StringRef &Res)=0
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
Represents a location in source code.
static RegisterPass< NVPTXAllocaHoisting > X("alloca-hoisting","Hoisting alloca instructions in non-entry ""blocks to the entry block")
std::string lower() const
const MCOperand & getOperand(unsigned i) const
void LLVMInitializeMipsAsmParser()