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MachineBasicBlock.cpp
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1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Collect the sequence of machine instructions for a basic block.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/Assembly/Writer.h"
26 #include "llvm/IR/BasicBlock.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/Support/Debug.h"
36 #include <algorithm>
37 using namespace llvm;
38 
39 MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb)
40  : BB(bb), Number(-1), xParent(&mf), Alignment(0), IsLandingPad(false),
41  AddressTaken(false), CachedMCSymbol(NULL) {
42  Insts.Parent = this;
43 }
44 
45 MachineBasicBlock::~MachineBasicBlock() {
47 }
48 
49 /// getSymbol - Return the MCSymbol for this basic block.
50 ///
52  if (!CachedMCSymbol) {
53  const MachineFunction *MF = getParent();
54  MCContext &Ctx = MF->getContext();
55  const char *Prefix = Ctx.getAsmInfo()->getPrivateGlobalPrefix();
56  CachedMCSymbol = Ctx.GetOrCreateSymbol(Twine(Prefix) + "BB" +
57  Twine(MF->getFunctionNumber()) +
58  "_" + Twine(getNumber()));
59  }
60 
61  return CachedMCSymbol;
62 }
63 
64 
66  MBB.print(OS);
67  return OS;
68 }
69 
70 /// addNodeToList (MBB) - When an MBB is added to an MF, we need to update the
71 /// parent pointer of the MBB, the MBB numbering, and any instructions in the
72 /// MBB to be on the right operand list for registers.
73 ///
74 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
75 /// gets the next available unique MBB number. If it is removed from a
76 /// MachineFunction, it goes back to being #-1.
78  MachineFunction &MF = *N->getParent();
79  N->Number = MF.addToMBBNumbering(N);
80 
81  // Make sure the instructions have their operands in the reginfo lists.
82  MachineRegisterInfo &RegInfo = MF.getRegInfo();
84  I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
85  I->AddRegOperandsToUseLists(RegInfo);
86 
88 }
89 
91  N->getParent()->removeFromMBBNumbering(N->Number);
92  N->Number = -1;
94 }
95 
96 
97 /// addNodeToList (MI) - When we add an instruction to a basic block
98 /// list, we update its parent pointer and add its operands from reg use/def
99 /// lists if appropriate.
101  assert(N->getParent() == 0 && "machine instruction already in a basic block");
102  N->setParent(Parent);
103 
104  // Add the instruction's register operands to their corresponding
105  // use/def lists.
106  MachineFunction *MF = Parent->getParent();
107  N->AddRegOperandsToUseLists(MF->getRegInfo());
108 
110 }
111 
112 /// removeNodeFromList (MI) - When we remove an instruction from a basic block
113 /// list, we update its parent pointer and remove its operands from reg use/def
114 /// lists if appropriate.
116  assert(N->getParent() != 0 && "machine instruction not in a basic block");
117 
118  // Remove from the use/def lists.
119  if (MachineFunction *MF = N->getParent()->getParent())
120  N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
121 
122  N->setParent(0);
123 
125 }
126 
127 /// transferNodesFromList (MI) - When moving a range of instructions from one
128 /// MBB list to another, we need to update the parent pointers and the use/def
129 /// lists.
134  assert(Parent->getParent() == fromList.Parent->getParent() &&
135  "MachineInstr parent mismatch!");
136 
137  // Splice within the same MBB -> no change.
138  if (Parent == fromList.Parent) return;
139 
140  // If splicing between two blocks within the same function, just update the
141  // parent pointers.
142  for (; first != last; ++first)
143  first->setParent(Parent);
144 }
145 
147  assert(!MI->getParent() && "MI is still in a block!");
148  Parent->getParent()->DeleteMachineInstr(MI);
149 }
150 
153  while (I != E && I->isPHI())
154  ++I;
155  assert((I == E || !I->isInsideBundle()) &&
156  "First non-phi MI cannot be inside a bundle!");
157  return I;
158 }
159 
162  iterator E = end();
163  while (I != E && (I->isPHI() || I->isLabel() || I->isDebugValue()))
164  ++I;
165  // FIXME: This needs to change if we wish to bundle labels / dbg_values
166  // inside the bundle.
167  assert((I == E || !I->isInsideBundle()) &&
168  "First non-phi / non-label instruction is inside a bundle!");
169  return I;
170 }
171 
173  iterator B = begin(), E = end(), I = E;
174  while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
175  ; /*noop */
176  while (I != E && !I->isTerminator())
177  ++I;
178  return I;
179 }
180 
183  const_iterator B = begin(), E = end(), I = E;
184  while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
185  ; /*noop */
186  while (I != E && !I->isTerminator())
187  ++I;
188  return I;
189 }
190 
192  instr_iterator B = instr_begin(), E = instr_end(), I = E;
193  while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
194  ; /*noop */
195  while (I != E && !I->isTerminator())
196  ++I;
197  return I;
198 }
199 
201  // Skip over end-of-block dbg_value instructions.
203  while (I != B) {
204  --I;
205  // Return instruction that starts a bundle.
206  if (I->isDebugValue() || I->isInsideBundle())
207  continue;
208  return I;
209  }
210  // The block is all debug values.
211  return end();
212 }
213 
216  // Skip over end-of-block dbg_value instructions.
218  while (I != B) {
219  --I;
220  // Return instruction that starts a bundle.
221  if (I->isDebugValue() || I->isInsideBundle())
222  continue;
223  return I;
224  }
225  // The block is all debug values.
226  return end();
227 }
228 
230  // A block with a landing pad successor only has one other successor.
231  if (succ_size() > 2)
232  return 0;
233  for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
234  if ((*I)->isLandingPad())
235  return *I;
236  return 0;
237 }
238 
239 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
241  print(dbgs());
242 }
243 #endif
244 
246  if (const BasicBlock *LBB = getBasicBlock())
247  return LBB->getName();
248  else
249  return "(null)";
250 }
251 
252 /// Return a hopefully unique identifier for this block.
253 std::string MachineBasicBlock::getFullName() const {
254  std::string Name;
255  if (getParent())
256  Name = (getParent()->getName() + ":").str();
257  if (getBasicBlock())
258  Name += getBasicBlock()->getName();
259  else
260  Name += (Twine("BB") + Twine(getNumber())).str();
261  return Name;
262 }
263 
265  const MachineFunction *MF = getParent();
266  if (!MF) {
267  OS << "Can't print out MachineBasicBlock because parent MachineFunction"
268  << " is null\n";
269  return;
270  }
271 
272  if (Indexes)
273  OS << Indexes->getMBBStartIdx(this) << '\t';
274 
275  OS << "BB#" << getNumber() << ": ";
276 
277  const char *Comma = "";
278  if (const BasicBlock *LBB = getBasicBlock()) {
279  OS << Comma << "derived from LLVM BB ";
280  WriteAsOperand(OS, LBB, /*PrintType=*/false);
281  Comma = ", ";
282  }
283  if (isLandingPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
284  if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
285  if (Alignment)
286  OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
287  << " bytes)";
288 
289  OS << '\n';
290 
291  const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
292  if (!livein_empty()) {
293  if (Indexes) OS << '\t';
294  OS << " Live Ins:";
295  for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
296  OS << ' ' << PrintReg(*I, TRI);
297  OS << '\n';
298  }
299  // Print the preds of this block according to the CFG.
300  if (!pred_empty()) {
301  if (Indexes) OS << '\t';
302  OS << " Predecessors according to CFG:";
303  for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
304  OS << " BB#" << (*PI)->getNumber();
305  OS << '\n';
306  }
307 
308  for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
309  if (Indexes) {
310  if (Indexes->hasIndex(I))
311  OS << Indexes->getInstructionIndex(I);
312  OS << '\t';
313  }
314  OS << '\t';
315  if (I->isInsideBundle())
316  OS << " * ";
317  I->print(OS, &getParent()->getTarget());
318  }
319 
320  // Print the successors of this block according to the CFG.
321  if (!succ_empty()) {
322  if (Indexes) OS << '\t';
323  OS << " Successors according to CFG:";
324  for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
325  OS << " BB#" << (*SI)->getNumber();
326  if (!Weights.empty())
327  OS << '(' << *getWeightIterator(SI) << ')';
328  }
329  OS << '\n';
330  }
331 }
332 
334  std::vector<unsigned>::iterator I =
335  std::find(LiveIns.begin(), LiveIns.end(), Reg);
336  if (I != LiveIns.end())
337  LiveIns.erase(I);
338 }
339 
340 bool MachineBasicBlock::isLiveIn(unsigned Reg) const {
341  livein_iterator I = std::find(livein_begin(), livein_end(), Reg);
342  return I != livein_end();
343 }
344 
345 unsigned
346 MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) {
347  assert(getParent() && "MBB must be inserted in function");
348  assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
349  assert(RC && "Register class is required");
350  assert((isLandingPad() || this == &getParent()->front()) &&
351  "Only the entry block and landing pads can have physreg live ins");
352 
353  bool LiveIn = isLiveIn(PhysReg);
354  iterator I = SkipPHIsAndLabels(begin()), E = end();
357 
358  // Look for an existing copy.
359  if (LiveIn)
360  for (;I != E && I->isCopy(); ++I)
361  if (I->getOperand(1).getReg() == PhysReg) {
362  unsigned VirtReg = I->getOperand(0).getReg();
363  if (!MRI.constrainRegClass(VirtReg, RC))
364  llvm_unreachable("Incompatible live-in register class.");
365  return VirtReg;
366  }
367 
368  // No luck, create a virtual register.
369  unsigned VirtReg = MRI.createVirtualRegister(RC);
370  BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
371  .addReg(PhysReg, RegState::Kill);
372  if (!LiveIn)
373  addLiveIn(PhysReg);
374  return VirtReg;
375 }
376 
378  getParent()->splice(NewAfter, this);
379 }
380 
382  MachineFunction::iterator BBI = NewBefore;
383  getParent()->splice(++BBI, this);
384 }
385 
388  // A block with no successors has no concerns with fall-through edges.
389  if (this->succ_empty()) return;
390 
391  MachineBasicBlock *TBB = 0, *FBB = 0;
393  DebugLoc dl; // FIXME: this is nowhere
394  bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
395  (void) B;
396  assert(!B && "UpdateTerminators requires analyzable predecessors!");
397  if (Cond.empty()) {
398  if (TBB) {
399  // The block has an unconditional branch. If its successor is now
400  // its layout successor, delete the branch.
401  if (isLayoutSuccessor(TBB))
402  TII->RemoveBranch(*this);
403  } else {
404  // The block has an unconditional fallthrough. If its successor is not
405  // its layout successor, insert a branch. First we have to locate the
406  // only non-landing-pad successor, as that is the fallthrough block.
407  for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
408  if ((*SI)->isLandingPad())
409  continue;
410  assert(!TBB && "Found more than one non-landing-pad successor!");
411  TBB = *SI;
412  }
413 
414  // If there is no non-landing-pad successor, the block has no
415  // fall-through edges to be concerned with.
416  if (!TBB)
417  return;
418 
419  // Finally update the unconditional successor to be reached via a branch
420  // if it would not be reached by fallthrough.
421  if (!isLayoutSuccessor(TBB))
422  TII->InsertBranch(*this, TBB, 0, Cond, dl);
423  }
424  } else {
425  if (FBB) {
426  // The block has a non-fallthrough conditional branch. If one of its
427  // successors is its layout successor, rewrite it to a fallthrough
428  // conditional branch.
429  if (isLayoutSuccessor(TBB)) {
430  if (TII->ReverseBranchCondition(Cond))
431  return;
432  TII->RemoveBranch(*this);
433  TII->InsertBranch(*this, FBB, 0, Cond, dl);
434  } else if (isLayoutSuccessor(FBB)) {
435  TII->RemoveBranch(*this);
436  TII->InsertBranch(*this, TBB, 0, Cond, dl);
437  }
438  } else {
439  // Walk through the successors and find the successor which is not
440  // a landing pad and is not the conditional branch destination (in TBB)
441  // as the fallthrough successor.
442  MachineBasicBlock *FallthroughBB = 0;
443  for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
444  if ((*SI)->isLandingPad() || *SI == TBB)
445  continue;
446  assert(!FallthroughBB && "Found more than one fallthrough successor.");
447  FallthroughBB = *SI;
448  }
449  if (!FallthroughBB && canFallThrough()) {
450  // We fallthrough to the same basic block as the conditional jump
451  // targets. Remove the conditional jump, leaving unconditional
452  // fallthrough.
453  // FIXME: This does not seem like a reasonable pattern to support, but it
454  // has been seen in the wild coming out of degenerate ARM test cases.
455  TII->RemoveBranch(*this);
456 
457  // Finally update the unconditional successor to be reached via a branch
458  // if it would not be reached by fallthrough.
459  if (!isLayoutSuccessor(TBB))
460  TII->InsertBranch(*this, TBB, 0, Cond, dl);
461  return;
462  }
463 
464  // The block has a fallthrough conditional branch.
465  if (isLayoutSuccessor(TBB)) {
466  if (TII->ReverseBranchCondition(Cond)) {
467  // We can't reverse the condition, add an unconditional branch.
468  Cond.clear();
469  TII->InsertBranch(*this, FallthroughBB, 0, Cond, dl);
470  return;
471  }
472  TII->RemoveBranch(*this);
473  TII->InsertBranch(*this, FallthroughBB, 0, Cond, dl);
474  } else if (!isLayoutSuccessor(FallthroughBB)) {
475  TII->RemoveBranch(*this);
476  TII->InsertBranch(*this, TBB, FallthroughBB, Cond, dl);
477  }
478  }
479  }
480 }
481 
483 
484  // If we see non-zero value for the first time it means we actually use Weight
485  // list, so we fill all Weights with 0's.
486  if (weight != 0 && Weights.empty())
487  Weights.resize(Successors.size());
488 
489  if (weight != 0 || !Weights.empty())
490  Weights.push_back(weight);
491 
492  Successors.push_back(succ);
493  succ->addPredecessor(this);
494  }
495 
497  succ->removePredecessor(this);
498  succ_iterator I = std::find(Successors.begin(), Successors.end(), succ);
499  assert(I != Successors.end() && "Not a current successor!");
500 
501  // If Weight list is empty it means we don't use it (disabled optimization).
502  if (!Weights.empty()) {
503  weight_iterator WI = getWeightIterator(I);
504  Weights.erase(WI);
505  }
506 
507  Successors.erase(I);
508 }
509 
512  assert(I != Successors.end() && "Not a current successor!");
513 
514  // If Weight list is empty it means we don't use it (disabled optimization).
515  if (!Weights.empty()) {
516  weight_iterator WI = getWeightIterator(I);
517  Weights.erase(WI);
518  }
519 
520  (*I)->removePredecessor(this);
521  return Successors.erase(I);
522 }
523 
525  MachineBasicBlock *New) {
526  if (Old == New)
527  return;
528 
529  succ_iterator E = succ_end();
530  succ_iterator NewI = E;
531  succ_iterator OldI = E;
532  for (succ_iterator I = succ_begin(); I != E; ++I) {
533  if (*I == Old) {
534  OldI = I;
535  if (NewI != E)
536  break;
537  }
538  if (*I == New) {
539  NewI = I;
540  if (OldI != E)
541  break;
542  }
543  }
544  assert(OldI != E && "Old is not a successor of this block");
545  Old->removePredecessor(this);
546 
547  // If New isn't already a successor, let it take Old's place.
548  if (NewI == E) {
549  New->addPredecessor(this);
550  *OldI = New;
551  return;
552  }
553 
554  // New is already a successor.
555  // Update its weight instead of adding a duplicate edge.
556  if (!Weights.empty()) {
557  weight_iterator OldWI = getWeightIterator(OldI);
558  *getWeightIterator(NewI) += *OldWI;
559  Weights.erase(OldWI);
560  }
561  Successors.erase(OldI);
562 }
563 
564 void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) {
565  Predecessors.push_back(pred);
566 }
567 
568 void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
569  pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), pred);
570  assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
571  Predecessors.erase(I);
572 }
573 
575  if (this == fromMBB)
576  return;
577 
578  while (!fromMBB->succ_empty()) {
579  MachineBasicBlock *Succ = *fromMBB->succ_begin();
580  uint32_t Weight = 0;
581 
582  // If Weight list is empty it means we don't use it (disabled optimization).
583  if (!fromMBB->Weights.empty())
584  Weight = *fromMBB->Weights.begin();
585 
586  addSuccessor(Succ, Weight);
587  fromMBB->removeSuccessor(Succ);
588  }
589 }
590 
591 void
593  if (this == fromMBB)
594  return;
595 
596  while (!fromMBB->succ_empty()) {
597  MachineBasicBlock *Succ = *fromMBB->succ_begin();
598  uint32_t Weight = 0;
599  if (!fromMBB->Weights.empty())
600  Weight = *fromMBB->Weights.begin();
601  addSuccessor(Succ, Weight);
602  fromMBB->removeSuccessor(Succ);
603 
604  // Fix up any PHI nodes in the successor.
606  ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
607  for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
608  MachineOperand &MO = MI->getOperand(i);
609  if (MO.getMBB() == fromMBB)
610  MO.setMBB(this);
611  }
612  }
613 }
614 
616  return std::find(pred_begin(), pred_end(), MBB) != pred_end();
617 }
618 
620  return std::find(succ_begin(), succ_end(), MBB) != succ_end();
621 }
622 
626 }
627 
629  MachineFunction::iterator Fallthrough = this;
630  ++Fallthrough;
631  // If FallthroughBlock is off the end of the function, it can't fall through.
632  if (Fallthrough == getParent()->end())
633  return false;
634 
635  // If FallthroughBlock isn't a successor, no fallthrough is possible.
636  if (!isSuccessor(Fallthrough))
637  return false;
638 
639  // Analyze the branches, if any, at the end of the block.
640  MachineBasicBlock *TBB = 0, *FBB = 0;
643  if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
644  // If we couldn't analyze the branch, examine the last instruction.
645  // If the block doesn't end in a known control barrier, assume fallthrough
646  // is possible. The isPredicated check is needed because this code can be
647  // called during IfConversion, where an instruction which is normally a
648  // Barrier is predicated and thus no longer an actual control barrier.
649  return empty() || !back().isBarrier() || TII->isPredicated(&back());
650  }
651 
652  // If there is no branch, control always falls through.
653  if (TBB == 0) return true;
654 
655  // If there is some explicit branch to the fallthrough block, it can obviously
656  // reach, even though the branch should get folded to fall through implicitly.
657  if (MachineFunction::iterator(TBB) == Fallthrough ||
658  MachineFunction::iterator(FBB) == Fallthrough)
659  return true;
660 
661  // If it's an unconditional branch to some block not the fall through, it
662  // doesn't fall through.
663  if (Cond.empty()) return false;
664 
665  // Otherwise, if it is conditional and has no explicit false block, it falls
666  // through.
667  return FBB == 0;
668 }
669 
672  // Splitting the critical edge to a landing pad block is non-trivial. Don't do
673  // it in this generic function.
674  if (Succ->isLandingPad())
675  return NULL;
676 
677  MachineFunction *MF = getParent();
678  DebugLoc dl; // FIXME: this is nowhere
679 
680  // We may need to update this's terminator, but we can't do that if
681  // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
682  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
683  MachineBasicBlock *TBB = 0, *FBB = 0;
685  if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
686  return NULL;
687 
688  // Avoid bugpoint weirdness: A block may end with a conditional branch but
689  // jumps to the same MBB is either case. We have duplicate CFG edges in that
690  // case that we can't handle. Since this never happens in properly optimized
691  // code, just skip those edges.
692  if (TBB && TBB == FBB) {
693  DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
694  << getNumber() << '\n');
695  return NULL;
696  }
697 
699  MF->insert(llvm::next(MachineFunction::iterator(this)), NMBB);
700  DEBUG(dbgs() << "Splitting critical edge:"
701  " BB#" << getNumber()
702  << " -- BB#" << NMBB->getNumber()
703  << " -- BB#" << Succ->getNumber() << '\n');
704 
707  if (LIS)
708  LIS->insertMBBInMaps(NMBB);
709  else if (Indexes)
710  Indexes->insertMBBInMaps(NMBB);
711 
712  // On some targets like Mips, branches may kill virtual registers. Make sure
713  // that LiveVariables is properly updated after updateTerminator replaces the
714  // terminators.
716 
717  // Collect a list of virtual registers killed by the terminators.
718  SmallVector<unsigned, 4> KilledRegs;
719  if (LV)
721  I != E; ++I) {
722  MachineInstr *MI = I;
724  OE = MI->operands_end(); OI != OE; ++OI) {
725  if (!OI->isReg() || OI->getReg() == 0 ||
726  !OI->isUse() || !OI->isKill() || OI->isUndef())
727  continue;
728  unsigned Reg = OI->getReg();
730  LV->getVarInfo(Reg).removeKill(MI)) {
731  KilledRegs.push_back(Reg);
732  DEBUG(dbgs() << "Removing terminator kill: " << *MI);
733  OI->setIsKill(false);
734  }
735  }
736  }
737 
738  SmallVector<unsigned, 4> UsedRegs;
739  if (LIS) {
741  I != E; ++I) {
742  MachineInstr *MI = I;
743 
745  OE = MI->operands_end(); OI != OE; ++OI) {
746  if (!OI->isReg() || OI->getReg() == 0)
747  continue;
748 
749  unsigned Reg = OI->getReg();
750  if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
751  UsedRegs.push_back(Reg);
752  }
753  }
754  }
755 
756  ReplaceUsesOfBlockWith(Succ, NMBB);
757 
758  // If updateTerminator() removes instructions, we need to remove them from
759  // SlotIndexes.
760  SmallVector<MachineInstr*, 4> Terminators;
761  if (Indexes) {
763  I != E; ++I)
764  Terminators.push_back(I);
765  }
766 
768 
769  if (Indexes) {
770  SmallVector<MachineInstr*, 4> NewTerminators;
772  I != E; ++I)
773  NewTerminators.push_back(I);
774 
775  for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
776  E = Terminators.end(); I != E; ++I) {
777  if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
778  NewTerminators.end())
779  Indexes->removeMachineInstrFromMaps(*I);
780  }
781  }
782 
783  // Insert unconditional "jump Succ" instruction in NMBB if necessary.
784  NMBB->addSuccessor(Succ);
785  if (!NMBB->isLayoutSuccessor(Succ)) {
786  Cond.clear();
787  MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, Succ, NULL, Cond, dl);
788 
789  if (Indexes) {
790  for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
791  I != E; ++I) {
792  // Some instructions may have been moved to NMBB by updateTerminator(),
793  // so we first remove any instruction that already has an index.
794  if (Indexes->hasIndex(I))
795  Indexes->removeMachineInstrFromMaps(I);
796  Indexes->insertMachineInstrInMaps(I);
797  }
798  }
799  }
800 
801  // Fix PHI nodes in Succ so they refer to NMBB instead of this
803  i = Succ->instr_begin(),e = Succ->instr_end();
804  i != e && i->isPHI(); ++i)
805  for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
806  if (i->getOperand(ni+1).getMBB() == this)
807  i->getOperand(ni+1).setMBB(NMBB);
808 
809  // Inherit live-ins from the successor
811  E = Succ->livein_end(); I != E; ++I)
812  NMBB->addLiveIn(*I);
813 
814  // Update LiveVariables.
815  const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
816  if (LV) {
817  // Restore kills of virtual registers that were killed by the terminators.
818  while (!KilledRegs.empty()) {
819  unsigned Reg = KilledRegs.pop_back_val();
820  for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
821  if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
822  continue;
824  LV->getVarInfo(Reg).Kills.push_back(I);
825  DEBUG(dbgs() << "Restored terminator kill: " << *I);
826  break;
827  }
828  }
829  // Update relevant live-through information.
830  LV->addNewBlock(NMBB, this, Succ);
831  }
832 
833  if (LIS) {
834  // After splitting the edge and updating SlotIndexes, live intervals may be
835  // in one of two situations, depending on whether this block was the last in
836  // the function. If the original block was the last in the function, all live
837  // intervals will end prior to the beginning of the new split block. If the
838  // original block was not at the end of the function, all live intervals will
839  // extend to the end of the new split block.
840 
841  bool isLastMBB =
843 
844  SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
845  SlotIndex PrevIndex = StartIndex.getPrevSlot();
846  SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
847 
848  // Find the registers used from NMBB in PHIs in Succ.
849  SmallSet<unsigned, 8> PHISrcRegs;
851  I = Succ->instr_begin(), E = Succ->instr_end();
852  I != E && I->isPHI(); ++I) {
853  for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
854  if (I->getOperand(ni+1).getMBB() == NMBB) {
855  MachineOperand &MO = I->getOperand(ni);
856  unsigned Reg = MO.getReg();
857  PHISrcRegs.insert(Reg);
858  if (MO.isUndef())
859  continue;
860 
861  LiveInterval &LI = LIS->getInterval(Reg);
862  VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
863  assert(VNI && "PHI sources should be live out of their predecessors.");
864  LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
865  }
866  }
867  }
868 
870  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
872  if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
873  continue;
874 
875  LiveInterval &LI = LIS->getInterval(Reg);
876  if (!LI.liveAt(PrevIndex))
877  continue;
878 
879  bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
880  if (isLiveOut && isLastMBB) {
881  VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
882  assert(VNI && "LiveInterval should have VNInfo where it is live.");
883  LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
884  } else if (!isLiveOut && !isLastMBB) {
885  LI.removeSegment(StartIndex, EndIndex);
886  }
887  }
888 
889  // Update all intervals for registers whose uses may have been modified by
890  // updateTerminator().
891  LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
892  }
893 
894  if (MachineDominatorTree *MDT =
896  // Update dominator information.
897  MachineDomTreeNode *SucccDTNode = MDT->getNode(Succ);
898 
899  bool IsNewIDom = true;
900  for (const_pred_iterator PI = Succ->pred_begin(), E = Succ->pred_end();
901  PI != E; ++PI) {
902  MachineBasicBlock *PredBB = *PI;
903  if (PredBB == NMBB)
904  continue;
905  if (!MDT->dominates(SucccDTNode, MDT->getNode(PredBB))) {
906  IsNewIDom = false;
907  break;
908  }
909  }
910 
911  // We know "this" dominates the newly created basic block.
912  MachineDomTreeNode *NewDTNode = MDT->addNewBlock(NMBB, this);
913 
914  // If all the other predecessors of "Succ" are dominated by "Succ" itself
915  // then the new block is the new immediate dominator of "Succ". Otherwise,
916  // the new block doesn't dominate anything.
917  if (IsNewIDom)
918  MDT->changeImmediateDominator(SucccDTNode, NewDTNode);
919  }
920 
922  if (MachineLoop *TIL = MLI->getLoopFor(this)) {
923  // If one or the other blocks were not in a loop, the new block is not
924  // either, and thus LI doesn't need to be updated.
925  if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
926  if (TIL == DestLoop) {
927  // Both in the same loop, the NMBB joins loop.
928  DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
929  } else if (TIL->contains(DestLoop)) {
930  // Edge from an outer loop to an inner loop. Add to the outer loop.
931  TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
932  } else if (DestLoop->contains(TIL)) {
933  // Edge from an inner loop to an outer loop. Add to the outer loop.
934  DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
935  } else {
936  // Edge from two loops with no containment relation. Because these
937  // are natural loops, we know that the destination block must be the
938  // header of its loop (adding a branch into a loop elsewhere would
939  // create an irreducible loop).
940  assert(DestLoop->getHeader() == Succ &&
941  "Should not create irreducible loops!");
942  if (MachineLoop *P = DestLoop->getParentLoop())
943  P->addBasicBlockToLoop(NMBB, MLI->getBase());
944  }
945  }
946  }
947 
948  return NMBB;
949 }
950 
951 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
952 /// neighboring instructions so the bundle won't be broken by removing MI.
953 static void unbundleSingleMI(MachineInstr *MI) {
954  // Removing the first instruction in a bundle.
955  if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
956  MI->unbundleFromSucc();
957  // Removing the last instruction in a bundle.
958  if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
959  MI->unbundleFromPred();
960  // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
961  // are already fine.
962 }
963 
966  unbundleSingleMI(I);
967  return Insts.erase(I);
968 }
969 
971  unbundleSingleMI(MI);
974  return Insts.remove(MI);
975 }
976 
978 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
979  assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
980  "Cannot insert instruction with bundle flags");
981  // Set the bundle flags when inserting inside a bundle.
982  if (I != instr_end() && I->isBundledWithPred()) {
985  }
986  return Insts.insert(I, MI);
987 }
988 
989 /// removeFromParent - This method unlinks 'this' from the containing function,
990 /// and returns it, but does not delete it.
992  assert(getParent() && "Not embedded in a function!");
993  getParent()->remove(this);
994  return this;
995 }
996 
997 
998 /// eraseFromParent - This method unlinks 'this' from the containing function,
999 /// and deletes it.
1001  assert(getParent() && "Not embedded in a function!");
1002  getParent()->erase(this);
1003 }
1004 
1005 
1006 /// ReplaceUsesOfBlockWith - Given a machine basic block that branched to
1007 /// 'Old', change the code and CFG so that it branches to 'New' instead.
1009  MachineBasicBlock *New) {
1010  assert(Old != New && "Cannot replace self with self!");
1011 
1013  while (I != instr_begin()) {
1014  --I;
1015  if (!I->isTerminator()) break;
1016 
1017  // Scan the operands of this machine instruction, replacing any uses of Old
1018  // with New.
1019  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1020  if (I->getOperand(i).isMBB() &&
1021  I->getOperand(i).getMBB() == Old)
1022  I->getOperand(i).setMBB(New);
1023  }
1024 
1025  // Update the successor information.
1026  replaceSuccessor(Old, New);
1027 }
1028 
1029 /// CorrectExtraCFGEdges - Various pieces of code can cause excess edges in the
1030 /// CFG to be inserted. If we have proven that MBB can only branch to DestA and
1031 /// DestB, remove any other MBB successors from the CFG. DestA and DestB can be
1032 /// null.
1033 ///
1034 /// Besides DestA and DestB, retain other edges leading to LandingPads
1035 /// (currently there can be only one; we don't check or require that here).
1036 /// Note it is possible that DestA and/or DestB are LandingPads.
1038  MachineBasicBlock *DestB,
1039  bool isCond) {
1040  // The values of DestA and DestB frequently come from a call to the
1041  // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1042  // values from there.
1043  //
1044  // 1. If both DestA and DestB are null, then the block ends with no branches
1045  // (it falls through to its successor).
1046  // 2. If DestA is set, DestB is null, and isCond is false, then the block ends
1047  // with only an unconditional branch.
1048  // 3. If DestA is set, DestB is null, and isCond is true, then the block ends
1049  // with a conditional branch that falls through to a successor (DestB).
1050  // 4. If DestA and DestB is set and isCond is true, then the block ends with a
1051  // conditional branch followed by an unconditional branch. DestA is the
1052  // 'true' destination and DestB is the 'false' destination.
1053 
1054  bool Changed = false;
1055 
1056  MachineFunction::iterator FallThru =
1058 
1059  if (DestA == 0 && DestB == 0) {
1060  // Block falls through to successor.
1061  DestA = FallThru;
1062  DestB = FallThru;
1063  } else if (DestA != 0 && DestB == 0) {
1064  if (isCond)
1065  // Block ends in conditional jump that falls through to successor.
1066  DestB = FallThru;
1067  } else {
1068  assert(DestA && DestB && isCond &&
1069  "CFG in a bad state. Cannot correct CFG edges");
1070  }
1071 
1072  // Remove superfluous edges. I.e., those which aren't destinations of this
1073  // basic block, duplicate edges, or landing pads.
1076  while (SI != succ_end()) {
1077  const MachineBasicBlock *MBB = *SI;
1078  if (!SeenMBBs.insert(MBB) ||
1079  (MBB != DestA && MBB != DestB && !MBB->isLandingPad())) {
1080  // This is a superfluous edge, remove it.
1081  SI = removeSuccessor(SI);
1082  Changed = true;
1083  } else {
1084  ++SI;
1085  }
1086  }
1087 
1088  return Changed;
1089 }
1090 
1091 /// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping
1092 /// any DBG_VALUE instructions. Return UnknownLoc if there is none.
1093 DebugLoc
1094 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1095  DebugLoc DL;
1096  instr_iterator E = instr_end();
1097  if (MBBI == E)
1098  return DL;
1099 
1100  // Skip debug declarations, we don't want a DebugLoc from them.
1101  while (MBBI != E && MBBI->isDebugValue())
1102  MBBI++;
1103  if (MBBI != E)
1104  DL = MBBI->getDebugLoc();
1105  return DL;
1106 }
1107 
1108 /// getSuccWeight - Return weight of the edge from this block to MBB.
1109 ///
1110 uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const {
1111  if (Weights.empty())
1112  return 0;
1113 
1114  return *getWeightIterator(Succ);
1115 }
1116 
1117 /// getWeightIterator - Return wight iterator corresonding to the I successor
1118 /// iterator
1119 MachineBasicBlock::weight_iterator MachineBasicBlock::
1120 getWeightIterator(MachineBasicBlock::succ_iterator I) {
1121  assert(Weights.size() == Successors.size() && "Async weight list!");
1122  size_t index = std::distance(Successors.begin(), I);
1123  assert(index < Weights.size() && "Not a current successor!");
1124  return Weights.begin() + index;
1125 }
1126 
1127 /// getWeightIterator - Return wight iterator corresonding to the I successor
1128 /// iterator
1129 MachineBasicBlock::const_weight_iterator MachineBasicBlock::
1130 getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
1131  assert(Weights.size() == Successors.size() && "Async weight list!");
1132  const size_t index = std::distance(Successors.begin(), I);
1133  assert(index < Weights.size() && "Not a current successor!");
1134  return Weights.begin() + index;
1135 }
1136 
1137 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1138 /// as of just before "MI".
1139 ///
1140 /// Search is localised to a neighborhood of
1141 /// Neighborhood instructions before (searching for defs or kills) and N
1142 /// instructions after (searching just for defs) MI.
1145  unsigned Reg, MachineInstr *MI,
1146  unsigned Neighborhood) {
1147  unsigned N = Neighborhood;
1148  MachineBasicBlock *MBB = MI->getParent();
1149 
1150  // Start by searching backwards from MI, looking for kills, reads or defs.
1151 
1153  // If this is the first insn in the block, don't search backwards.
1154  if (I != MBB->begin()) {
1155  do {
1156  --I;
1157 
1159  MIOperands(I).analyzePhysReg(Reg, TRI);
1160 
1161  if (Analysis.Defines)
1162  // Outputs happen after inputs so they take precedence if both are
1163  // present.
1164  return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
1165 
1166  if (Analysis.Kills || Analysis.Clobbers)
1167  // Register killed, so isn't live.
1168  return LQR_Dead;
1169 
1170  else if (Analysis.ReadsOverlap)
1171  // Defined or read without a previous kill - live.
1172  return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1173 
1174  } while (I != MBB->begin() && --N > 0);
1175  }
1176 
1177  // Did we get to the start of the block?
1178  if (I == MBB->begin()) {
1179  // If so, the register's state is definitely defined by the live-in state.
1180  for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1181  RAI.isValid(); ++RAI) {
1182  if (MBB->isLiveIn(*RAI))
1183  return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
1184  }
1185 
1186  return LQR_Dead;
1187  }
1188 
1189  N = Neighborhood;
1190 
1191  // Try searching forwards from MI, looking for reads or defs.
1193  // If this is the last insn in the block, don't search forwards.
1194  if (I != MBB->end()) {
1195  for (++I; I != MBB->end() && N > 0; ++I, --N) {
1197  MIOperands(I).analyzePhysReg(Reg, TRI);
1198 
1199  if (Analysis.ReadsOverlap)
1200  // Used, therefore must have been live.
1201  return (Analysis.Reads) ?
1203 
1204  else if (Analysis.Clobbers || Analysis.Defines)
1205  // Defined (but not read) therefore cannot have been live.
1206  return LQR_Dead;
1207  }
1208  }
1209 
1210  // At this point we have no idea of the liveness of the register.
1211  return LQR_Unknown;
1212 }
1213 
1215  bool t) {
1216  OS << "BB#" << MBB->getNumber();
1217 }
1218 
unsigned succ_size() const
void push_back(const T &Elt)
Definition: SmallVector.h:236
const MachineFunction * getParent() const
mop_iterator operands_end()
Definition: MachineInstr.h:285
instr_iterator erase(instr_iterator I)
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:175
instr_iterator instr_begin()
void transferNodesFromList(ilist_node_traits &, ilist_iterator< NodeTy >, ilist_iterator< NodeTy >)
Definition: ilist.h:117
void removeNodeFromList(NodeTy *)
Definition: ilist.h:116
instr_iterator instr_end()
bool removeKill(MachineInstr *MI)
Definition: LiveVariables.h:94
MachineBasicBlock * getMBB() const
static unsigned index2VirtReg(unsigned Index)
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
instr_iterator getFirstInstrTerminator()
std::vector< unsigned >::const_iterator livein_iterator
static bool isVirtualRegister(unsigned Reg)
const char * getPrivateGlobalPrefix() const
Definition: MCAsmInfo.h:434
void removeLiveIn(unsigned Reg)
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
bool insert(PtrType Ptr)
Definition: SmallPtrSet.h:253
void addLiveIn(unsigned Reg)
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, unsigned Reg, MachineInstr *MI, unsigned Neighborhood=10)
void moveAfter(MachineBasicBlock *NewBefore)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const
unsigned getFunctionNumber() const
Instructions::iterator instr_iterator
MachineBasicBlock * removeFromParent()
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:350
LoopInfoBase< BlockT, LoopT > * LI
Definition: LoopInfoImpl.h:411
StringRef getName() const
Definition: Value.cpp:167
bool DefinesDead
DefinesDead - All defs of a Reg or a super-register are dead.
void WriteAsOperand(raw_ostream &, const Value *, bool PrintTy=true, const Module *Context=0)
Definition: AsmWriter.cpp:1179
livein_iterator livein_begin() const
unsigned getNumVirtRegs() const
void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
static void removeGarbageObject(void *Object)
Definition: LeakDetector.h:47
MCSymbol * GetOrCreateSymbol(StringRef Name)
Definition: MCContext.cpp:118
const HexagonInstrInfo * TII
AnalysisType * getAnalysisIfAvailable() const
bool isPHI() const
Definition: MachineInstr.h:648
#define llvm_unreachable(msg)
std::vector< MachineBasicBlock * >::iterator succ_iterator
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P)
bool isUndef() const
static void unbundleSingleMI(MachineInstr *MI)
void print(raw_ostream &OS, SlotIndexes *=0) const
MachineInstr * remove_instr(MachineInstr *I)
PhysRegInfo analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI)
#define false
Definition: ConvertUTF.c:64
unsigned getNumOperands() const
Definition: MachineInstr.h:265
bool isBundledWithSucc() const
Definition: MachineInstr.h:226
void unbundleFromPred()
Break bundle above this instruction.
void transferSuccessors(MachineBasicBlock *fromMBB)
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:56
iterator addSegment(Segment S)
Definition: LiveInterval.h:403
bool insert(const T &V)
Definition: SmallSet.h:59
virtual bool ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
MCContext & getContext() const
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
const BasicBlock * getBasicBlock() const
SlotIndex getPrevSlot() const
Definition: SlotIndexes.h:292
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:119
bundle_iterator< MachineInstr, instr_iterator > iterator
#define P(N)
bool Kills
There is a kill of Reg or a super-register.
iterator SkipPHIsAndLabels(iterator I)
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=0)
void insertMBBInMaps(MachineBasicBlock *mbb)
Add the given MachineBasicBlock into the maps.
Definition: SlotIndexes.h:639
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
bool ReadsOverlap
ReadsOverlap - Reg or an overlapping register is read.
livein_iterator livein_end() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:267
void setMBB(MachineBasicBlock *MBB)
iterator insert(iterator where, const NodeTy &val)
Definition: ilist.h:664
Register is known to be dead.
void setFlag(MIFlag Flag)
setFlag - Set a MI flag.
Definition: MachineInstr.h:159
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:170
ItTy next(ItTy it, Dist n)
Definition: STLExtras.h:154
const MachineBasicBlock * getLandingPadSuccessor() const
void remove(iterator MBBI)
bool isBundledWithPred() const
Definition: MachineInstr.h:222
LivenessQueryResult
Possible outcome of a register liveness query to computeRegisterLiveness()
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Register is known to be live.
void removeSuccessor(MachineBasicBlock *succ)
void moveBefore(MachineBasicBlock *NewAfter)
VarInfo & getVarInfo(unsigned RegIdx)
getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:330
MCSymbol * getSymbol() const
SlotIndex getInstructionIndex(const MachineInstr *MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:414
iterator erase(iterator where)
Definition: ilist.h:465
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
DebugLoc findDebugLoc(instr_iterator MBBI)
void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB, MachineBasicBlock *SuccBB)
std::string getFullName() const
Return a hopefully unique identifier for this block.
std::vector< MachineInstr * > Kills
Definition: LiveVariables.h:89
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
virtual const TargetInstrInfo * getInstrInfo() const
BasicBlockListType::const_iterator const_iterator
void splice(iterator InsertPt, iterator MBBI)
bool hasIndex(const MachineInstr *instr) const
Definition: SlotIndexes.h:409
bool isSuccessor(const MachineBasicBlock *MBB) const
bool Reads
Reads - Read or a super-register is read.
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const
raw_ostream & dbgs()
dbgs - Return a circular-buffered debug stream.
Definition: Debug.cpp:101
static void deleteNode(NodeTy *V)
Definition: ilist.h:113
StringRef getName() const
static void addGarbageObject(void *Object)
Definition: LeakDetector.h:37
void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New)
bool count(const T &V) const
count - Return true if the element is in the set.
Definition: SmallSet.h:48
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
static bool isPhysicalRegister(unsigned Reg)
block Block Frequency Analysis
void addNodeToList(NodeTy *)
Definition: ilist.h:115
bool isLiveIn(unsigned Reg) const
MachineRegisterInfo & getRegInfo()
bool Defines
Defines - Reg or a super-register is defined.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
const TargetMachine & getTarget() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
virtual const TargetRegisterInfo * getRegisterInfo() const
void removeFromMBBNumbering(unsigned N)
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:486
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:1688
unsigned getReg() const
getReg - Returns the register number.
void erase(iterator MBBI)
void insert(iterator MBBI, MachineBasicBlock *MBB)
void unbundleFromSucc()
Break bundle below this instruction.
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
unsigned addToMBBNumbering(MachineBasicBlock *MBB)
Adds the MBB to the internal numbering. Returns the unique number assigned to the MBB...
mop_iterator operands_begin()
Definition: MachineInstr.h:284
BasicBlockListType::iterator iterator
#define DEBUG(X)
Definition: Debug.h:97
virtual bool isPredicated(const MachineInstr *MI) const
bool isPredecessor(const MachineBasicBlock *MBB) const
const MCRegisterInfo & MRI
StringRef getName() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:92
NodeTy * remove(iterator &IT)
Definition: ilist.h:435
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
bool CorrectExtraCFGEdges(MachineBasicBlock *DestA, MachineBasicBlock *DestB, bool isCond)
bool isBarrier(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:356