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ScheduleDAG.cpp
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1 //===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #define DEBUG_TYPE "pre-RA-sched"
20 #include "llvm/Support/Debug.h"
25 #include <climits>
26 using namespace llvm;
27 
28 #ifndef NDEBUG
30  "stress-sched", cl::Hidden, cl::init(false),
31  cl::desc("Stress test instruction scheduling"));
32 #endif
33 
34 void SchedulingPriorityQueue::anchor() { }
35 
37  : TM(mf.getTarget()),
38  TII(TM.getInstrInfo()),
39  TRI(TM.getRegisterInfo()),
40  MF(mf), MRI(mf.getRegInfo()),
41  EntrySU(), ExitSU() {
42 #ifndef NDEBUG
44 #endif
45 }
46 
48 
49 /// Clear the DAG state (e.g. between scheduling regions).
51  SUnits.clear();
52  EntrySU = SUnit();
53  ExitSU = SUnit();
54 }
55 
56 /// getInstrDesc helper to handle SDNodes.
57 const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
58  if (!Node || !Node->isMachineOpcode()) return NULL;
59  return &TII->get(Node->getMachineOpcode());
60 }
61 
62 /// addPred - This adds the specified edge as a pred of the current node if
63 /// not already. It also adds the current node as a successor of the
64 /// specified node.
65 bool SUnit::addPred(const SDep &D, bool Required) {
66  // If this node already has this depenence, don't add a redundant one.
67  for (SmallVectorImpl<SDep>::iterator I = Preds.begin(), E = Preds.end();
68  I != E; ++I) {
69  // Zero-latency weak edges may be added purely for heuristic ordering. Don't
70  // add them if another kind of edge already exists.
71  if (!Required && I->getSUnit() == D.getSUnit())
72  return false;
73  if (I->overlaps(D)) {
74  // Extend the latency if needed. Equivalent to removePred(I) + addPred(D).
75  if (I->getLatency() < D.getLatency()) {
76  SUnit *PredSU = I->getSUnit();
77  // Find the corresponding successor in N.
78  SDep ForwardD = *I;
79  ForwardD.setSUnit(this);
80  for (SmallVectorImpl<SDep>::iterator II = PredSU->Succs.begin(),
81  EE = PredSU->Succs.end(); II != EE; ++II) {
82  if (*II == ForwardD) {
83  II->setLatency(D.getLatency());
84  break;
85  }
86  }
87  I->setLatency(D.getLatency());
88  }
89  return false;
90  }
91  }
92  // Now add a corresponding succ to N.
93  SDep P = D;
94  P.setSUnit(this);
95  SUnit *N = D.getSUnit();
96  // Update the bookkeeping.
97  if (D.getKind() == SDep::Data) {
98  assert(NumPreds < UINT_MAX && "NumPreds will overflow!");
99  assert(N->NumSuccs < UINT_MAX && "NumSuccs will overflow!");
100  ++NumPreds;
101  ++N->NumSuccs;
102  }
103  if (!N->isScheduled) {
104  if (D.isWeak()) {
105  ++WeakPredsLeft;
106  }
107  else {
108  assert(NumPredsLeft < UINT_MAX && "NumPredsLeft will overflow!");
109  ++NumPredsLeft;
110  }
111  }
112  if (!isScheduled) {
113  if (D.isWeak()) {
114  ++N->WeakSuccsLeft;
115  }
116  else {
117  assert(N->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");
118  ++N->NumSuccsLeft;
119  }
120  }
121  Preds.push_back(D);
122  N->Succs.push_back(P);
123  if (P.getLatency() != 0) {
124  this->setDepthDirty();
125  N->setHeightDirty();
126  }
127  return true;
128 }
129 
130 /// removePred - This removes the specified edge as a pred of the current
131 /// node if it exists. It also removes the current node as a successor of
132 /// the specified node.
133 void SUnit::removePred(const SDep &D) {
134  // Find the matching predecessor.
135  for (SmallVectorImpl<SDep>::iterator I = Preds.begin(), E = Preds.end();
136  I != E; ++I)
137  if (*I == D) {
138  // Find the corresponding successor in N.
139  SDep P = D;
140  P.setSUnit(this);
141  SUnit *N = D.getSUnit();
142  SmallVectorImpl<SDep>::iterator Succ = std::find(N->Succs.begin(),
143  N->Succs.end(), P);
144  assert(Succ != N->Succs.end() && "Mismatching preds / succs lists!");
145  N->Succs.erase(Succ);
146  Preds.erase(I);
147  // Update the bookkeeping.
148  if (P.getKind() == SDep::Data) {
149  assert(NumPreds > 0 && "NumPreds will underflow!");
150  assert(N->NumSuccs > 0 && "NumSuccs will underflow!");
151  --NumPreds;
152  --N->NumSuccs;
153  }
154  if (!N->isScheduled) {
155  if (D.isWeak())
156  --WeakPredsLeft;
157  else {
158  assert(NumPredsLeft > 0 && "NumPredsLeft will underflow!");
159  --NumPredsLeft;
160  }
161  }
162  if (!isScheduled) {
163  if (D.isWeak())
164  --N->WeakSuccsLeft;
165  else {
166  assert(N->NumSuccsLeft > 0 && "NumSuccsLeft will underflow!");
167  --N->NumSuccsLeft;
168  }
169  }
170  if (P.getLatency() != 0) {
171  this->setDepthDirty();
172  N->setHeightDirty();
173  }
174  return;
175  }
176 }
177 
178 void SUnit::setDepthDirty() {
179  if (!isDepthCurrent) return;
180  SmallVector<SUnit*, 8> WorkList;
181  WorkList.push_back(this);
182  do {
183  SUnit *SU = WorkList.pop_back_val();
184  SU->isDepthCurrent = false;
185  for (SUnit::const_succ_iterator I = SU->Succs.begin(),
186  E = SU->Succs.end(); I != E; ++I) {
187  SUnit *SuccSU = I->getSUnit();
188  if (SuccSU->isDepthCurrent)
189  WorkList.push_back(SuccSU);
190  }
191  } while (!WorkList.empty());
192 }
193 
195  if (!isHeightCurrent) return;
196  SmallVector<SUnit*, 8> WorkList;
197  WorkList.push_back(this);
198  do {
199  SUnit *SU = WorkList.pop_back_val();
200  SU->isHeightCurrent = false;
201  for (SUnit::const_pred_iterator I = SU->Preds.begin(),
202  E = SU->Preds.end(); I != E; ++I) {
203  SUnit *PredSU = I->getSUnit();
204  if (PredSU->isHeightCurrent)
205  WorkList.push_back(PredSU);
206  }
207  } while (!WorkList.empty());
208 }
209 
210 /// setDepthToAtLeast - Update this node's successors to reflect the
211 /// fact that this node's depth just increased.
212 ///
213 void SUnit::setDepthToAtLeast(unsigned NewDepth) {
214  if (NewDepth <= getDepth())
215  return;
216  setDepthDirty();
217  Depth = NewDepth;
218  isDepthCurrent = true;
219 }
220 
221 /// setHeightToAtLeast - Update this node's predecessors to reflect the
222 /// fact that this node's height just increased.
223 ///
224 void SUnit::setHeightToAtLeast(unsigned NewHeight) {
225  if (NewHeight <= getHeight())
226  return;
227  setHeightDirty();
228  Height = NewHeight;
229  isHeightCurrent = true;
230 }
231 
232 /// ComputeDepth - Calculate the maximal path from the node to the exit.
233 ///
234 void SUnit::ComputeDepth() {
235  SmallVector<SUnit*, 8> WorkList;
236  WorkList.push_back(this);
237  do {
238  SUnit *Cur = WorkList.back();
239 
240  bool Done = true;
241  unsigned MaxPredDepth = 0;
242  for (SUnit::const_pred_iterator I = Cur->Preds.begin(),
243  E = Cur->Preds.end(); I != E; ++I) {
244  SUnit *PredSU = I->getSUnit();
245  if (PredSU->isDepthCurrent)
246  MaxPredDepth = std::max(MaxPredDepth,
247  PredSU->Depth + I->getLatency());
248  else {
249  Done = false;
250  WorkList.push_back(PredSU);
251  }
252  }
253 
254  if (Done) {
255  WorkList.pop_back();
256  if (MaxPredDepth != Cur->Depth) {
257  Cur->setDepthDirty();
258  Cur->Depth = MaxPredDepth;
259  }
260  Cur->isDepthCurrent = true;
261  }
262  } while (!WorkList.empty());
263 }
264 
265 /// ComputeHeight - Calculate the maximal path from the node to the entry.
266 ///
267 void SUnit::ComputeHeight() {
268  SmallVector<SUnit*, 8> WorkList;
269  WorkList.push_back(this);
270  do {
271  SUnit *Cur = WorkList.back();
272 
273  bool Done = true;
274  unsigned MaxSuccHeight = 0;
275  for (SUnit::const_succ_iterator I = Cur->Succs.begin(),
276  E = Cur->Succs.end(); I != E; ++I) {
277  SUnit *SuccSU = I->getSUnit();
278  if (SuccSU->isHeightCurrent)
279  MaxSuccHeight = std::max(MaxSuccHeight,
280  SuccSU->Height + I->getLatency());
281  else {
282  Done = false;
283  WorkList.push_back(SuccSU);
284  }
285  }
286 
287  if (Done) {
288  WorkList.pop_back();
289  if (MaxSuccHeight != Cur->Height) {
290  Cur->setHeightDirty();
291  Cur->Height = MaxSuccHeight;
292  }
293  Cur->isHeightCurrent = true;
294  }
295  } while (!WorkList.empty());
296 }
297 
299  if (NumPreds < 2)
300  return;
301 
302  SUnit::pred_iterator BestI = Preds.begin();
303  unsigned MaxDepth = BestI->getSUnit()->getDepth();
305  I = llvm::next(BestI), E = Preds.end(); I != E; ++I) {
306  if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth)
307  BestI = I;
308  }
309  if (BestI != Preds.begin())
310  std::swap(*Preds.begin(), *BestI);
311 }
312 
313 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
314 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
315 /// a group of nodes flagged together.
316 void SUnit::dump(const ScheduleDAG *G) const {
317  dbgs() << "SU(" << NodeNum << "): ";
318  G->dumpNode(this);
319 }
320 
321 void SUnit::dumpAll(const ScheduleDAG *G) const {
322  dump(G);
323 
324  dbgs() << " # preds left : " << NumPredsLeft << "\n";
325  dbgs() << " # succs left : " << NumSuccsLeft << "\n";
326  if (WeakPredsLeft)
327  dbgs() << " # weak preds left : " << WeakPredsLeft << "\n";
328  if (WeakSuccsLeft)
329  dbgs() << " # weak succs left : " << WeakSuccsLeft << "\n";
330  dbgs() << " # rdefs left : " << NumRegDefsLeft << "\n";
331  dbgs() << " Latency : " << Latency << "\n";
332  dbgs() << " Depth : " << getDepth() << "\n";
333  dbgs() << " Height : " << getHeight() << "\n";
334 
335  if (Preds.size() != 0) {
336  dbgs() << " Predecessors:\n";
337  for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
338  I != E; ++I) {
339  dbgs() << " ";
340  switch (I->getKind()) {
341  case SDep::Data: dbgs() << "val "; break;
342  case SDep::Anti: dbgs() << "anti"; break;
343  case SDep::Output: dbgs() << "out "; break;
344  case SDep::Order: dbgs() << "ch "; break;
345  }
346  dbgs() << "SU(" << I->getSUnit()->NodeNum << ")";
347  if (I->isArtificial())
348  dbgs() << " *";
349  dbgs() << ": Latency=" << I->getLatency();
350  if (I->isAssignedRegDep())
351  dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
352  dbgs() << "\n";
353  }
354  }
355  if (Succs.size() != 0) {
356  dbgs() << " Successors:\n";
357  for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
358  I != E; ++I) {
359  dbgs() << " ";
360  switch (I->getKind()) {
361  case SDep::Data: dbgs() << "val "; break;
362  case SDep::Anti: dbgs() << "anti"; break;
363  case SDep::Output: dbgs() << "out "; break;
364  case SDep::Order: dbgs() << "ch "; break;
365  }
366  dbgs() << "SU(" << I->getSUnit()->NodeNum << ")";
367  if (I->isArtificial())
368  dbgs() << " *";
369  dbgs() << ": Latency=" << I->getLatency();
370  if (I->isAssignedRegDep())
371  dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
372  dbgs() << "\n";
373  }
374  }
375  dbgs() << "\n";
376 }
377 #endif
378 
379 #ifndef NDEBUG
380 /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
381 /// their state is consistent. Return the number of scheduled nodes.
382 ///
383 unsigned ScheduleDAG::VerifyScheduledDAG(bool isBottomUp) {
384  bool AnyNotSched = false;
385  unsigned DeadNodes = 0;
386  for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
387  if (!SUnits[i].isScheduled) {
388  if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) {
389  ++DeadNodes;
390  continue;
391  }
392  if (!AnyNotSched)
393  dbgs() << "*** Scheduling failed! ***\n";
394  SUnits[i].dump(this);
395  dbgs() << "has not been scheduled!\n";
396  AnyNotSched = true;
397  }
398  if (SUnits[i].isScheduled &&
399  (isBottomUp ? SUnits[i].getHeight() : SUnits[i].getDepth()) >
400  unsigned(INT_MAX)) {
401  if (!AnyNotSched)
402  dbgs() << "*** Scheduling failed! ***\n";
403  SUnits[i].dump(this);
404  dbgs() << "has an unexpected "
405  << (isBottomUp ? "Height" : "Depth") << " value!\n";
406  AnyNotSched = true;
407  }
408  if (isBottomUp) {
409  if (SUnits[i].NumSuccsLeft != 0) {
410  if (!AnyNotSched)
411  dbgs() << "*** Scheduling failed! ***\n";
412  SUnits[i].dump(this);
413  dbgs() << "has successors left!\n";
414  AnyNotSched = true;
415  }
416  } else {
417  if (SUnits[i].NumPredsLeft != 0) {
418  if (!AnyNotSched)
419  dbgs() << "*** Scheduling failed! ***\n";
420  SUnits[i].dump(this);
421  dbgs() << "has predecessors left!\n";
422  AnyNotSched = true;
423  }
424  }
425  }
426  assert(!AnyNotSched);
427  return SUnits.size() - DeadNodes;
428 }
429 #endif
430 
431 /// InitDAGTopologicalSorting - create the initial topological
432 /// ordering from the DAG to be scheduled.
433 ///
434 /// The idea of the algorithm is taken from
435 /// "Online algorithms for managing the topological order of
436 /// a directed acyclic graph" by David J. Pearce and Paul H.J. Kelly
437 /// This is the MNR algorithm, which was first introduced by
438 /// A. Marchetti-Spaccamela, U. Nanni and H. Rohnert in
439 /// "Maintaining a topological order under edge insertions".
440 ///
441 /// Short description of the algorithm:
442 ///
443 /// Topological ordering, ord, of a DAG maps each node to a topological
444 /// index so that for all edges X->Y it is the case that ord(X) < ord(Y).
445 ///
446 /// This means that if there is a path from the node X to the node Z,
447 /// then ord(X) < ord(Z).
448 ///
449 /// This property can be used to check for reachability of nodes:
450 /// if Z is reachable from X, then an insertion of the edge Z->X would
451 /// create a cycle.
452 ///
453 /// The algorithm first computes a topological ordering for the DAG by
454 /// initializing the Index2Node and Node2Index arrays and then tries to keep
455 /// the ordering up-to-date after edge insertions by reordering the DAG.
456 ///
457 /// On insertion of the edge X->Y, the algorithm first marks by calling DFS
458 /// the nodes reachable from Y, and then shifts them using Shift to lie
459 /// immediately after X in Index2Node.
461  unsigned DAGSize = SUnits.size();
462  std::vector<SUnit*> WorkList;
463  WorkList.reserve(DAGSize);
464 
465  Index2Node.resize(DAGSize);
466  Node2Index.resize(DAGSize);
467 
468  // Initialize the data structures.
469  if (ExitSU)
470  WorkList.push_back(ExitSU);
471  for (unsigned i = 0, e = DAGSize; i != e; ++i) {
472  SUnit *SU = &SUnits[i];
473  int NodeNum = SU->NodeNum;
474  unsigned Degree = SU->Succs.size();
475  // Temporarily use the Node2Index array as scratch space for degree counts.
476  Node2Index[NodeNum] = Degree;
477 
478  // Is it a node without dependencies?
479  if (Degree == 0) {
480  assert(SU->Succs.empty() && "SUnit should have no successors");
481  // Collect leaf nodes.
482  WorkList.push_back(SU);
483  }
484  }
485 
486  int Id = DAGSize;
487  while (!WorkList.empty()) {
488  SUnit *SU = WorkList.back();
489  WorkList.pop_back();
490  if (SU->NodeNum < DAGSize)
491  Allocate(SU->NodeNum, --Id);
492  for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
493  I != E; ++I) {
494  SUnit *SU = I->getSUnit();
495  if (SU->NodeNum < DAGSize && !--Node2Index[SU->NodeNum])
496  // If all dependencies of the node are processed already,
497  // then the node can be computed now.
498  WorkList.push_back(SU);
499  }
500  }
501 
502  Visited.resize(DAGSize);
503 
504 #ifndef NDEBUG
505  // Check correctness of the ordering
506  for (unsigned i = 0, e = DAGSize; i != e; ++i) {
507  SUnit *SU = &SUnits[i];
508  for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
509  I != E; ++I) {
510  assert(Node2Index[SU->NodeNum] > Node2Index[I->getSUnit()->NodeNum] &&
511  "Wrong topological sorting");
512  }
513  }
514 #endif
515 }
516 
517 /// AddPred - Updates the topological ordering to accommodate an edge
518 /// to be added from SUnit X to SUnit Y.
520  int UpperBound, LowerBound;
521  LowerBound = Node2Index[Y->NodeNum];
522  UpperBound = Node2Index[X->NodeNum];
523  bool HasLoop = false;
524  // Is Ord(X) < Ord(Y) ?
525  if (LowerBound < UpperBound) {
526  // Update the topological order.
527  Visited.reset();
528  DFS(Y, UpperBound, HasLoop);
529  assert(!HasLoop && "Inserted edge creates a loop!");
530  // Recompute topological indexes.
531  Shift(Visited, LowerBound, UpperBound);
532  }
533 }
534 
535 /// RemovePred - Updates the topological ordering to accommodate an
536 /// an edge to be removed from the specified node N from the predecessors
537 /// of the current node M.
539  // InitDAGTopologicalSorting();
540 }
541 
542 /// DFS - Make a DFS traversal to mark all nodes reachable from SU and mark
543 /// all nodes affected by the edge insertion. These nodes will later get new
544 /// topological indexes by means of the Shift method.
545 void ScheduleDAGTopologicalSort::DFS(const SUnit *SU, int UpperBound,
546  bool &HasLoop) {
547  std::vector<const SUnit*> WorkList;
548  WorkList.reserve(SUnits.size());
549 
550  WorkList.push_back(SU);
551  do {
552  SU = WorkList.back();
553  WorkList.pop_back();
554  Visited.set(SU->NodeNum);
555  for (int I = SU->Succs.size()-1; I >= 0; --I) {
556  unsigned s = SU->Succs[I].getSUnit()->NodeNum;
557  // Edges to non-SUnits are allowed but ignored (e.g. ExitSU).
558  if (s >= Node2Index.size())
559  continue;
560  if (Node2Index[s] == UpperBound) {
561  HasLoop = true;
562  return;
563  }
564  // Visit successors if not already and in affected region.
565  if (!Visited.test(s) && Node2Index[s] < UpperBound) {
566  WorkList.push_back(SU->Succs[I].getSUnit());
567  }
568  }
569  } while (!WorkList.empty());
570 }
571 
572 /// Shift - Renumber the nodes so that the topological ordering is
573 /// preserved.
574 void ScheduleDAGTopologicalSort::Shift(BitVector& Visited, int LowerBound,
575  int UpperBound) {
576  std::vector<int> L;
577  int shift = 0;
578  int i;
579 
580  for (i = LowerBound; i <= UpperBound; ++i) {
581  // w is node at topological index i.
582  int w = Index2Node[i];
583  if (Visited.test(w)) {
584  // Unmark.
585  Visited.reset(w);
586  L.push_back(w);
587  shift = shift + 1;
588  } else {
589  Allocate(w, i - shift);
590  }
591  }
592 
593  for (unsigned j = 0; j < L.size(); ++j) {
594  Allocate(L[j], i - shift);
595  i = i + 1;
596  }
597 }
598 
599 
600 /// WillCreateCycle - Returns true if adding an edge to TargetSU from SU will
601 /// create a cycle. If so, it is not safe to call AddPred(TargetSU, SU).
603  // Is SU reachable from TargetSU via successor edges?
604  if (IsReachable(SU, TargetSU))
605  return true;
607  I = TargetSU->Preds.begin(), E = TargetSU->Preds.end(); I != E; ++I)
608  if (I->isAssignedRegDep() &&
609  IsReachable(SU, I->getSUnit()))
610  return true;
611  return false;
612 }
613 
614 /// IsReachable - Checks if SU is reachable from TargetSU.
616  const SUnit *TargetSU) {
617  // If insertion of the edge SU->TargetSU would create a cycle
618  // then there is a path from TargetSU to SU.
619  int UpperBound, LowerBound;
620  LowerBound = Node2Index[TargetSU->NodeNum];
621  UpperBound = Node2Index[SU->NodeNum];
622  bool HasLoop = false;
623  // Is Ord(TargetSU) < Ord(SU) ?
624  if (LowerBound < UpperBound) {
625  Visited.reset();
626  // There may be a path from TargetSU to SU. Check for it.
627  DFS(TargetSU, UpperBound, HasLoop);
628  }
629  return HasLoop;
630 }
631 
632 /// Allocate - assign the topological index to the node n.
633 void ScheduleDAGTopologicalSort::Allocate(int n, int index) {
634  Node2Index[n] = index;
635  Index2Node[index] = n;
636 }
637 
639 ScheduleDAGTopologicalSort(std::vector<SUnit> &sunits, SUnit *exitsu)
640  : SUnits(sunits), ExitSU(exitsu) {}
641 
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:210
BitVector & set()
Definition: BitVector.h:236
void reserve(unsigned N)
Definition: SmallVector.h:425
unsigned NumPreds
Definition: ScheduleDAG.h:273
void setSUnit(SUnit *SU)
Definition: ScheduleDAG.h:165
void removePred(const SDep &D)
SmallVector< SDep, 4 > Preds
Definition: ScheduleDAG.h:263
A register anti-dependedence (aka WAR).
Definition: ScheduleDAG.h:50
void dumpAll(const ScheduleDAG *G) const
bool isScheduled
Definition: ScheduleDAG.h:291
unsigned getHeight() const
Definition: ScheduleDAG.h:411
unsigned NumSuccs
Definition: ScheduleDAG.h:274
unsigned NumSuccsLeft
Definition: ScheduleDAG.h:276
bool isWeak() const
Definition: ScheduleDAG.h:198
const HexagonInstrInfo * TII
T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val()
Definition: SmallVector.h:430
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:49
#define G(x, y, z)
Definition: MD5.cpp:52
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:51
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:56
static cl::opt< bool > StressSchedOpt("stress-sched", cl::Hidden, cl::init(false), cl::desc("Stress test instruction scheduling"))
unsigned WeakSuccsLeft
Definition: ScheduleDAG.h:278
unsigned NumPredsLeft
Definition: ScheduleDAG.h:275
void setDepthToAtLeast(unsigned NewDepth)
void setHeightToAtLeast(unsigned NewHeight)
#define P(N)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:314
void setDepthDirty()
bool WillCreateCycle(SUnit *TargetSU, SUnit *SU)
WillCreateCycle - Return true if addPred(TargetSU, SU) creates a cycle.
void clearDAG()
clearDAG - clear the DAG state (between regions).
Definition: ScheduleDAG.cpp:50
unsigned short Latency
Definition: ScheduleDAG.h:280
ItTy next(ItTy it, Dist n)
Definition: STLExtras.h:154
BitVector & reset()
Definition: BitVector.h:275
unsigned getLatency() const
Definition: ScheduleDAG.h:150
void RemovePred(SUnit *M, SUnit *N)
Any other ordering dependency.
Definition: ScheduleDAG.h:52
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
unsigned WeakPredsLeft
Definition: ScheduleDAG.h:277
const unsigned MaxDepth
bool test(unsigned Idx) const
Definition: BitVector.h:337
raw_ostream & dbgs()
dbgs - Return a circular-buffered debug stream.
Definition: Debug.cpp:101
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:591
bool IsReachable(const SUnit *SU, const SUnit *TargetSU)
IsReachable - Checks if SU is reachable from TargetSU.
void biasCriticalPath()
Order this node's predecessor edges such that the critical path edge occurs first.
SUnit * getSUnit() const
Definition: ScheduleDAG.h:160
ScheduleDAG(MachineFunction &mf)
Definition: ScheduleDAG.cpp:36
unsigned getDepth() const
Definition: ScheduleDAG.h:403
unsigned VerifyScheduledDAG(bool isBottomUp)
const TargetRegisterInfo * TRI
Definition: ScheduleDAG.h:542
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
unsigned short NumRegDefsLeft
Definition: ScheduleDAG.h:279
Kind getKind() const
getKind - Return an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:170
const TargetInstrInfo * TII
Definition: ScheduleDAG.h:541
unsigned NodeNum
Definition: ScheduleDAG.h:271
void setHeightDirty()
virtual void dumpNode(const SUnit *SU) const =0
bool addPred(const SDep &D, bool Required=true)
Definition: ScheduleDAG.cpp:65
SmallVector< SDep, 4 > Succs
Definition: ScheduleDAG.h:264
void AddPred(SUnit *Y, SUnit *X)
virtual ~ScheduleDAG()
Definition: ScheduleDAG.cpp:47
const MCRegisterInfo & MRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
std::vector< SUnit > SUnits
Definition: ScheduleDAG.h:545
ScheduleDAGTopologicalSort(std::vector< SUnit > &SUnits, SUnit *ExitSU)
static RegisterPass< NVPTXAllocaHoisting > X("alloca-hoisting","Hoisting alloca instructions in non-entry ""blocks to the entry block")
void dump(const ScheduleDAG *G) const
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:249
bool isMachineOpcode() const
unsigned getMachineOpcode() const