37 unsigned DestReg,
unsigned SubIdx,
40 unsigned MIFlags)
const {
Thumb2RegisterInfo(const ARMSubtarget &STI)
const MachineFunction * getParent() const
The machine constant pool.
LLVMContext & getContext() const
const Function * getFunction() const
const HexagonInstrInfo * TII
const MachineInstrBuilder & addImm(int64_t Val) const
void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
unsigned getDefRegState(bool B)
bundle_iterator< MachineInstr, instr_iterator > iterator
LLVM Constant Representation.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
MachineConstantPool * getConstantPool()
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
const MCInstrDesc & get(unsigned Opcode) const
virtual const TargetInstrInfo * getInstrInfo() const
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
static IntegerType * getInt32Ty(LLVMContext &C)
const TargetMachine & getTarget() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)