10 #define DEBUG_TYPE "calcspillweights"
30 DEBUG(
dbgs() <<
"********** Compute Spill Weights **********\n"
31 <<
"********** Function: " << MF.
getName() <<
'\n');
35 for (
unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
37 if (MRI.reg_nodbg_empty(Reg))
47 unsigned sub, hreg, hsub;
62 return sub == hsub ? hreg : 0;
68 return rc->
contains(hreg) ? hreg : 0;
87 assert(MI &&
"Dead valno in interval");
101 bool isExiting =
false;
102 float totalWeight = 0;
106 float bestPhys = 0, bestVirt = 0;
107 unsigned hintPhys = 0, hintVirt = 0;
141 totalWeight += weight;
145 if (noHint || !mi->
isCopy())
150 float hweight = Hint[hint] += weight;
153 bestPhys = hweight, hintPhys = hint;
155 if (hweight > bestVirt)
156 bestVirt = hweight, hintVirt = hint;
163 if (
unsigned hint = hintPhys ? hintPhys : hintVirt) {
166 totalWeight *= 1.01F;
static float getSpillWeight(bool isDef, bool isUse, BlockFrequency freq)
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint...
SlotIndex def
The index of the defining instruction.
static unsigned index2VirtReg(unsigned Index)
float(* NormalizingFn)(float, unsigned)
bool isSpillable() const
isSpillable - Can this interval be spilled?
static bool isVirtualRegister(unsigned Reg)
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
bool isLoopExiting(const BlockT *BB) const
void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF, const MachineLoopInfo &MLI, const MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo::NormalizingFn norm=normalizeSpillWeight)
Compute spill weights and allocation hints for all virtual register live intervals.
static bool isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, const TargetInstrInfo &TII)
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
LoopInfoBase< BlockT, LoopT > * LI
const HexagonInstrInfo * TII
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned Reg) const
const TargetRegisterClass * getRegClass(unsigned Reg) const
void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg)
bool isUnused() const
Returns true if this value is unused.
static bool sub(uint64_t *dest, const uint64_t *x, const uint64_t *y, unsigned len)
Generalized subtraction of 64-bit integer arrays.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
VNInfoList::const_iterator const_vni_iterator
static unsigned copyHint(const MachineInstr *mi, unsigned reg, const TargetRegisterInfo &tri, const MachineRegisterInfo &mri)
const MachineBasicBlock * getParent() const
bool isDebugValue() const
bool isImplicitDef() const
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
SlotIndexes * getSlotIndexes() const
const MachineOperand & getOperand(unsigned i) const
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=0) const
unsigned getSubReg() const
virtual const TargetInstrInfo * getInstrInfo() const
void calculateSpillWeightAndHint(LiveInterval &li)
(re)compute li's spill weight and allocation hint.
bool isIdentityCopy() const
isIdentityCopy - Return true is the instruction is an identity copy.
bool isAllocatable(unsigned PhysReg) const
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs - Return a circular-buffered debug stream.
bool isZeroLength(SlotIndexes *Indexes) const
static bool isPhysicalRegister(unsigned Reg)
MachineRegisterInfo & getRegInfo()
const TargetMachine & getTarget() const
virtual const TargetRegisterInfo * getRegisterInfo() const
bool isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=0) const
unsigned getReg() const
getReg - Returns the register number.
AliasAnalysis * getAliasAnalysis() const
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
reg_iterator reg_begin(unsigned RegNo) const
const MCRegisterInfo & MRI
StringRef getName() const
tier< T1, T2 > tie(T1 &f, T2 &s)
bool contains(unsigned Reg) const