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CalcSpillWeights.cpp
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1 //===------------------------ CalcSpillWeights.cpp ------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #define DEBUG_TYPE "calcspillweights"
11 
18 #include "llvm/Support/Debug.h"
23 using namespace llvm;
24 
26  MachineFunction &MF,
27  const MachineLoopInfo &MLI,
28  const MachineBlockFrequencyInfo &MBFI,
30  DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
31  << "********** Function: " << MF.getName() << '\n');
32 
34  VirtRegAuxInfo VRAI(MF, LIS, MLI, MBFI, norm);
35  for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
37  if (MRI.reg_nodbg_empty(Reg))
38  continue;
40  }
41 }
42 
43 // Return the preferred allocation register for reg, given a COPY instruction.
44 static unsigned copyHint(const MachineInstr *mi, unsigned reg,
45  const TargetRegisterInfo &tri,
46  const MachineRegisterInfo &mri) {
47  unsigned sub, hreg, hsub;
48  if (mi->getOperand(0).getReg() == reg) {
49  sub = mi->getOperand(0).getSubReg();
50  hreg = mi->getOperand(1).getReg();
51  hsub = mi->getOperand(1).getSubReg();
52  } else {
53  sub = mi->getOperand(1).getSubReg();
54  hreg = mi->getOperand(0).getReg();
55  hsub = mi->getOperand(0).getSubReg();
56  }
57 
58  if (!hreg)
59  return 0;
60 
62  return sub == hsub ? hreg : 0;
63 
64  const TargetRegisterClass *rc = mri.getRegClass(reg);
65 
66  // Only allow physreg hints in rc.
67  if (sub == 0)
68  return rc->contains(hreg) ? hreg : 0;
69 
70  // reg:sub should match the physreg hreg.
71  return tri.getMatchingSuperReg(hreg, sub, rc);
72 }
73 
74 // Check if all values in LI are rematerializable
75 static bool isRematerializable(const LiveInterval &LI,
76  const LiveIntervals &LIS,
77  const TargetInstrInfo &TII) {
79  I != E; ++I) {
80  const VNInfo *VNI = *I;
81  if (VNI->isUnused())
82  continue;
83  if (VNI->isPHIDef())
84  return false;
85 
87  assert(MI && "Dead valno in interval");
88 
90  return false;
91  }
92  return true;
93 }
94 
95 void
97  MachineRegisterInfo &mri = MF.getRegInfo();
98  const TargetRegisterInfo &tri = *MF.getTarget().getRegisterInfo();
99  MachineBasicBlock *mbb = 0;
100  MachineLoop *loop = 0;
101  bool isExiting = false;
102  float totalWeight = 0;
104 
105  // Find the best physreg hint and the best virtreg hint.
106  float bestPhys = 0, bestVirt = 0;
107  unsigned hintPhys = 0, hintVirt = 0;
108 
109  // Don't recompute a target specific hint.
110  bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
111 
112  // Don't recompute spill weight for an unspillable register.
113  bool Spillable = li.isSpillable();
114 
116  MachineInstr *mi = I.skipInstruction();) {
117  if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugValue())
118  continue;
119  if (!visited.insert(mi))
120  continue;
121 
122  float weight = 1.0f;
123  if (Spillable) {
124  // Get loop info for mi.
125  if (mi->getParent() != mbb) {
126  mbb = mi->getParent();
127  loop = Loops.getLoopFor(mbb);
128  isExiting = loop ? loop->isLoopExiting(mbb) : false;
129  }
130 
131  // Calculate instr weight.
132  bool reads, writes;
133  tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg);
135  writes, reads, MBFI.getBlockFreq(mi->getParent()));
136 
137  // Give extra weight to what looks like a loop induction variable update.
138  if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
139  weight *= 3;
140 
141  totalWeight += weight;
142  }
143 
144  // Get allocation hints from copies.
145  if (noHint || !mi->isCopy())
146  continue;
147  unsigned hint = copyHint(mi, li.reg, tri, mri);
148  if (!hint)
149  continue;
150  float hweight = Hint[hint] += weight;
152  if (hweight > bestPhys && mri.isAllocatable(hint))
153  bestPhys = hweight, hintPhys = hint;
154  } else {
155  if (hweight > bestVirt)
156  bestVirt = hweight, hintVirt = hint;
157  }
158  }
159 
160  Hint.clear();
161 
162  // Always prefer the physreg hint.
163  if (unsigned hint = hintPhys ? hintPhys : hintVirt) {
164  mri.setRegAllocationHint(li.reg, 0, hint);
165  // Weakly boost the spill weight of hinted registers.
166  totalWeight *= 1.01F;
167  }
168 
169  // If the live interval was already unspillable, leave it that way.
170  if (!Spillable)
171  return;
172 
173  // Mark li as unspillable if all live ranges are tiny.
174  if (li.isZeroLength(LIS.getSlotIndexes())) {
175  li.markNotSpillable();
176  return;
177  }
178 
179  // If all of the definitions of the interval are re-materializable,
180  // it is a preferred candidate for spilling.
181  // FIXME: this gets much more complicated once we support non-trivial
182  // re-materialization.
183  if (isRematerializable(li, LIS, *MF.getTarget().getInstrInfo()))
184  totalWeight *= 0.5F;
185 
186  li.weight = normalize(totalWeight, li.getSize());
187 }
static float getSpillWeight(bool isDef, bool isUse, BlockFrequency freq)
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint...
const unsigned reg
Definition: LiveInterval.h:532
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:52
static unsigned index2VirtReg(unsigned Index)
float(* NormalizingFn)(float, unsigned)
vni_iterator vni_begin()
Definition: LiveInterval.h:200
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:543
static bool isVirtualRegister(unsigned Reg)
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
bool insert(PtrType Ptr)
Definition: SmallPtrSet.h:253
bool isLoopExiting(const BlockT *BB) const
Definition: LoopInfo.h:151
void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF, const MachineLoopInfo &MLI, const MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo::NormalizingFn norm=normalizeSpillWeight)
Compute spill weights and allocation hints for all virtual register live intervals.
static bool isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, const TargetInstrInfo &TII)
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
LoopInfoBase< BlockT, LoopT > * LI
Definition: LoopInfoImpl.h:411
const HexagonInstrInfo * TII
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned Reg) const
const TargetRegisterClass * getRegClass(unsigned Reg) const
unsigned getSize() const
void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg)
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:76
static bool sub(uint64_t *dest, const uint64_t *x, const uint64_t *y, unsigned len)
Generalized subtraction of 64-bit integer arrays.
Definition: APInt.cpp:264
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
VNInfoList::const_iterator const_vni_iterator
Definition: LiveInterval.h:203
static unsigned copyHint(const MachineInstr *mi, unsigned reg, const TargetRegisterInfo &tri, const MachineRegisterInfo &mri)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:119
bool isDebugValue() const
Definition: MachineInstr.h:639
bool isImplicitDef() const
Definition: MachineInstr.h:650
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
SlotIndexes * getSlotIndexes() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:267
bool isCopy() const
Definition: MachineInstr.h:669
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=0) const
unsigned getSubReg() const
bool isPHIDef() const
Definition: LiveInterval.h:73
virtual const TargetInstrInfo * getInstrInfo() const
void calculateSpillWeightAndHint(LiveInterval &li)
(re)compute li's spill weight and allocation hint.
bool isIdentityCopy() const
isIdentityCopy - Return true is the instruction is an identity copy.
Definition: MachineInstr.h:683
bool isAllocatable(unsigned PhysReg) const
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
Definition: LiveInterval.h:548
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs - Return a circular-buffered debug stream.
Definition: Debug.cpp:101
bool isZeroLength(SlotIndexes *Indexes) const
Definition: LiveInterval.h:486
static bool isPhysicalRegister(unsigned Reg)
MachineRegisterInfo & getRegInfo()
#define I(x, y, z)
Definition: MD5.cpp:54
const TargetMachine & getTarget() const
virtual const TargetRegisterInfo * getRegisterInfo() const
bool isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=0) const
unsigned getReg() const
getReg - Returns the register number.
AliasAnalysis * getAliasAnalysis() const
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
#define DEBUG(X)
Definition: Debug.h:97
reg_iterator reg_begin(unsigned RegNo) const
const MCRegisterInfo & MRI
StringRef getName() const
tier< T1, T2 > tie(T1 &f, T2 &s)
Definition: STLExtras.h:216
vni_iterator vni_end()
Definition: LiveInterval.h:201
bool contains(unsigned Reg) const