36 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
37 DFAStateEntryTable(SET) {}
49 void DFAPacketizer::ReadTable(
unsigned int state) {
50 unsigned ThisState = DFAStateEntryTable[state];
51 unsigned NextStateInTable = DFAStateEntryTable[state+1];
54 if (CachedTable.
count(UnsignPair(state,
55 DFAStateInputTable[ThisState][0])))
58 for (
unsigned i = ThisState; i < NextStateInTable; i++)
59 CachedTable[UnsignPair(state, DFAStateInputTable[i][0])] =
60 DFAStateInputTable[i][1];
70 UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
71 ReadTable(CurrentState);
72 return (CachedTable.
count(StateTrans) != 0);
82 UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
83 ReadTable(CurrentState);
84 assert(CachedTable.
count(StateTrans) != 0);
85 CurrentState = CachedTable[StateTrans];
130 bool IsPostRA) :
TM(MF.getTarget()), MF(MF) {
161 assert(
VLIWScheduler &&
"VLIW Scheduler is not initialized!");
164 std::distance(BeginItr, EndItr));
175 for (; BeginItr != EndItr; ++BeginItr) {
191 assert(SUI &&
"Missing SUnit Info!");
201 assert(SUJ &&
"Missing SUnit Info!");
bool canReserveResources(const llvm::MCInstrDesc *MID)
std::vector< MachineInstr * > CurrentPacketMIs
virtual void finishBlock()
finishBlock - Clean up after scheduling in the given block.
virtual void initPacketizerState()
MachineInstr * getInstr() const
bool CanHandleTerminators
DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, bool IsPostRA)
virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ)
const MCInstrDesc & getDesc() const
virtual void startBlock(MachineBasicBlock *BB)
startBlock - Prepare to perform scheduling in the given block.
virtual bool ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB)
std::map< MachineInstr *, SUnit * > MIToSUnit
const InstrStage * beginStage(unsigned ItinClassIndx) const
unsigned getUnits() const
getUnits - returns the choice of FUs
DFAPacketizer * ResourceTracker
const MachineLoopInfo & MLI
bool IsPostRA
isPostRA flag indicates vregs cannot be present.
void reserveResources(const llvm::MCInstrDesc *MID)
virtual void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the scheduler state for the next scheduling region.
virtual DFAPacketizer * CreateTargetScheduleState(const TargetMachine *, const ScheduleDAG *) const
Create machine specific model for scheduling.
bundle_iterator< MachineInstr, instr_iterator > iterator
virtual void exitRegion()
Notify that the scheduler has finished scheduling the current region.
bool count(const KeyT &Val) const
count - Return true if the specified key is in the map.
const MachineDominatorTree & MDT
virtual const TargetInstrInfo * getInstrInfo() const
const TargetInstrInfo * TII
virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ)
DFAPacketizer(const InstrItineraryData *I, const int(*SIT)[2], const unsigned *SET)
unsigned getSchedClass() const
Return the scheduling class for this instruction. The scheduling class is an index into the InstrItin...
void endPacket(MachineBasicBlock *MBB, MachineInstr *MI)
virtual bool isSoloInstruction(MachineInstr *MI)
VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, bool IsPostRA)
virtual ~VLIWPacketizerList()
std::vector< SUnit > SUnits
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker=0, PressureDiffs *PDiffs=0)
void PacketizeMIs(MachineBasicBlock *MBB, MachineBasicBlock::iterator BeginItr, MachineBasicBlock::iterator EndItr)
DefaultVLIWScheduler * VLIWScheduler
SUnit - Scheduling unit. This is a node in the scheduling DAG.
virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI)