42 #define GET_REGINFO_TARGET_DESC
43 #include "X86GenRegisterInfo.inc"
49 cl::desc(
"Force align the stack to the minimum alignment"
50 " needed for the function."),
55 cl::desc(
"Enable use of a base pointer for complex stack frames"));
59 ? X86::RIP : X86::EIP),
63 ? X86::RIP : X86::EIP)),
84 BasePtr = Is64Bit ? X86::RBX :
X86::ESI;
90 switch (getLLVMRegNum(RegNum, isEH)) {
91 case X86::EBX:
case X86::RBX:
return 1;
92 case X86::ECX:
case X86::R12:
return 2;
93 case X86::EDX:
case X86::R13:
return 3;
94 case X86::EDI:
case X86::R14:
return 4;
95 case X86::ESI:
case X86::R15:
return 5;
96 case X86::EBP:
case X86::RBP:
return 6;
110 return getEncodingValue(i);
115 unsigned Idx)
const {
118 if (!Is64Bit && Idx == X86::sub_8bit)
119 Idx = X86::sub_8bit_hi;
122 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
128 unsigned SubIdx)
const {
130 if (!Is64Bit && SubIdx == X86::sub_8bit) {
131 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
135 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
148 if (RC == &X86::GR8_NOREXRegClass)
154 switch (Super->
getID()) {
155 case X86::GR8RegClassID:
156 case X86::GR16RegClassID:
157 case X86::GR32RegClassID:
158 case X86::GR64RegClassID:
159 case X86::FR32RegClassID:
160 case X86::FR64RegClassID:
161 case X86::RFP32RegClassID:
162 case X86::RFP64RegClassID:
163 case X86::RFP80RegClassID:
164 case X86::VR128RegClassID:
165 case X86::VR256RegClassID:
184 return &X86::GR64RegClass;
185 return &X86::GR32RegClass;
188 return &X86::GR64_NOSPRegClass;
189 return &X86::GR32_NOSPRegClass;
192 return &X86::GR64_TCW64RegClass;
194 return &X86::GR64_TCRegClass;
199 return &X86::GR32RegClass;
200 return &X86::GR32_TCRegClass;
206 if (RC == &X86::CCRRegClass) {
208 return &X86::GR64RegClass;
210 return &X86::GR32RegClass;
220 unsigned FPDiff = TFI->
hasFP(MF) ? 1 : 0;
221 switch (RC->
getID()) {
224 case X86::GR32RegClassID:
226 case X86::GR64RegClassID:
228 case X86::VR128RegClassID:
230 case X86::VR64RegClassID:
240 return CSR_NoRegs_SaveList;
243 return CSR_64_SaveList;
245 return CSR_MostRegs_64_SaveList;
250 if (HasAVX512 && IsWin64)
251 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
252 if (HasAVX512 && Is64Bit)
253 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
254 if (HasAVX && IsWin64)
255 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
256 if (HasAVX && Is64Bit)
257 return CSR_64_Intel_OCL_BI_AVX_SaveList;
258 if (!HasAVX && !IsWin64 && Is64Bit)
259 return CSR_64_Intel_OCL_BI_SaveList;
265 return CSR_MostRegs_64_SaveList;
275 return CSR_Win64_SaveList;
277 return CSR_64EHRet_SaveList;
278 return CSR_64_SaveList;
281 return CSR_32EHRet_SaveList;
282 return CSR_32_SaveList;
291 if (IsWin64 && HasAVX512)
292 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
293 if (Is64Bit && HasAVX512)
294 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
295 if (IsWin64 && HasAVX)
296 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
297 if (Is64Bit && HasAVX)
298 return CSR_64_Intel_OCL_BI_AVX_RegMask;
299 if (!HasAVX && !IsWin64 && Is64Bit)
300 return CSR_64_Intel_OCL_BI_RegMask;
303 return CSR_NoRegs_RegMask;
305 return CSR_MostRegs_64_RegMask;
307 return CSR_32_RegMask;
309 return CSR_MostRegs_64_RegMask;
311 return CSR_Win64_RegMask;
312 return CSR_64_RegMask;
317 return CSR_NoRegs_RegMask;
335 if (TFI->
hasFP(MF)) {
347 "Stack realignment in presence of dynamic allocas is not supported with"
348 "this calling convention.");
356 Reserved.
set(X86::CS);
357 Reserved.
set(X86::SS);
358 Reserved.
set(X86::DS);
359 Reserved.
set(X86::ES);
364 for (
unsigned n = 0; n != 8; ++n)
365 Reserved.
set(X86::ST0 + n);
371 Reserved.
set(X86::SIL);
372 Reserved.
set(X86::DIL);
373 Reserved.
set(X86::BPL);
374 Reserved.
set(X86::SPL);
376 for (
unsigned n = 0; n != 8; ++n) {
387 for (
unsigned n = 16; n != 32; ++n) {
443 bool requiresRealignment =
456 unsigned Reg,
int &FrameIdx)
const {
459 if (Reg == FramePtr && TFI->
hasFP(MF)) {
468 int SPAdj,
unsigned FIOperandNum,
470 assert(SPAdj == 0 &&
"Unexpected");
479 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
483 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
487 BasePtr = (TFI->
hasFP(MF) ? FramePtr : StackPtr);
505 int Offset = FIOffset + Imm;
506 assert((!Is64Bit ||
isInt<32>((
long long)FIOffset + Imm)) &&
507 "Requesting 64-bit offset in 32-bit immediate!");
511 uint64_t Offset = FIOffset +
519 return TFI->
hasFP(MF) ? FramePtr : StackPtr;
531 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
533 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
535 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
537 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
539 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
541 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
543 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
545 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
551 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
553 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
555 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
557 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
559 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
561 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
563 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
565 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
567 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
569 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
571 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
573 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
575 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
577 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
579 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
581 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
588 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
590 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
592 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
594 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
596 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
598 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
600 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
602 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
604 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
606 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
608 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
610 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
612 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
614 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
616 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
618 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
624 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
626 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
628 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
630 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
632 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
634 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
636 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
638 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
640 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
642 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
644 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
646 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
648 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
650 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
652 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
654 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
660 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
662 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
664 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
666 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
668 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
670 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
672 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
674 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
676 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
678 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
680 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
682 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
684 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
686 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
688 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
690 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
697 if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
698 return X86::ZMM0 + (Reg - X86::XMM0);
699 if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
700 return X86::ZMM0 + (Reg - X86::YMM0);
701 if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
bool isInt< 32 >(int64_t x)
unsigned getStackAlignment() const
X86RegisterInfo(X86TargetMachine &tm)
const MachineFunction * getParent() const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC) const
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
bool hasBasePointer(const MachineFunction &MF) const
const Function * getFunction() const
unsigned getFrameRegister(const MachineFunction &MF) const
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
const uint32_t * getCallPreservedMask(CallingConv::ID) const
bool canReserveReg(unsigned PhysReg) const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
CallingConv::ID getCallingConv() const
unsigned getMaxAlignment() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
virtual bool hasFP(const MachineFunction &MF) const =0
#define llvm_unreachable(msg)
Abstract Stack Frame Information.
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
bool needsStackRealignment(const MachineFunction &MF) const
ID
LLVM Calling Convention Representation.
int getObjectIndexBegin() const
bool canRealignStack(const MachineFunction &MF) const
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
unsigned getDwarfRegFlavour(StringRef TT, bool isEH)
void ChangeToImmediate(int64_t ImmVal)
unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT, bool High)
const MachineBasicBlock * getParent() const
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
const MachineOperand & getOperand(unsigned i) const
unsigned get512BitSuperRegister(unsigned Reg)
BitVector getReservedRegs(const MachineFunction &MF) const
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
int64_t getOffset() const
void setOffset(int64_t Offset)
const TargetRegisterClass *const * sc_iterator
virtual const TargetFrameLowering * getFrameLowering() const
unsigned getBaseRegister() const
int64_t getObjectOffset(int ObjectIdx) const
bool callsEHReturn() const
void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI)
virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const
const STC & getSubtarget() const
int getOffsetOfLocalArea() const
int getSEHRegNum(unsigned i) const
MachineFrameInfo * getFrameInfo()
int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
AttributeSet getAttributes() const
Return the attribute list for this Function.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
const uint32_t * getNoPreservedMask() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
virtual const TargetFrameLowering * getFrameLowering() const
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
bool hasMSInlineAsm() const
Returns true if the function contains any MS-style inline assembly.
const TargetMachine & getTarget() const
const uint16_t * getCalleeSavedRegs(const MachineFunction *MF=0) const
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
bool hasVarSizedObjects() const
cl::opt< bool > ForceStackAlign("force-align-stack", cl::desc("Force align the stack to the minimum alignment"" needed for the function."), cl::init(false), cl::Hidden)
bool isTargetWin64() const
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=NULL) const
MachineModuleInfo & getMMI() const
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
const MCRegisterInfo & MRI
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
sc_iterator getSuperClasses() const