15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
514 bool hasSymbolicDisplacement =
true);
520 bool is64Bit,
bool IsVarArg,
bool TailCallOpt);
565 bool IsMemset,
bool ZeroMemset,
bool MemcpyStrSrc,
625 unsigned Depth = 0)
const;
630 unsigned Depth)
const;
644 AsmOperandInfo &
info,
const char *constraint)
const;
653 std::string &Constraint,
654 std::vector<SDValue> &Ops,
661 std::pair<unsigned, const TargetRegisterClass*>
738 return !X86ScalarSSEf64 || VT ==
MVT::f80;
748 return (VT ==
MVT::f64 && X86ScalarSSEf64) ||
749 (VT ==
MVT::f32 && X86ScalarSSEf32);
784 std::pair<const TargetRegisterClass*, uint8_t>
801 bool X86ScalarSSEf32;
802 bool X86ScalarSSEf64;
805 std::vector<APFloat> LegalFPImmediates;
809 void addLegalFPImmediate(
const APFloat& Imm) {
810 LegalFPImmediates.push_back(Imm);
813 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
815 const SmallVectorImpl<ISD::InputArg> &
Ins,
816 SDLoc dl, SelectionDAG &DAG,
817 SmallVectorImpl<SDValue> &InVals)
const;
818 SDValue LowerMemArgument(SDValue Chain,
820 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
821 SDLoc dl, SelectionDAG &DAG,
822 const CCValAssign &VA, MachineFrameInfo *MFI,
824 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
825 SDLoc dl, SelectionDAG &DAG,
826 const CCValAssign &VA,
827 ISD::ArgFlagsTy
Flags)
const;
834 bool IsEligibleForTailCallOptimization(SDValue Callee,
837 bool isCalleeStructRet,
838 bool isCallerStructRet,
840 const SmallVectorImpl<ISD::OutputArg> &Outs,
841 const SmallVectorImpl<SDValue> &OutVals,
842 const SmallVectorImpl<ISD::InputArg> &
Ins,
843 SelectionDAG& DAG)
const;
845 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
846 SDValue Chain,
bool IsTailCall,
bool Is64Bit,
847 int FPDiff, SDLoc dl)
const;
849 unsigned GetAlignedArgumentStackSize(
unsigned StackSize,
850 SelectionDAG &DAG)
const;
852 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
854 bool isReplace)
const;
856 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG)
const;
857 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG)
const;
858 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
const;
859 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
const;
860 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
const;
861 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG)
const;
862 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG)
const;
863 SDValue LowerGlobalAddress(
const GlobalValue *GV, SDLoc dl,
864 int64_t Offset, SelectionDAG &DAG)
const;
865 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
const;
866 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
const;
867 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG)
const;
868 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG)
const;
869 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG)
const;
870 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG)
const;
871 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG)
const;
872 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG)
const;
873 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG)
const;
874 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
const;
875 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
const;
876 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG)
const;
877 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG)
const;
878 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG)
const;
879 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
const;
881 SDLoc dl, SelectionDAG &DAG)
const;
882 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG)
const;
883 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG)
const;
884 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG)
const;
885 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG)
const;
886 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG)
const;
887 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
const;
888 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
const;
889 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
const;
890 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG)
const;
891 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG)
const;
892 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG)
const;
893 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
const;
894 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG)
const;
895 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG)
const;
896 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG)
const;
897 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG)
const;
898 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG)
const;
901 LowerFormalArguments(SDValue Chain,
903 const SmallVectorImpl<ISD::InputArg> &
Ins,
904 SDLoc dl, SelectionDAG &DAG,
905 SmallVectorImpl<SDValue> &InVals)
const;
907 LowerCall(CallLoweringInfo &CLI,
908 SmallVectorImpl<SDValue> &InVals)
const;
911 LowerReturn(SDValue Chain,
913 const SmallVectorImpl<ISD::OutputArg> &Outs,
914 const SmallVectorImpl<SDValue> &OutVals,
915 SDLoc dl, SelectionDAG &DAG)
const;
917 virtual bool isUsedByReturnOnly(SDNode *
N, SDValue &Chain)
const;
919 virtual bool mayBeEmittedAsTailCall(CallInst *CI)
const;
922 getTypeForExtArgOrReturn(MVT VT,
ISD::NodeType ExtendKind)
const;
927 const SmallVectorImpl<ISD::OutputArg> &Outs,
928 LLVMContext &Context)
const;
936 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *
MI,
937 MachineBasicBlock *MBB)
const;
941 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *
MI,
942 MachineBasicBlock *MBB)
const;
945 MachineBasicBlock *EmitVAARG64WithCustomInserter(
947 MachineBasicBlock *MBB)
const;
950 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
951 MachineInstr *BInstr,
952 MachineBasicBlock *BB)
const;
954 MachineBasicBlock *EmitLoweredSelect(MachineInstr *
I,
955 MachineBasicBlock *BB)
const;
957 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *
MI,
958 MachineBasicBlock *BB)
const;
960 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *
MI,
961 MachineBasicBlock *BB,
964 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *
MI,
965 MachineBasicBlock *BB)
const;
967 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *
MI,
968 MachineBasicBlock *BB)
const;
970 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *
MI,
971 MachineBasicBlock *MBB)
const;
973 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *
MI,
974 MachineBasicBlock *MBB)
const;
978 SDValue EmitTest(SDValue Op0,
unsigned X86CC, SelectionDAG &DAG)
const;
982 SDValue EmitCmp(SDValue Op0, SDValue Op1,
unsigned X86CC,
983 SelectionDAG &DAG)
const;
986 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG)
const;
991 const TargetLibraryInfo *libInfo);
995 #endif // X86ISELLOWERING_H
bool isVINSERT128Index(SDNode *N)
virtual bool ShouldShrinkFPConstant(EVT VT) const
PSIGN - Copy integer sign.
COFF::RelocationTypeX86 Type
virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const
PSHUFB - Shuffle 16 8-bit values within a vector.
virtual void resetOperationActions()
Reset the operation actions based on target options.
virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const
bool isVEXTRACT128Index(SDNode *N)
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, unsigned Depth) const
BLENDV - Blend where the selector is a register.
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const
unsigned getInsertVINSERT128Immediate(SDNode *N)
virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
FHSUB - Floating point horizontal sub.
const X86Subtarget * getSubtarget() const
HSUB - Integer horizontal sub.
virtual bool isZExtFree(Type *Ty1, Type *Ty2) const
virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const
X86 bit-test instructions.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(MVT VT) const
bool isVINSERT256Index(SDNode *N)
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
virtual bool isShuffleMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const
unsigned getExtractVEXTRACT128Immediate(SDNode *N)
ID
LLVM Calling Convention Representation.
HADD - Integer horizontal add.
X86TargetLowering(X86TargetMachine &TM)
X86 compare and logical compare instructions.
virtual bool isVectorClearMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const
virtual bool isSafeMemOpType(MVT VT) const
ConstraintType getConstraintType(const std::string &Constraint) const
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const
FMAXC, FMINC - Commutative FMIN and FMAX.
SMAX, SMIN - Signed integer max and min.
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
bool isIntegerTypeFTOL(EVT VT) const
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const
getSetCCResultType - Return the value type to use for ISD::SETCC.
virtual const char * LowerXConstraint(EVT ConstraintVT) const
virtual bool ExpandInlineAsm(CallInst *CI) const
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
virtual unsigned getJumpTableEncoding() const
virtual bool isLegalICmpImmediate(int64_t Imm) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const
virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const
REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
BLENDI - Blend where the selector is an immediate.
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const
virtual const char * getTargetNodeName(unsigned Opcode) const
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const
bool isTargetWindows() const
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const LLVM_OVERRIDE
Returns true if a cast between SrcAS and DestAS is a noop.
bool isVEXTRACT256Index(SDNode *N)
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
virtual bool isLegalAddImmediate(int64_t Imm) const
virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const
unsigned getExtractVEXTRACT256Immediate(SDNode *N)
static const int FIRST_TARGET_MEMORY_OPCODE
Class for arbitrary precision integers.
AddrMode
ARM Addressing Modes.
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
UMAX, UMIN - Unsigned integer max and min.
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
virtual void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const
ANDNP - Bitwise Logical AND NOT of Packed FP values.
virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
unsigned getInsertVINSERT256Immediate(SDNode *N)
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool TailCallOpt)
virtual FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
FHADD - Floating point horizontal add.
bool isZeroNode(SDValue Elt)
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement=true)
virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const
bool isTargetFTOL() const
virtual unsigned getByValTypeAlignment(Type *Ty) const
bool isScalarFPTypeInSSEReg(EVT VT) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)