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X86ISelLowering.h
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1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef X86ISELLOWERING_H
16 #define X86ISELLOWERING_H
17 
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
22 #include "llvm/CodeGen/FastISel.h"
26 
27 namespace llvm {
28  namespace X86ISD {
29  // X86 Specific DAG Nodes
30  enum NodeType {
31  // Start the numbering where the builtin ops leave off.
33 
34  /// BSF - Bit scan forward.
35  /// BSR - Bit scan reverse.
36  BSF,
37  BSR,
38 
39  /// SHLD, SHRD - Double shift instructions. These correspond to
40  /// X86::SHLDxx and X86::SHRDxx instructions.
43 
44  /// FAND - Bitwise logical AND of floating point values. This corresponds
45  /// to X86::ANDPS or X86::ANDPD.
47 
48  /// FOR - Bitwise logical OR of floating point values. This corresponds
49  /// to X86::ORPS or X86::ORPD.
50  FOR,
51 
52  /// FXOR - Bitwise logical XOR of floating point values. This corresponds
53  /// to X86::XORPS or X86::XORPD.
55 
56  /// FANDN - Bitwise logical ANDNOT of floating point values. This
57  /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 
60  /// FSRL - Bitwise logical right shift of floating point values. These
61  /// corresponds to X86::PSRLDQ.
63 
64  /// CALL - These operations represent an abstract X86 call
65  /// instruction, which includes a bunch of information. In particular the
66  /// operands of these node are:
67  ///
68  /// #0 - The incoming token chain
69  /// #1 - The callee
70  /// #2 - The number of arg bytes the caller pushes on the stack.
71  /// #3 - The number of arg bytes the callee pops off the stack.
72  /// #4 - The value to pass in AL/AX/EAX (optional)
73  /// #5 - The value to pass in DL/DX/EDX (optional)
74  ///
75  /// The result values of these nodes are:
76  ///
77  /// #0 - The outgoing token chain
78  /// #1 - The first register result value (optional)
79  /// #2 - The second register result value (optional)
80  ///
82 
83  /// RDTSC_DAG - This operation implements the lowering for
84  /// readcyclecounter
86 
87  /// X86 compare and logical compare instructions.
89 
90  /// X86 bit-test instructions.
91  BT,
92 
93  /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94  /// operand, usually produced by a CMP instruction.
96 
97  // Same as SETCC except it's materialized with a sbb and the value is all
98  // one's or all zero's.
99  SETCC_CARRY, // R = carry_bit ? ~0 : 0
100 
101  /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
102  /// Operands are two FP values to compare; result is a mask of
103  /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
105 
106  /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
107  /// result in an integer GPR. Needs masking for scalar result.
109 
110  /// X86 conditional moves. Operand 0 and operand 1 are the two values
111  /// to select from. Operand 2 is the condition code, and operand 3 is the
112  /// flag operand produced by a CMP or TEST instruction. It also writes a
113  /// flag result.
115 
116  /// X86 conditional branches. Operand 0 is the chain operand, operand 1
117  /// is the block to branch if condition is true, operand 2 is the
118  /// condition code, and operand 3 is the flag operand produced by a CMP
119  /// or TEST instruction.
121 
122  /// Return with a flag operand. Operand 0 is the chain operand, operand
123  /// 1 is the number of bytes of stack to pop.
125 
126  /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
128 
129  /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
131 
132  /// GlobalBaseReg - On Darwin, this node represents the result of the popl
133  /// at function entry, used for PIC code.
135 
136  /// Wrapper - A wrapper node for TargetConstantPool,
137  /// TargetExternalSymbol, and TargetGlobalAddress.
139 
140  /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
141  /// relative displacements.
143 
144  /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
145  /// to an MMX vector. If you think this is too close to the previous
146  /// mnemonic, so do I; blame Intel.
148 
149  /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
150  /// vector to a GPR.
152 
153  /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
154  /// i32, corresponds to X86::PEXTRB.
156 
157  /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
158  /// i32, corresponds to X86::PEXTRW.
160 
161  /// INSERTPS - Insert any element of a 4 x float vector into any element
162  /// of a destination 4 x floatvector.
164 
165  /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
166  /// corresponds to X86::PINSRB.
168 
169  /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
170  /// corresponds to X86::PINSRW.
172 
173  /// PSHUFB - Shuffle 16 8-bit values within a vector.
175 
176  /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
178 
179  /// PSIGN - Copy integer sign.
181 
182  /// BLENDV - Blend where the selector is a register.
184 
185  /// BLENDI - Blend where the selector is an immediate.
187 
188  // SUBUS - Integer sub with unsigned saturation.
190 
191  /// HADD - Integer horizontal add.
193 
194  /// HSUB - Integer horizontal sub.
196 
197  /// FHADD - Floating point horizontal add.
199 
200  /// FHSUB - Floating point horizontal sub.
202 
203  /// UMAX, UMIN - Unsigned integer max and min.
205 
206  /// SMAX, SMIN - Signed integer max and min.
208 
209  /// FMAX, FMIN - Floating point max and min.
210  ///
212 
213  /// FMAXC, FMINC - Commutative FMIN and FMAX.
215 
216  /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
217  /// approximation. Note that these typically require refinement
218  /// in order to obtain suitable precision.
220 
221  // TLSADDR - Thread Local Storage.
223 
224  // TLSBASEADDR - Thread Local Storage. A call to get the start address
225  // of the TLS block for the current module.
227 
228  // TLSCALL - Thread Local Storage. When calling to an OS provided
229  // thunk at the address from an earlier relocation.
231 
232  // EH_RETURN - Exception Handling helpers.
234 
235  // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
237 
238  // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
240 
241  /// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for
242  /// the list of operands.
244 
245  // VZEXT_MOVL - Vector move low and zero extend.
247 
248  // VSEXT_MOVL - Vector move low and sign extend.
250 
251  // VZEXT - Vector integer zero-extend.
253 
254  // VSEXT - Vector integer signed-extend.
256 
257  // VTRUNC - Vector integer truncate.
259 
260  // VTRUNC - Vector integer truncate with mask.
262 
263  // VFPEXT - Vector FP extend.
265 
266  // VFPROUND - Vector FP round.
268 
269  // VSHL, VSRL - 128-bit vector logical left / right shift
271 
272  // VSHL, VSRL, VSRA - Vector shift elements
274 
275  // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
277 
278  // CMPP - Vector packed double/float comparison.
280 
281  // PCMP* - Vector integer comparisons.
283  // PCMP*M - Vector integer comparisons, the result is in a mask vector.
285 
286  /// CMPM, CMPMU - Vector comparison generating mask bits for fp and
287  /// integer signed and unsigned data types.
290 
291  // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
293  INC, DEC, OR, XOR, AND,
294 
295  BLSI, // BLSI - Extract lowest set isolated bit
296  BLSMSK, // BLSMSK - Get mask up to lowest set bit
297  BLSR, // BLSR - Reset lowest set bit
298  BZHI, // BZHI - Zero high bits
299  BEXTR, // BEXTR - Bit field extract
300 
301  UMUL, // LOW, HI, FLAGS = umul LHS, RHS
302 
303  // MUL_IMM - X86 specific multiply by immediate.
305 
306  // PTEST - Vector bitwise comparisons.
308 
309  // TESTP - Vector packed fp sign bitwise comparisons.
311 
312  // TESTM - Vector "test" in AVX-512, the result is in a mask vector.
314 
315  // OR/AND test for masks
318 
319  // Several flavors of instructions with vector shuffle behaviors.
343  // masked broadcast
346 
347  // PMULUDQ - Vector multiply packed unsigned doubleword integers
349 
350  // FMA nodes
357 
358  // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
359  // according to %al. An operator is needed so that this can be expanded
360  // with control flow.
362 
363  // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
365 
366  // SEG_ALLOCA - For allocating variable amounts of stack space when using
367  // segmented stacks. Check if the current stacklet has enough space, and
368  // falls back to heap allocation if not.
370 
371  // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
373 
374  // Memory barrier
379 
380  // FNSTSW16r - Store FP status word into i16 register.
382 
383  // SAHF - Store contents of %ah into %eflags.
385 
386  // RDRAND - Get a random integer and indicate whether it is valid in CF.
388 
389  // RDSEED - Get a NIST SP800-90B & C compliant random integer and
390  // indicate whether it is valid in CF.
392 
393  // PCMP*STRI
396 
397  // XTEST - Test if in transactional execution.
399 
400  // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
401  // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
402  // Atomic 64-bit binary operations.
414 
415  // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
419 
420  // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
422 
423  // FNSTCW16m - Store FP control world into i16 memory.
425 
426  /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
427  /// integer destination in memory and a FP reg source. This corresponds
428  /// to the X86::FIST*m instructions and the rounding mode change stuff. It
429  /// has two inputs (token chain and address) and two outputs (int value
430  /// and token chain).
434 
435  /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
436  /// integer source in memory and FP reg result. This corresponds to the
437  /// X86::FILD*m instructions. It has three inputs (token chain, address,
438  /// and source type) and two outputs (FP value and token chain). FILD_FLAG
439  /// also produces a flag).
442 
443  /// FLD - This instruction implements an extending load to FP stack slots.
444  /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
445  /// operand, ptr to load from, and a ValueType node indicating the type
446  /// to load to.
448 
449  /// FST - This instruction implements a truncating store to FP stack
450  /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
451  /// chain operand, value to store, address, and a ValueType to store it
452  /// as.
454 
455  /// VAARG_64 - This instruction grabs the address of the next argument
456  /// from a va_list. (reads and modifies the va_list in memory)
458 
459  // WARNING: Do not add anything in the end unless you want the node to
460  // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
461  // thought as target memory ops!
462  };
463  }
464 
465  /// Define some predicates that are used for node matching.
466  namespace X86 {
467  /// isVEXTRACT128Index - Return true if the specified
468  /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
469  /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
470  bool isVEXTRACT128Index(SDNode *N);
471 
472  /// isVINSERT128Index - Return true if the specified
473  /// INSERT_SUBVECTOR operand specifies a subvector insert that is
474  /// suitable for input to VINSERTF128, VINSERTI128 instructions.
475  bool isVINSERT128Index(SDNode *N);
476 
477  /// isVEXTRACT256Index - Return true if the specified
478  /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
479  /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
480  bool isVEXTRACT256Index(SDNode *N);
481 
482  /// isVINSERT256Index - Return true if the specified
483  /// INSERT_SUBVECTOR operand specifies a subvector insert that is
484  /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
485  bool isVINSERT256Index(SDNode *N);
486 
487  /// getExtractVEXTRACT128Immediate - Return the appropriate
488  /// immediate to extract the specified EXTRACT_SUBVECTOR index
489  /// with VEXTRACTF128, VEXTRACTI128 instructions.
490  unsigned getExtractVEXTRACT128Immediate(SDNode *N);
491 
492  /// getInsertVINSERT128Immediate - Return the appropriate
493  /// immediate to insert at the specified INSERT_SUBVECTOR index
494  /// with VINSERTF128, VINSERT128 instructions.
495  unsigned getInsertVINSERT128Immediate(SDNode *N);
496 
497  /// getExtractVEXTRACT256Immediate - Return the appropriate
498  /// immediate to extract the specified EXTRACT_SUBVECTOR index
499  /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
500  unsigned getExtractVEXTRACT256Immediate(SDNode *N);
501 
502  /// getInsertVINSERT256Immediate - Return the appropriate
503  /// immediate to insert at the specified INSERT_SUBVECTOR index
504  /// with VINSERTF64x4, VINSERTI64x4 instructions.
505  unsigned getInsertVINSERT256Immediate(SDNode *N);
506 
507  /// isZeroNode - Returns true if Elt is a constant zero or a floating point
508  /// constant +0.0.
509  bool isZeroNode(SDValue Elt);
510 
511  /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
512  /// fit into displacement field of the instruction.
513  bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
514  bool hasSymbolicDisplacement = true);
515 
516 
517  /// isCalleePop - Determines whether the callee is required to pop its
518  /// own arguments. Callee pop is necessary to support tail calls.
519  bool isCalleePop(CallingConv::ID CallingConv,
520  bool is64Bit, bool IsVarArg, bool TailCallOpt);
521  }
522 
523  //===--------------------------------------------------------------------===//
524  // X86TargetLowering - X86 Implementation of the TargetLowering interface
526  public:
527  explicit X86TargetLowering(X86TargetMachine &TM);
528 
529  virtual unsigned getJumpTableEncoding() const;
530 
531  virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
532 
533  virtual const MCExpr *
535  const MachineBasicBlock *MBB, unsigned uid,
536  MCContext &Ctx) const;
537 
538  /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
539  /// jumptable.
541  SelectionDAG &DAG) const;
542  virtual const MCExpr *
544  unsigned JTI, MCContext &Ctx) const;
545 
546  /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
547  /// function arguments in the caller parameter area. For X86, aggregates
548  /// that contains are placed at 16-byte boundaries while the rest are at
549  /// 4-byte boundaries.
550  virtual unsigned getByValTypeAlignment(Type *Ty) const;
551 
552  /// getOptimalMemOpType - Returns the target specific optimal type for load
553  /// and store operations as a result of memset, memcpy, and memmove
554  /// lowering. If DstAlign is zero that means it's safe to destination
555  /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
556  /// means there isn't a need to check it against alignment requirement,
557  /// probably because the source does not need to be loaded. If 'IsMemset' is
558  /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
559  /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
560  /// source is constant so it does not need to be loaded.
561  /// It returns EVT::Other if the type should be determined using generic
562  /// target-independent logic.
563  virtual EVT
564  getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
565  bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
566  MachineFunction &MF) const;
567 
568  /// isSafeMemOpType - Returns true if it's safe to use load / store of the
569  /// specified type to expand memcpy / memset inline. This is mostly true
570  /// for all types except for some special cases. For example, on X86
571  /// targets without SSE2 f64 load / store are done with fldl / fstpl which
572  /// also does type conversion. Note the specified type doesn't have to be
573  /// legal as the hook is used before type legalization.
574  virtual bool isSafeMemOpType(MVT VT) const;
575 
576  /// allowsUnalignedMemoryAccesses - Returns true if the target allows
577  /// unaligned memory accesses. of the specified type. Returns whether it
578  /// is "fast" by reference in the second argument.
579  virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
580 
581  /// LowerOperation - Provide custom lowering hooks for some operations.
582  ///
583  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
584 
585  /// ReplaceNodeResults - Replace the results of node with an illegal result
586  /// type with new values built out of custom code.
587  ///
588  virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
589  SelectionDAG &DAG) const;
590 
591 
592  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
593 
594  /// isTypeDesirableForOp - Return true if the target has native support for
595  /// the specified value type and it is 'desirable' to use the type for the
596  /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
597  /// instruction encodings are longer and some i16 instructions are slow.
598  virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
599 
600  /// isTypeDesirable - Return true if the target has native support for the
601  /// specified value type and it is 'desirable' to use the type. e.g. On x86
602  /// i16 is legal, but undesirable since i16 instruction encodings are longer
603  /// and some i16 instructions are slow.
604  virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
605 
606  virtual MachineBasicBlock *
608  MachineBasicBlock *MBB) const;
609 
610 
611  /// getTargetNodeName - This method returns the name of a target specific
612  /// DAG node.
613  virtual const char *getTargetNodeName(unsigned Opcode) const;
614 
615  /// getSetCCResultType - Return the value type to use for ISD::SETCC.
616  virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
617 
618  /// computeMaskedBitsForTargetNode - Determine which of the bits specified
619  /// in Mask are known to be either zero or one and return them in the
620  /// KnownZero/KnownOne bitsets.
621  virtual void computeMaskedBitsForTargetNode(const SDValue Op,
622  APInt &KnownZero,
623  APInt &KnownOne,
624  const SelectionDAG &DAG,
625  unsigned Depth = 0) const;
626 
627  // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
628  // operation that are sign bits.
629  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
630  unsigned Depth) const;
631 
632  virtual bool
633  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
634 
636 
637  virtual bool ExpandInlineAsm(CallInst *CI) const;
638 
639  ConstraintType getConstraintType(const std::string &Constraint) const;
640 
641  /// Examine constraint string and operand type and determine a weight value.
642  /// The operand object must already have been set up with the operand type.
644  AsmOperandInfo &info, const char *constraint) const;
645 
646  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
647 
648  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
649  /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
650  /// true it means one of the asm constraint of the inline asm instruction
651  /// being processed is 'm'.
652  virtual void LowerAsmOperandForConstraint(SDValue Op,
653  std::string &Constraint,
654  std::vector<SDValue> &Ops,
655  SelectionDAG &DAG) const;
656 
657  /// getRegForInlineAsmConstraint - Given a physical register constraint
658  /// (e.g. {edx}), return the register number and the register class for the
659  /// register. This should only be used for C_Register constraints. On
660  /// error, this returns a register number of 0.
661  std::pair<unsigned, const TargetRegisterClass*>
662  getRegForInlineAsmConstraint(const std::string &Constraint,
663  MVT VT) const;
664 
665  /// isLegalAddressingMode - Return true if the addressing mode represented
666  /// by AM is legal for this target, for a load/store of the specified type.
667  virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
668 
669  /// isLegalICmpImmediate - Return true if the specified immediate is legal
670  /// icmp immediate, that is the target has icmp instructions which can
671  /// compare a register against the immediate without having to materialize
672  /// the immediate into a register.
673  virtual bool isLegalICmpImmediate(int64_t Imm) const;
674 
675  /// isLegalAddImmediate - Return true if the specified immediate is legal
676  /// add immediate, that is the target has add instructions which can
677  /// add a register and the immediate without having to materialize
678  /// the immediate into a register.
679  virtual bool isLegalAddImmediate(int64_t Imm) const;
680 
681  /// isTruncateFree - Return true if it's free to truncate a value of
682  /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
683  /// register EAX to i16 by referencing its sub-register AX.
684  virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
685  virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
686 
687  virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
688 
689  /// isZExtFree - Return true if any actual instruction that defines a
690  /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
691  /// register. This does not necessarily include registers defined in
692  /// unknown ways, such as incoming arguments, or copies from unknown
693  /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
694  /// does not necessarily apply to truncate instructions. e.g. on x86-64,
695  /// all instructions that define 32-bit values implicit zero-extend the
696  /// result out to 64 bits.
697  virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
698  virtual bool isZExtFree(EVT VT1, EVT VT2) const;
699  virtual bool isZExtFree(SDValue Val, EVT VT2) const;
700 
701  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
702  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
703  /// expanded to FMAs when this method returns true, otherwise fmuladd is
704  /// expanded to fmul + fadd.
705  virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
706 
707  /// isNarrowingProfitable - Return true if it's profitable to narrow
708  /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
709  /// from i32 to i8 but not from i32 to i16.
710  virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
711 
712  /// isFPImmLegal - Returns true if the target can instruction select the
713  /// specified FP immediate natively. If false, the legalizer will
714  /// materialize the FP immediate as a load from a constant pool.
715  virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
716 
717  /// isShuffleMaskLegal - Targets can use this to indicate that they only
718  /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
719  /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
720  /// values are assumed to be legal.
721  virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
722  EVT VT) const;
723 
724  /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
725  /// used by Targets can use this to indicate if there is a suitable
726  /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
727  /// pool entry.
728  virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
729  EVT VT) const;
730 
731  /// ShouldShrinkFPConstant - If true, then instruction selection should
732  /// seek to shrink the FP constant of the specified type to a smaller type
733  /// in order to save space and / or reduce runtime.
734  virtual bool ShouldShrinkFPConstant(EVT VT) const {
735  // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
736  // expensive than a straight movsd. On the other hand, it's important to
737  // shrink long double fp constant since fldt is very slow.
738  return !X86ScalarSSEf64 || VT == MVT::f80;
739  }
740 
741  const X86Subtarget* getSubtarget() const {
742  return Subtarget;
743  }
744 
745  /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
746  /// computed in an SSE register, not on the X87 floating point stack.
747  bool isScalarFPTypeInSSEReg(EVT VT) const {
748  return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
749  (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
750  }
751 
752  /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
753  /// for fptoui.
754  bool isTargetFTOL() const {
755  return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
756  }
757 
758  /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
759  /// used for fptoui to the given type.
760  bool isIntegerTypeFTOL(EVT VT) const {
761  return isTargetFTOL() && VT == MVT::i64;
762  }
763 
764  /// createFastISel - This method returns a target specific FastISel object,
765  /// or null if the target does not support "fast" ISel.
766  virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
767  const TargetLibraryInfo *libInfo) const;
768 
769  /// getStackCookieLocation - Return true if the target stores stack
770  /// protector cookies at a fixed offset in some non-standard address
771  /// space, and populates the address space and offset as
772  /// appropriate.
773  virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
774 
775  SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
776  SelectionDAG &DAG) const;
777 
778  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const LLVM_OVERRIDE;
779 
780  /// \brief Reset the operation actions based on target options.
781  virtual void resetOperationActions();
782 
783  protected:
784  std::pair<const TargetRegisterClass*, uint8_t>
785  findRepresentativeClass(MVT VT) const;
786 
787  private:
788  /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
789  /// make the right decision when generating code for different targets.
790  const X86Subtarget *Subtarget;
791  const DataLayout *TD;
792 
793  /// Used to store the TargetOptions so that we don't waste time resetting
794  /// the operation actions unless we have to.
795  TargetOptions TO;
796 
797  /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
798  /// floating point ops.
799  /// When SSE is available, use it for f32 operations.
800  /// When SSE2 is available, use it for f64 operations.
801  bool X86ScalarSSEf32;
802  bool X86ScalarSSEf64;
803 
804  /// LegalFPImmediates - A list of legal fp immediates.
805  std::vector<APFloat> LegalFPImmediates;
806 
807  /// addLegalFPImmediate - Indicate that this x86 target can instruction
808  /// select the specified FP immediate natively.
809  void addLegalFPImmediate(const APFloat& Imm) {
810  LegalFPImmediates.push_back(Imm);
811  }
812 
813  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
814  CallingConv::ID CallConv, bool isVarArg,
815  const SmallVectorImpl<ISD::InputArg> &Ins,
816  SDLoc dl, SelectionDAG &DAG,
817  SmallVectorImpl<SDValue> &InVals) const;
818  SDValue LowerMemArgument(SDValue Chain,
819  CallingConv::ID CallConv,
820  const SmallVectorImpl<ISD::InputArg> &ArgInfo,
821  SDLoc dl, SelectionDAG &DAG,
822  const CCValAssign &VA, MachineFrameInfo *MFI,
823  unsigned i) const;
824  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
825  SDLoc dl, SelectionDAG &DAG,
826  const CCValAssign &VA,
827  ISD::ArgFlagsTy Flags) const;
828 
829  // Call lowering helpers.
830 
831  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
832  /// for tail call optimization. Targets which want to do tail call
833  /// optimization should implement this function.
834  bool IsEligibleForTailCallOptimization(SDValue Callee,
835  CallingConv::ID CalleeCC,
836  bool isVarArg,
837  bool isCalleeStructRet,
838  bool isCallerStructRet,
839  Type *RetTy,
840  const SmallVectorImpl<ISD::OutputArg> &Outs,
841  const SmallVectorImpl<SDValue> &OutVals,
842  const SmallVectorImpl<ISD::InputArg> &Ins,
843  SelectionDAG& DAG) const;
844  bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
845  SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
846  SDValue Chain, bool IsTailCall, bool Is64Bit,
847  int FPDiff, SDLoc dl) const;
848 
849  unsigned GetAlignedArgumentStackSize(unsigned StackSize,
850  SelectionDAG &DAG) const;
851 
852  std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
853  bool isSigned,
854  bool isReplace) const;
855 
856  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
857  SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
858  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
859  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
860  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
861  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
862  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
863  SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
864  int64_t Offset, SelectionDAG &DAG) const;
865  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
866  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
867  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
868  SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
869  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
870  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
871  SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
872  SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
873  SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
874  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
875  SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
876  SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
877  SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
878  SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
879  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
880  SDValue LowerToBT(SDValue And, ISD::CondCode CC,
881  SDLoc dl, SelectionDAG &DAG) const;
882  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
883  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
884  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
885  SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
886  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
887  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
888  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
889  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
890  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
891  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
892  SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
893  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
894  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
895  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
896  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
897  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
898  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
899 
900  virtual SDValue
901  LowerFormalArguments(SDValue Chain,
902  CallingConv::ID CallConv, bool isVarArg,
903  const SmallVectorImpl<ISD::InputArg> &Ins,
904  SDLoc dl, SelectionDAG &DAG,
905  SmallVectorImpl<SDValue> &InVals) const;
906  virtual SDValue
907  LowerCall(CallLoweringInfo &CLI,
908  SmallVectorImpl<SDValue> &InVals) const;
909 
910  virtual SDValue
911  LowerReturn(SDValue Chain,
912  CallingConv::ID CallConv, bool isVarArg,
913  const SmallVectorImpl<ISD::OutputArg> &Outs,
914  const SmallVectorImpl<SDValue> &OutVals,
915  SDLoc dl, SelectionDAG &DAG) const;
916 
917  virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
918 
919  virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
920 
921  virtual MVT
922  getTypeForExtArgOrReturn(MVT VT, ISD::NodeType ExtendKind) const;
923 
924  virtual bool
925  CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
926  bool isVarArg,
927  const SmallVectorImpl<ISD::OutputArg> &Outs,
928  LLVMContext &Context) const;
929 
930  virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const;
931 
932  /// Utility function to emit atomic-load-arith operations (and, or, xor,
933  /// nand, max, min, umax, umin). It takes the corresponding instruction to
934  /// expand, the associated machine basic block, and the associated X86
935  /// opcodes for reg/reg.
936  MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
937  MachineBasicBlock *MBB) const;
938 
939  /// Utility function to emit atomic-load-arith operations (and, or, xor,
940  /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
941  MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
942  MachineBasicBlock *MBB) const;
943 
944  // Utility function to emit the low-level va_arg code for X86-64.
945  MachineBasicBlock *EmitVAARG64WithCustomInserter(
946  MachineInstr *MI,
947  MachineBasicBlock *MBB) const;
948 
949  /// Utility function to emit the xmm reg save portion of va_start.
950  MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
951  MachineInstr *BInstr,
952  MachineBasicBlock *BB) const;
953 
954  MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
955  MachineBasicBlock *BB) const;
956 
957  MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
958  MachineBasicBlock *BB) const;
959 
960  MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
961  MachineBasicBlock *BB,
962  bool Is64Bit) const;
963 
964  MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
965  MachineBasicBlock *BB) const;
966 
967  MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
968  MachineBasicBlock *BB) const;
969 
970  MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
971  MachineBasicBlock *MBB) const;
972 
973  MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
974  MachineBasicBlock *MBB) const;
975 
976  /// Emit nodes that will be selected as "test Op0,Op0", or something
977  /// equivalent, for use with the given x86 condition code.
978  SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
979 
980  /// Emit nodes that will be selected as "cmp Op0,Op1", or something
981  /// equivalent, for use with the given x86 condition code.
982  SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
983  SelectionDAG &DAG) const;
984 
985  /// Convert a comparison if required by the subtarget.
986  SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
987  };
988 
989  namespace X86 {
990  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
991  const TargetLibraryInfo *libInfo);
992  }
993 }
994 
995 #endif // X86ISELLOWERING_H
bool isVINSERT128Index(SDNode *N)
virtual bool ShouldShrinkFPConstant(EVT VT) const
PSIGN - Copy integer sign.
COFF::RelocationTypeX86 Type
Definition: COFFYAML.cpp:227
virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const
PSHUFB - Shuffle 16 8-bit values within a vector.
virtual void resetOperationActions()
Reset the operation actions based on target options.
virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const
bool isVEXTRACT128Index(SDNode *N)
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, unsigned Depth) const
BLENDV - Blend where the selector is a register.
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const
unsigned getInsertVINSERT128Immediate(SDNode *N)
virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
FHSUB - Floating point horizontal sub.
const X86Subtarget * getSubtarget() const
HSUB - Integer horizontal sub.
virtual bool isZExtFree(Type *Ty1, Type *Ty2) const
virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const
X86 bit-test instructions.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(MVT VT) const
lazy value info
bool isVINSERT256Index(SDNode *N)
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
virtual bool isShuffleMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const
unsigned getExtractVEXTRACT128Immediate(SDNode *N)
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
HADD - Integer horizontal add.
X86TargetLowering(X86TargetMachine &TM)
X86 compare and logical compare instructions.
virtual bool isVectorClearMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const
virtual bool isSafeMemOpType(MVT VT) const
ConstraintType getConstraintType(const std::string &Constraint) const
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const
FMAXC, FMINC - Commutative FMIN and FMAX.
SMAX, SMIN - Signed integer max and min.
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:240
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
bool isIntegerTypeFTOL(EVT VT) const
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const
getSetCCResultType - Return the value type to use for ISD::SETCC.
virtual const char * LowerXConstraint(EVT ConstraintVT) const
virtual bool ExpandInlineAsm(CallInst *CI) const
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
Definition: APFloat.h:122
virtual unsigned getJumpTableEncoding() const
virtual bool isLegalICmpImmediate(int64_t Imm) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const
virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const
REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
BLENDI - Blend where the selector is an immediate.
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const
virtual const char * getTargetNodeName(unsigned Opcode) const
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const
bool isTargetWindows() const
Definition: X86Subtarget.h:326
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const LLVM_OVERRIDE
Returns true if a cast between SrcAS and DestAS is a noop.
bool isVEXTRACT256Index(SDNode *N)
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
virtual bool isLegalAddImmediate(int64_t Imm) const
virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const
AddressSpace
Definition: NVPTXBaseInfo.h:22
unsigned getExtractVEXTRACT256Immediate(SDNode *N)
static const int FIRST_TARGET_MEMORY_OPCODE
Definition: ISDOpcodes.h:648
Class for arbitrary precision integers.
Definition: APInt.h:75
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:234
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1840
UMAX, UMIN - Unsigned integer max and min.
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
virtual void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
ANDNP - Bitwise Logical AND NOT of Packed FP values.
virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
unsigned getInsertVINSERT256Immediate(SDNode *N)
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool TailCallOpt)
virtual FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
FHADD - Floating point horizontal add.
bool isZeroNode(SDValue Elt)
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement=true)
virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const
virtual unsigned getByValTypeAlignment(Type *Ty) const
bool isScalarFPTypeInSSEReg(EVT VT) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
#define LLVM_OVERRIDE
Definition: Compiler.h:155