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llvm::X86TargetLowering Class Reference

#include <X86ISelLowering.h>

Inheritance diagram for llvm::X86TargetLowering:
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Collaboration diagram for llvm::X86TargetLowering:
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Public Member Functions

 X86TargetLowering (X86TargetMachine &TM)
 
virtual unsigned getJumpTableEncoding () const
 
virtual MVT getScalarShiftAmountTy (EVT LHSTy) const
 
virtual const MCExpr * LowerCustomJumpTableEntry (const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const
 
virtual SDValue getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
 
virtual const MCExpr * getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
 
virtual unsigned getByValTypeAlignment (Type *Ty) const
 
virtual EVT getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const
 
virtual bool isSafeMemOpType (MVT VT) const
 
virtual bool allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const
 
virtual SDValue LowerOperation (SDValue Op, SelectionDAG &DAG) const
 
virtual void ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
 
virtual SDValue PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const
 
virtual bool isTypeDesirableForOp (unsigned Opc, EVT VT) const
 
virtual bool IsDesirableToPromoteOp (SDValue Op, EVT &PVT) const
 
virtual MachineBasicBlock * EmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB) const
 
virtual const char * getTargetNodeName (unsigned Opcode) const
 
virtual EVT getSetCCResultType (LLVMContext &Context, EVT VT) const
 getSetCCResultType - Return the value type to use for ISD::SETCC. More...
 
virtual void computeMaskedBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const
 
virtual unsigned ComputeNumSignBitsForTargetNode (SDValue Op, unsigned Depth) const
 
virtual bool isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
 
SDValue getReturnAddressFrameIndex (SelectionDAG &DAG) const
 
virtual bool ExpandInlineAsm (CallInst *CI) const
 
ConstraintType getConstraintType (const std::string &Constraint) const
 
virtual ConstraintWeight getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const
 
virtual const char * LowerXConstraint (EVT ConstraintVT) const
 
virtual void LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
 
std::pair< unsigned, const
TargetRegisterClass * > 		getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const
 
virtual bool isLegalAddressingMode (const AddrMode &AM, Type *Ty) const
 
virtual bool isLegalICmpImmediate (int64_t Imm) const
 
virtual bool isLegalAddImmediate (int64_t Imm) const
 
virtual bool isTruncateFree (Type *Ty1, Type *Ty2) const
 
virtual bool isTruncateFree (EVT VT1, EVT VT2) const
 
virtual bool allowTruncateForTailCall (Type *Ty1, Type *Ty2) const
 
virtual bool isZExtFree (Type *Ty1, Type *Ty2) const
 
virtual bool isZExtFree (EVT VT1, EVT VT2) const
 
virtual bool isZExtFree (SDValue Val, EVT VT2) const
 
virtual bool isFMAFasterThanFMulAndFAdd (EVT VT) const
 
virtual bool isNarrowingProfitable (EVT VT1, EVT VT2) const
 
virtual bool isFPImmLegal (const APFloat &Imm, EVT VT) const
 
virtual bool isShuffleMaskLegal (const SmallVectorImpl< int > &Mask, EVT VT) const
 
virtual bool isVectorClearMaskLegal (const SmallVectorImpl< int > &Mask, EVT VT) const
 
virtual bool ShouldShrinkFPConstant (EVT VT) const
 
const X86Subtarget * getSubtarget () const
 
bool isScalarFPTypeInSSEReg (EVT VT) const
 
bool isTargetFTOL () const
 
bool isIntegerTypeFTOL (EVT VT) const
 
virtual FastISel * createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const
 
virtual bool getStackCookieLocation (unsigned &AddressSpace, unsigned &Offset) const
 
SDValue BuildFILD (SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const
 
virtual bool isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const LLVM_OVERRIDE
 Returns true if a cast between SrcAS and DestAS is a noop. More...
 
virtual void resetOperationActions ()
 Reset the operation actions based on target options. More...
 
- Public Member Functions inherited from llvm::TargetLowering
 TargetLowering (const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)
 NOTE: The constructor takes ownership of TLOF. More...
 
virtual bool getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
 
virtual bool getPostIndexedAddressParts (SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
 
virtual bool isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const
 
bool isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
 
void softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
 
std::pair< SDValue, SDValue > makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
 Returns a pair of (return value, chain). More...
 
bool SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
 
SDValue SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const
 
virtual bool isDesirableToTransformToIntegerOp (unsigned, EVT) const
 
std::pair< SDValue, SDValue > LowerCallTo (CallLoweringInfo &CLI) const
 
virtual void HandleByVal (CCState *, unsigned &, unsigned) const
 Target-specific cleanup for formal ByVal parameters. More...
 
virtual void LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
 
virtual AsmOperandInfoVector ParseConstraints (ImmutableCallSite CS) const
 
virtual ConstraintWeight getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const
 
virtual void ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=0) const
 
SDValue BuildExactSDIV (SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const
 Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant. More...
 
SDValue BuildSDIV (SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...
 
SDValue BuildUDIV (SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...
 
virtual void AdjustInstrPostInstrSelection (MachineInstr *MI, SDNode *Node) const
 
- Public Member Functions inherited from llvm::TargetLoweringBase
 TargetLoweringBase (const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)
 NOTE: The constructor takes ownership of TLOF. More...
 
virtual ~TargetLoweringBase ()
 
const TargetMachine & getTargetMachine () const
 
const DataLayout * getDataLayout () const
 
const TargetLoweringObjectFile & getObjFileLowering () const
 
bool isBigEndian () const
 
bool isLittleEndian () const
 
virtual MVT getPointerTy (uint32_t=0) const
 
unsigned getPointerSizeInBits (uint32_t AS=0) const
 
unsigned getPointerTypeSizeInBits (Type *Ty) const
 
EVT getShiftAmountTy (EVT LHSTy) const
 
virtual MVT getVectorIdxTy () const
 
bool isSelectExpensive () const
 Return true if the select operation is expensive for this target. More...
 
virtual bool isSelectSupported (SelectSupportKind) const
 
virtual bool shouldSplitVectorElementType (EVT) const
 
bool isIntDivCheap () const
 
bool isSlowDivBypassed () const
 Returns true if target has indicated at least one type should be bypassed. More...
 
const DenseMap< unsigned int,
unsigned int > & 		getBypassSlowDivWidths () const
 
bool isPow2DivCheap () const
 Return true if pow2 div is cheaper than a chain of srl/add/sra. More...
 
bool isJumpExpensive () const
 
bool isPredictableSelectExpensive () const
 
virtual bool isLoadBitCastBeneficial (EVT, EVT) const
 
virtual MVT::SimpleValueType getCmpLibcallReturnType () const
 
BooleanContent getBooleanContents (bool isVec) const
 
Sched::Preference getSchedulingPreference () const
 Return target scheduling preference. More...
 
virtual Sched::Preference getSchedulingPreference (SDNode *) const
 
virtual const TargetRegisterClass * getRegClassFor (MVT VT) const
 
virtual const TargetRegisterClass * getRepRegClassFor (MVT VT) const
 
virtual uint8_t getRepRegClassCostFor (MVT VT) const
 
bool isTypeLegal (EVT VT) const
 
const ValueTypeActionImpl & getValueTypeActions () const
 
LegalizeTypeAction getTypeAction (LLVMContext &Context, EVT VT) const
 
LegalizeTypeAction getTypeAction (MVT VT) const
 
EVT getTypeToTransformTo (LLVMContext &Context, EVT VT) const
 
EVT getTypeToExpandTo (LLVMContext &Context, EVT VT) const
 
unsigned getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 
virtual bool getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, unsigned) const
 
virtual bool canOpTrap (unsigned Op, EVT VT) const
 
LegalizeAction getOperationAction (unsigned Op, EVT VT) const
 
bool isOperationLegalOrCustom (unsigned Op, EVT VT) const
 
bool isOperationLegalOrPromote (unsigned Op, EVT VT) const
 
bool isOperationExpand (unsigned Op, EVT VT) const
 
bool isOperationLegal (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target. More...
 
LegalizeAction getLoadExtAction (unsigned ExtType, MVT VT) const
 
bool isLoadExtLegal (unsigned ExtType, EVT VT) const
 Return true if the specified load with extension is legal on this target. More...
 
LegalizeAction getTruncStoreAction (MVT ValVT, MVT MemVT) const
 
bool isTruncStoreLegal (EVT ValVT, EVT MemVT) const
 
LegalizeAction getIndexedLoadAction (unsigned IdxMode, MVT VT) const
 
bool isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getIndexedStoreAction (unsigned IdxMode, MVT VT) const
 
bool isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getCondCodeAction (ISD::CondCode CC, MVT VT) const
 
bool isCondCodeLegal (ISD::CondCode CC, MVT VT) const
 Return true if the specified condition code is legal on this target. More...
 
MVT getTypeToPromoteTo (unsigned Op, MVT VT) const
 
EVT getValueType (Type *Ty, bool AllowUnknown=false) const
 
MVT getSimpleValueType (Type *Ty, bool AllowUnknown=false) const
 Return the MVT corresponding to this LLVM type. See getValueType. More...
 
MVT getRegisterType (MVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
MVT getRegisterType (LLVMContext &Context, EVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
unsigned getNumRegisters (LLVMContext &Context, EVT VT) const
 
bool hasTargetDAGCombine (ISD::NodeType NT) const
 
unsigned getMaxStoresPerMemset (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memset. More...
 
unsigned getMaxStoresPerMemcpy (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memcpy. More...
 
unsigned getMaxStoresPerMemmove (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memmove. More...
 
bool usesUnderscoreSetJmp () const
 Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...
 
bool usesUnderscoreLongJmp () const
 Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...
 
bool supportJumpTables () const
 Return whether the target can generate code for jump tables. More...
 
int getMinimumJumpTableEntries () const
 
unsigned getStackPointerRegisterToSaveRestore () const
 
unsigned getExceptionPointerRegister () const
 
unsigned getExceptionSelectorRegister () const
 
unsigned getJumpBufSize () const
 
unsigned getJumpBufAlignment () const
 
unsigned getMinStackArgumentAlignment () const
 Return the minimum stack alignment of an argument. More...
 
unsigned getMinFunctionAlignment () const
 Return the minimum function alignment. More...
 
unsigned getPrefFunctionAlignment () const
 Return the preferred function alignment. More...
 
unsigned getPrefLoopAlignment () const
 Return the preferred loop alignment. More...
 
bool getInsertFencesForAtomic () const
 
virtual unsigned getMaximalGlobalOffset () const
 
virtual bool GetAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const
 
virtual int getScalingFactorCost (const AddrMode &AM, Type *Ty) const
 Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...
 
virtual bool hasPairedLoad (Type *, unsigned &) const
 
virtual bool hasPairedLoad (EVT, unsigned &) const
 
virtual bool isFNegFree (EVT VT) const
 
virtual bool isFAbsFree (EVT VT) const
 
void setLibcallName (RTLIB::Libcall Call, const char *Name)
 Rename the default libcall routine name for the specified libcall. More...
 
const char * getLibcallName (RTLIB::Libcall Call) const
 Get the libcall routine name for the specified libcall. More...
 
void setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
 
ISD::CondCode getCmpLibcallCC (RTLIB::Libcall Call) const
 
void setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
 Set the CallingConv that should be used for the specified libcall. More...
 
CallingConv::ID getLibcallCallingConv (RTLIB::Libcall Call) const
 Get the CallingConv that should be used for the specified libcall. More...
 
LegalizeKind getTypeConversion (LLVMContext &Context, EVT VT) const
 
int InstructionOpcodeToISD (unsigned Opcode) const
 Get the ISD node that corresponds to the Instruction class opcode. More...
 
std::pair< unsigned, MVT > getTypeLegalizationCost (Type *Ty) const
 Estimate the cost of type-legalization and the legalized type. More...
 

Protected Member Functions

std::pair< const
TargetRegisterClass *, uint8_t > 		findRepresentativeClass (MVT VT) const
 
- Protected Member Functions inherited from llvm::TargetLoweringBase
void initActions ()
 Initialize all of the actions to default values. More...
 
void setBooleanContents (BooleanContent Ty)
 
void setBooleanVectorContents (BooleanContent Ty)
 
void setSchedulingPreference (Sched::Preference Pref)
 Specify the target scheduling preference. More...
 
void setUseUnderscoreSetJmp (bool Val)
 
void setUseUnderscoreLongJmp (bool Val)
 
void setSupportJumpTables (bool Val)
 Indicate whether the target can generate code for jump tables. More...
 
void setMinimumJumpTableEntries (int Val)
 
void setStackPointerRegisterToSaveRestore (unsigned R)
 
void setExceptionPointerRegister (unsigned R)
 
void setExceptionSelectorRegister (unsigned R)
 
void setSelectIsExpensive (bool isExpensive=true)
 
void setJumpIsExpensive (bool isExpensive=true)
 
void setIntDivIsCheap (bool isCheap=true)
 
void addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
 Tells the code generator which bitwidths to bypass. More...
 
void setPow2DivIsCheap (bool isCheap=true)
 
void addRegisterClass (MVT VT, const TargetRegisterClass *RC)
 
void clearRegisterClasses ()
 Remove all register classes. More...
 
void clearOperationActions ()
 Remove all operation actions. More...
 
void computeRegisterProperties ()
 
void setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
 
void setLoadExtAction (unsigned ExtType, MVT VT, LegalizeAction Action)
 
void setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
 
void setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 
void setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 
void setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
 
void AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 
void setTargetDAGCombine (ISD::NodeType NT)
 
void setJumpBufSize (unsigned Size)
 Set the target's required jmp_buf buffer size (in bytes); default is 200. More...
 
void setJumpBufAlignment (unsigned Align)
 
void setMinFunctionAlignment (unsigned Align)
 Set the target's minimum function alignment (in log2(bytes)) More...
 
void setPrefFunctionAlignment (unsigned Align)
 
void setPrefLoopAlignment (unsigned Align)
 
void setMinStackArgumentAlignment (unsigned Align)
 Set the minimum stack alignment of an argument (in log2(bytes)). More...
 
void setInsertFencesForAtomic (bool fence)
 
bool isLegalRC (const TargetRegisterClass *RC) const
 

Additional Inherited Members

- Public Types inherited from llvm::TargetLowering
enum  ConstraintType {
  C_Register, C_RegisterClass, C_Memory, C_Other,
  C_Unknown
}
 
enum  ConstraintWeight {
  CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2,
  CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better,
  CW_Constant = CW_Best, CW_Default = CW_Okay
}
 
typedef std::vector< ArgListEntry > ArgListTy
 
typedef std::vector
< AsmOperandInfo > 		AsmOperandInfoVector
 
- Public Types inherited from llvm::TargetLoweringBase
enum  LegalizeAction { Legal, Promote, Expand, Custom }
 
enum  LegalizeTypeAction {
  TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat,
  TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector
}
 
enum  BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
 Enum that describes how the target represents true/false values. More...
 
enum  SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
 Enum that describes what type of support for selects the target has. More...
 
typedef std::pair
< LegalizeTypeAction, EVT > 		LegalizeKind
 
- Static Public Member Functions inherited from llvm::TargetLoweringBase
static ISD::NodeType getExtendForContent (BooleanContent Content)
 
- Protected Attributes inherited from llvm::TargetLoweringBase
unsigned MaxStoresPerMemset
 Specify maximum number of store instructions per memset call. More...
 
unsigned MaxStoresPerMemsetOptSize
 
unsigned MaxStoresPerMemcpy
 Specify maximum bytes of store instructions per memcpy call. More...
 
unsigned MaxStoresPerMemcpyOptSize
 
unsigned MaxStoresPerMemmove
 Specify maximum bytes of store instructions per memmove call. More...
 
unsigned MaxStoresPerMemmoveOptSize
 
bool PredictableSelectIsExpensive
 

Detailed Description

Definition at line 525 of file X86ISelLowering.h.

Constructor & Destructor Documentation

X86TargetLowering::X86TargetLowering ( X86TargetMachine &  TM)
explicit

Definition at line 198 of file X86ISelLowering.cpp.

References llvm::TargetLoweringBase::getDataLayout(), llvm::TargetMachine::getSubtarget(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), and resetOperationActions().

Member Function Documentation

bool X86TargetLowering::allowsUnalignedMemoryAccesses ( EVT  VT,
bool *  Fast 
) const
virtual

allowsUnalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses. of the specified type. Returns whether it is "fast" by reference in the second argument.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1664 of file X86ISelLowering.cpp.

References llvm::X86Subtarget::isUnalignedMemAccessFast().

bool X86TargetLowering::allowTruncateForTailCall ( Type *  ,
Type *   
) const
virtual

Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position. Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13920 of file X86ISelLowering.cpp.

References llvm::EVT::getEVT(), llvm::Type::getPrimitiveSizeInBits(), llvm::Type::isIntegerTy(), and llvm::TargetLoweringBase::isTypeLegal().

SDValue X86TargetLowering::BuildFILD ( SDValue  Op,
EVT  SrcVT,
SDValue  Chain,
SDValue  StackSlot,
SelectionDAG &  DAG 
) const

Definition at line 8493 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, llvm::lltok::APFloat, llvm::array_lengthof(), llvm::ISD::BITCAST, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::BitsToDouble(), llvm::ISD::BUILD_PAIR, llvm::MachineFrameInfo::CreateStackObject(), llvm::SelectionDAG::CreateStackTemporary(), llvm::dyn_cast(), llvm::N86::EAX, llvm::N86::EDX, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::ISD::FADD, llvm::X86ISD::FHADD, llvm::X86ISD::FILD, llvm::X86ISD::FILD_FLAG, llvm::X86ISD::FLD, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::X86ISD::FP_TO_INT16_IN_MEM, llvm::X86ISD::FP_TO_INT32_IN_MEM, llvm::X86ISD::FP_TO_INT64_IN_MEM, llvm::X86ISD::FST, llvm::ISD::FSUB, llvm::ConstantInt::get(), llvm::ConstantFP::get(), llvm::ConstantVector::get(), llvm::ConstantDataVector::get(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getConstantPool(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::FrameIndexSDNode::getIndex(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getSetCC(), getSetCCResultType(), getShuffleVectorZeroOrUndef(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), getTargetShuffleNode(), getUnpackl(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::X86Subtarget::hasSSE3(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::APFloat::IEEEdouble, llvm::X86Subtarget::is64Bit(), isIntegerTypeFTOL(), isScalarFPTypeInSSEReg(), llvm::EVT::isVector(), llvm_unreachable, llvm::SPII::Load, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::ISD::OR, llvm::APIntOps::Or(), llvm::MVT::Other, llvm::X86ISD::PSHUFD, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT, llvm::ISD::SETLT, llvm::SelectionDAG::SignBitIsZero(), llvm::MVT::SimpleTy, llvm::ISD::SINT_TO_FP, llvm::SPII::Store, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i8, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::X86ISD::WIN_FTOL, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zext().

Referenced by PerformSINT_TO_FPCombine().

void X86TargetLowering::computeMaskedBitsForTargetNode ( const SDValue  Op,
APInt &  KnownZero,
APInt &  KnownOne,
const SelectionDAG &  DAG,
unsigned  Depth = 0 
) const
virtual

computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Reimplemented from llvm::TargetLowering.

Definition at line 16002 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADC, llvm::X86ISD::ADD, llvm::X86ISD::AND, llvm::ISD::BUILTIN_OP_END, llvm::X86ISD::DEC, llvm::APInt::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::X86ISD::INC, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm_unreachable, llvm::X86ISD::OR, llvm::X86ISD::SBB, llvm::X86ISD::SETCC, llvm::X86ISD::SMUL, llvm::X86ISD::SUB, llvm::X86ISD::UMUL, llvm::Intrinsic::x86_avx2_pmovmskb, llvm::Intrinsic::x86_avx_movmsk_pd_256, llvm::Intrinsic::x86_avx_movmsk_ps_256, llvm::Intrinsic::x86_mmx_pmovmskb, llvm::Intrinsic::x86_sse2_movmsk_pd, llvm::Intrinsic::x86_sse2_pmovmskb_128, llvm::Intrinsic::x86_sse_movmsk_ps, and llvm::X86ISD::XOR.

unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode ( SDValue  Op,
unsigned  Depth 
) const
virtual

This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

ComputeNumSignBitsForTargetNode - This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

Reimplemented from llvm::TargetLowering.

Definition at line 16069 of file X86ISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), and llvm::X86ISD::SETCC_CARRY.

FastISel * X86TargetLowering::createFastISel ( FunctionLoweringInfo &  funcInfo,
const TargetLibraryInfo *  libInfo 
) const
virtual

createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Reimplemented from llvm::TargetLowering.

Definition at line 3245 of file X86ISelLowering.cpp.

References llvm::X86::createFastISel().

MachineBasicBlock * X86TargetLowering::EmitInstrWithCustomInserter ( MachineInstr *  MI,
MachineBasicBlock *  MBB 
) const
virtual

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow.

Reimplemented from llvm::TargetLowering.

Definition at line 15769 of file X86ISelLowering.cpp.

References llvm::addFrameReference(), llvm::addFullAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::X86AddressMode::Base, llvm::X86AddressMode::BaseType, llvm::BuildMI(), llvm::MachineFrameInfo::CreateStackObject(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::X86AddressMode::Disp, EmitMonitor(), EmitPCMPSTRI(), EmitPCMPSTRM(), EmitXBegin(), llvm::MachineInstr::eraseFromParent(), llvm::X86ISD::FNSTCW16m, llvm::X86AddressMode::FrameIndex, llvm::X86AddressMode::FrameIndexBase, llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetLoweringBase::getTargetMachine(), llvm::X86AddressMode::GV, llvm::X86Subtarget::hasSSE42(), llvm::X86AddressMode::IndexReg, llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm_unreachable, llvm::X86AddressMode::Reg, llvm::X86AddressMode::RegBase, llvm::X86AddressMode::Scale, llvm::X86ISD::VAARG_64, llvm::X86ISD::VASTART_SAVE_XMM_REGS, and llvm::X86ISD::WIN_ALLOCA.

bool X86TargetLowering::ExpandInlineAsm ( CallInst *  ) const
virtual

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.

Reimplemented from llvm::TargetLowering.

Definition at line 19299 of file X86ISelLowering.cpp.

References llvm::array_pod_sort(), llvm::SmallVectorTemplateCommon< T >::begin(), llvm::SmallVectorImpl< T >::clear(), clobbersFlagRegisters(), llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T >::end(), llvm::InlineAsm::getAsmString(), llvm::IntegerType::getBitWidth(), llvm::CallInst::getCalledValue(), llvm::InlineAsm::getConstraintString(), llvm::Value::getType(), llvm::Type::isIntegerTy(), llvm::IntrinsicLowering::LowerToByteSwap(), llvm::InlineAsm::ParseConstraints(), llvm::SmallVectorTemplateCommon< T >::size(), and llvm::SplitString().

std::pair< const TargetRegisterClass *, uint8_t > X86TargetLowering::findRepresentativeClass ( MVT  VT) const
protectedvirtual

Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1723 of file X86ISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::TargetLoweringBase::findRepresentativeClass(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), llvm::MSP430ISD::RRC, llvm::MVT::SimpleTy, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8f32, llvm::MVT::v8i16, llvm::MVT::v8i32, and llvm::MVT::x86mmx.

unsigned X86TargetLowering::getByValTypeAlignment ( Type *  Ty) const
virtual

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. For X86, aggregates that contains are placed at 16-byte boundaries while the rest are at 4-byte boundaries.

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. For X86, aggregates that contain SSE vectors are placed at 16-byte boundaries while the rest are at 4-byte boundaries.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1592 of file X86ISelLowering.cpp.

References Align(), llvm::DataLayout::getABITypeAlignment(), getMaxByValAlign(), llvm::X86Subtarget::hasSSE1(), and llvm::X86Subtarget::is64Bit().

X86TargetLowering::ConstraintType X86TargetLowering::getConstraintType ( const std::string &  Constraint) const
virtual

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

Reimplemented from llvm::TargetLowering.

Definition at line 19378 of file X86ISelLowering.cpp.

References llvm::TargetLowering::C_Other, llvm::TargetLowering::C_Register, llvm::TargetLowering::C_RegisterClass, and llvm::TargetLowering::getConstraintType().

unsigned X86TargetLowering::getJumpTableEncoding ( ) const
virtual

getJumpTableEncoding - Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

Reimplemented from llvm::TargetLowering.

Definition at line 1673 of file X86ISelLowering.cpp.

References llvm::MachineJumpTableInfo::EK_Custom32, llvm::TargetLowering::getJumpTableEncoding(), llvm::TargetLoweringBase::getTargetMachine(), llvm::X86Subtarget::isPICStyleGOT(), and llvm::Reloc::PIC_.

EVT X86TargetLowering::getOptimalMemOpType ( uint64_t  Size,
unsigned  DstAlign,
unsigned  SrcAlign,
bool  IsMemset,
bool  ZeroMemset,
bool  MemcpyStrSrc,
MachineFunction &  MF 
) const
virtual

getOptimalMemOpType - Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1619 of file X86ISelLowering.cpp.

References F(), llvm::MVT::f64, llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::AttributeSet::hasAttribute(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i32, llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isUnalignedMemAccessFast(), llvm::Attribute::NoImplicitFloat, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8f32, and llvm::MVT::v8i32.

SDValue X86TargetLowering::getPICJumpTableRelocBase ( SDValue  Table,
SelectionDAG &  DAG 
) const
virtual

getPICJumpTableRelocaBase - Returns relocation base for the given PIC jumptable.

Reimplemented from llvm::TargetLowering.

Definition at line 1698 of file X86ISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::X86ISD::GlobalBaseReg, and llvm::X86Subtarget::is64Bit().

const MCExpr * X86TargetLowering::getPICJumpTableRelocBaseExpr ( const MachineFunction *  MF,
unsigned  JTI,
MCContext &  Ctx 
) const
virtual

getPICJumpTableRelocBaseExpr - This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

Reimplemented from llvm::TargetLowering.

Definition at line 1711 of file X86ISelLowering.cpp.

References llvm::MCSymbolRefExpr::Create(), llvm::MachineFunction::getPICBaseSymbol(), llvm::TargetLowering::getPICJumpTableRelocBaseExpr(), and llvm::X86Subtarget::isPICStyleRIPRel().

std::pair< unsigned, const TargetRegisterClass * > X86TargetLowering::getRegForInlineAsmConstraint ( const std::string &  Constraint,
MVT  VT 
) const
virtual

getRegForInlineAsmConstraint - Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register. This should only be used for C_Register constraints. On error, this returns a register number of 0.

Reimplemented from llvm::TargetLowering.

Definition at line 19676 of file X86ISelLowering.cpp.

References llvm::A64CC::AL, llvm::XCoreISD::BL, llvm::N86::EAX, llvm::N86::EBP, llvm::N86::EBX, llvm::N86::ECX, llvm::N86::EDI, llvm::N86::EDX, llvm::StringRef::equals_lower(), llvm::N86::ESI, llvm::N86::ESP, llvm::MVT::f32, llvm::MVT::f64, llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, if(), llvm::X86Subtarget::is64Bit(), isScalarFPTypeInSSEReg(), llvm::MVT::SimpleTy, llvm::MVT::v16f32, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8f32, llvm::MVT::v8f64, llvm::MVT::v8i16, llvm::MVT::v8i32, and llvm::MVT::v8i64.

SDValue X86TargetLowering::getReturnAddressFrameIndex ( SelectionDAG &  DAG) const

Definition at line 3344 of file X86ISelLowering.cpp.

References llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getPointerTy(), llvm::X86MachineFunctionInfo::getRAIndex(), llvm::TargetMachine::getRegisterInfo(), llvm::X86RegisterInfo::getSlotSize(), llvm::TargetLoweringBase::getTargetMachine(), and llvm::X86MachineFunctionInfo::setRAIndex().

Referenced by LowerINTRINSIC_W_CHAIN().

virtual MVT llvm::X86TargetLowering::getScalarShiftAmountTy ( EVT  LHSTy) const
inlinevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 531 of file X86ISelLowering.h.

References llvm::MVT::i8.

EVT X86TargetLowering::getSetCCResultType ( LLVMContext &  Context,
EVT  VT 
) const
virtual

getSetCCResultType - Return the value type to use for ISD::SETCC.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1549 of file X86ISelLowering.cpp.

References llvm::EVT::changeVectorElementTypeToInteger(), llvm::TargetLoweringBase::getTargetMachine(), llvm::EVT::getVectorNumElements(), llvm::X86Subtarget::hasAVX512(), llvm::MVT::i8, llvm::EVT::isVector(), llvm::TargetMachine::Options, llvm::TargetOptions::UseSoftFloat, llvm::MVT::v16i1, and llvm::MVT::v8i1.

Referenced by BuildFILD().

TargetLowering::ConstraintWeight X86TargetLowering::getSingleConstraintMatchWeight ( AsmOperandInfo &  info,
const char *  constraint 
) const
virtual

Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Reimplemented from llvm::TargetLowering.

Definition at line 19422 of file X86ISelLowering.cpp.

References llvm::TargetLowering::AsmOperandInfo::CallOperandVal, llvm::TargetLowering::CW_Constant, llvm::TargetLowering::CW_Default, llvm::TargetLowering::CW_Invalid, llvm::TargetLowering::CW_Register, llvm::TargetLowering::CW_SpecificReg, llvm::Type::getPrimitiveSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::TargetLowering::getSingleConstraintMatchWeight(), llvm::Value::getType(), llvm::ConstantSDNode::getZExtValue(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE1(), llvm::Type::isFloatingPointTy(), llvm::Type::isIntegerTy(), and llvm::Type::isX86_MMXTy().

bool X86TargetLowering::getStackCookieLocation ( unsigned &  AddressSpace,
unsigned &  Offset 
) const
virtual

getStackCookieLocation - Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1748 of file X86ISelLowering.cpp.

References llvm::TargetMachine::getCodeModel(), llvm::TargetLoweringBase::getTargetMachine(), llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isTargetLinux(), and llvm::CodeModel::Kernel.

const X86Subtarget* llvm::X86TargetLowering::getSubtarget ( ) const
inline

Definition at line 741 of file X86ISelLowering.h.

Referenced by PerformSINT_TO_FPCombine().

const char * X86TargetLowering::getTargetNodeName ( unsigned  Opcode) const
virtual

getTargetNodeName - This method returns the name of a target specific DAG node.

Reimplemented from llvm::TargetLowering.

Definition at line 13686 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADC, llvm::X86ISD::ADD, llvm::X86ISD::AND, llvm::X86ISD::ANDNP, llvm::X86ISD::ATOMADD64_DAG, llvm::X86ISD::ATOMAND64_DAG, llvm::X86ISD::ATOMNAND64_DAG, llvm::X86ISD::ATOMOR64_DAG, llvm::X86ISD::ATOMSUB64_DAG, llvm::X86ISD::ATOMXOR64_DAG, llvm::X86ISD::BEXTR, llvm::X86ISD::BLENDI, llvm::X86ISD::BLENDV, llvm::X86ISD::BLSI, llvm::X86ISD::BLSMSK, llvm::X86ISD::BLSR, llvm::X86ISD::BRCOND, llvm::X86ISD::BSF, llvm::X86ISD::BSR, llvm::X86ISD::BT, llvm::X86ISD::BZHI, llvm::X86ISD::CALL, llvm::X86ISD::CMOV, llvm::X86ISD::CMP, llvm::X86ISD::CMPM, llvm::X86ISD::CMPMU, llvm::X86ISD::CMPP, llvm::X86ISD::COMI, llvm::X86ISD::DEC, llvm::X86ISD::EH_RETURN, llvm::X86ISD::EH_SJLJ_LONGJMP, llvm::X86ISD::EH_SJLJ_SETJMP, llvm::X86ISD::FAND, llvm::X86ISD::FANDN, llvm::X86ISD::FHADD, llvm::X86ISD::FHSUB, llvm::X86ISD::FILD_FLAG, llvm::X86ISD::FLD, llvm::X86ISD::FMADD, llvm::X86ISD::FMADDSUB, llvm::X86ISD::FMAX, llvm::X86ISD::FMAXC, llvm::X86ISD::FMIN, llvm::X86ISD::FMINC, llvm::X86ISD::FMSUB, llvm::X86ISD::FMSUBADD, llvm::X86ISD::FNMADD, llvm::X86ISD::FNMSUB, llvm::X86ISD::FNSTCW16m, llvm::X86ISD::FNSTSW16r, llvm::X86ISD::FOR, llvm::X86ISD::FP_TO_INT16_IN_MEM, llvm::X86ISD::FP_TO_INT32_IN_MEM, llvm::X86ISD::FP_TO_INT64_IN_MEM, llvm::X86ISD::FRCP, llvm::X86ISD::FRSQRT, llvm::X86ISD::FSETCCsd, llvm::X86ISD::FSETCCss, llvm::X86ISD::FSRL, llvm::X86ISD::FST, llvm::X86ISD::FXOR, llvm::X86ISD::GlobalBaseReg, llvm::X86ISD::HADD, llvm::X86ISD::HSUB, llvm::X86ISD::INC, llvm::X86ISD::INSERTPS, llvm::X86ISD::KORTEST, llvm::X86ISD::KTEST, llvm::X86ISD::LCMPXCHG8_DAG, llvm::X86ISD::LCMPXCHG_DAG, llvm::X86ISD::MEMBARRIER, llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPD, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVLPD, llvm::X86ISD::MOVLPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSHDUP, llvm::X86ISD::MOVSLDUP, llvm::X86ISD::MOVSS, llvm::X86ISD::MUL_IMM, llvm::X86ISD::OR, llvm::X86ISD::PALIGNR, llvm::X86ISD::PCMPEQ, llvm::X86ISD::PCMPEQM, llvm::X86ISD::PCMPESTRI, llvm::X86ISD::PCMPGT, llvm::X86ISD::PCMPGTM, llvm::X86ISD::PCMPISTRI, llvm::X86ISD::PEXTRB, llvm::X86ISD::PEXTRW, llvm::X86ISD::PINSRB, llvm::X86ISD::PINSRW, llvm::X86ISD::PMULUDQ, llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::X86ISD::PSIGN, llvm::X86ISD::PTEST, llvm::X86ISD::RDRAND, llvm::X86ISD::RDSEED, llvm::X86ISD::RDTSC_DAG, llvm::X86ISD::REP_MOVS, llvm::X86ISD::REP_STOS, llvm::X86ISD::RET_FLAG, llvm::X86ISD::SAHF, llvm::X86ISD::SBB, llvm::X86ISD::SEG_ALLOCA, llvm::X86ISD::SETCC, llvm::X86ISD::SETCC_CARRY, llvm::X86ISD::SHLD, llvm::X86ISD::SHRD, llvm::X86ISD::SHUFP, llvm::X86ISD::SMAX, llvm::X86ISD::SMIN, llvm::X86ISD::SMUL, llvm::X86ISD::SUB, llvm::X86ISD::SUBUS, llvm::X86ISD::TC_RETURN, llvm::X86ISD::TESTM, llvm::X86ISD::TESTP, llvm::X86ISD::TLSADDR, llvm::X86ISD::TLSBASEADDR, llvm::X86ISD::TLSCALL, llvm::X86ISD::UCOMI, llvm::X86ISD::UMAX, llvm::X86ISD::UMIN, llvm::X86ISD::UMUL, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::X86ISD::VAARG_64, llvm::X86ISD::VASTART_SAVE_XMM_REGS, llvm::X86ISD::VBROADCAST, llvm::X86ISD::VBROADCASTM, llvm::X86ISD::VFPEXT, llvm::X86ISD::VFPROUND, llvm::X86ISD::VINSERT, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMI, llvm::X86ISD::VPERMILP, llvm::X86ISD::VPERMV, llvm::X86ISD::VPERMV3, llvm::X86ISD::VSEXT, llvm::X86ISD::VSEXT_MOVL, llvm::X86ISD::VSHL, llvm::X86ISD::VSHLDQ, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRA, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRL, llvm::X86ISD::VSRLDQ, llvm::X86ISD::VSRLI, llvm::X86ISD::VTRUNC, llvm::X86ISD::VTRUNCM, llvm::X86ISD::VZEXT, llvm::X86ISD::VZEXT_LOAD, llvm::X86ISD::VZEXT_MOVL, llvm::X86ISD::WIN_ALLOCA, llvm::X86ISD::WIN_FTOL, llvm::X86ISD::Wrapper, llvm::X86ISD::WrapperRIP, llvm::X86ISD::XOR, and llvm::X86ISD::XTEST.

bool X86TargetLowering::IsDesirableToPromoteOp ( SDValue  Op,
EVT &  PVT 
) const
virtual

isTypeDesirable - Return true if the target has native support for the specified value type and it is 'desirable' to use the type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.

IsDesirableToPromoteOp - This method query the target whether it is beneficial for dag combiner to promote the specified node. If true, it should return the desired promotion type by reference.

Reimplemented from llvm::TargetLowering.

Definition at line 19191 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::CopyToReg, llvm::LoadSDNode::getExtensionType(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::ISD::LOAD, MayFoldIntoStore(), MayFoldLoad(), llvm::ISD::MUL, llvm::ISD::NON_EXTLOAD, llvm::ISD::OR, llvm::TargetLoweringBase::Promote, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, llvm::ISD::SUB, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

bool X86TargetLowering::isFMAFasterThanFMulAndFAdd ( EVT  VT) const
virtual

isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd instructions. fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13986 of file X86ISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::X86Subtarget::hasFMA(), llvm::X86Subtarget::hasFMA4(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.

bool X86TargetLowering::isFPImmLegal ( const APFloat &  Imm,
EVT  VT 
) const
virtual

isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively. If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 3528 of file X86ISelLowering.cpp.

References llvm::APFloat::bitwiseIsEqual().

bool X86TargetLowering::isGAPlusOffset ( SDNode *  N,
const GlobalValue *&  GA,
int64_t &  Offset 
) const
virtual

isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

Reimplemented from llvm::TargetLowering.

Definition at line 16081 of file X86ISelLowering.cpp.

References llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLowering::isGAPlusOffset(), and llvm::X86ISD::Wrapper.

bool llvm::X86TargetLowering::isIntegerTypeFTOL ( EVT  VT) const
inline

isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be used for fptoui to the given type.

Definition at line 760 of file X86ISelLowering.h.

References llvm::MVT::i64, and isTargetFTOL().

Referenced by BuildFILD(), and ReplaceNodeResults().

bool X86TargetLowering::isLegalAddImmediate ( int64_t  Imm) const
virtual

isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13938 of file X86ISelLowering.cpp.

References llvm::isInt< 32 >().

bool X86TargetLowering::isLegalAddressingMode ( const AddrMode &  AM,
Type *  Ty 
) const
virtual

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13860 of file X86ISelLowering.cpp.

References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::X86Subtarget::ClassifyGlobalReference(), llvm::TargetMachine::getCodeModel(), llvm::TargetMachine::getRelocationModel(), llvm::TargetLoweringBase::getTargetMachine(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::X86Subtarget::is64Bit(), llvm::isGlobalRelativeToPICBase(), llvm::isGlobalStubReference(), llvm::X86::isOffsetSuitableForCodeModel(), llvm::TargetLoweringBase::AddrMode::Scale, llvm::CodeModel::Small, and llvm::Reloc::Static.

bool X86TargetLowering::isLegalICmpImmediate ( int64_t  Imm) const
virtual

isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13934 of file X86ISelLowering.cpp.

References llvm::isInt< 32 >().

bool X86TargetLowering::isNarrowingProfitable ( EVT  VT1,
EVT  VT2 
) const
virtual

isNarrowingProfitable - Return true if it's profitable to narrow operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14006 of file X86ISelLowering.cpp.

References llvm::MVT::i16, and llvm::MVT::i32.

bool X86TargetLowering::isNoopAddrSpaceCast ( unsigned  SrcAS,
unsigned  DestAS 
) const
virtual

Returns true if a cast between SrcAS and DestAS is a noop.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1768 of file X86ISelLowering.cpp.

bool X86TargetLowering::isSafeMemOpType ( MVT  VT) const
virtual

isSafeMemOpType - Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1655 of file X86ISelLowering.cpp.

References llvm::MVT::f32, and llvm::MVT::f64.

bool llvm::X86TargetLowering::isScalarFPTypeInSSEReg ( EVT  VT) const
inline

isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating point stack.

Definition at line 747 of file X86ISelLowering.h.

References llvm::MVT::f32, and llvm::MVT::f64.

Referenced by BuildFILD(), and getRegForInlineAsmConstraint().

bool X86TargetLowering::isShuffleMaskLegal ( const SmallVectorImpl< int > &  M,
EVT  VT 
) const
virtual

isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14016 of file X86ISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::X86Subtarget::hasInt256(), isMOVLMask(), isPALIGNRMask(), isPSHUFDMask(), isPSHUFHWMask(), isPSHUFLWMask(), isSHUFPMask(), llvm::EVT::isSimple(), llvm::ShuffleVectorSDNode::isSplatMask(), isUNPCKH_v_undef_Mask(), isUNPCKHMask(), isUNPCKL_v_undef_Mask(), and isUNPCKLMask().

bool llvm::X86TargetLowering::isTargetFTOL ( ) const
inline

isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine for fptoui.

Definition at line 754 of file X86ISelLowering.h.

References llvm::X86Subtarget::is64Bit(), and llvm::X86Subtarget::isTargetWindows().

Referenced by isIntegerTypeFTOL(), and resetOperationActions().

bool X86TargetLowering::isTruncateFree ( Type *  Ty1,
Type *  Ty2 
) const
virtual

isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13912 of file X86ISelLowering.cpp.

References llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().

bool X86TargetLowering::isTruncateFree ( EVT  VT1,
EVT  VT2 
) const
virtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13943 of file X86ISelLowering.cpp.

References llvm::EVT::getSizeInBits(), and llvm::EVT::isInteger().

bool X86TargetLowering::isTypeDesirableForOp ( unsigned  Opc,
EVT  VT 
) const
virtual

isTypeDesirableForOp - Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.

Reimplemented from llvm::TargetLowering.

Definition at line 19163 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::TargetLoweringBase::isTypeLegal(), llvm::ISD::LOAD, llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

bool X86TargetLowering::isVectorClearMaskLegal ( const SmallVectorImpl< int > &  Mask,
EVT  VT 
) const
virtual

isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14043 of file X86ISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), isCommutedMOVLMask(), isMOVLMask(), isSHUFPMask(), and llvm::EVT::isSimple().

bool X86TargetLowering::isZExtFree ( Type *  Ty1,
Type *  Ty2 
) const
virtual

isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the value to Ty2 in the result register. This does not necessarily include registers defined in unknown ways, such as incoming arguments, or copies from unknown virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to truncate instructions. e.g. on x86-64, all instructions that define 32-bit values implicit zero-extend the result out to 64 bits.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13951 of file X86ISelLowering.cpp.

References llvm::X86Subtarget::is64Bit(), and llvm::Type::isIntegerTy().

Referenced by isZExtFree().

bool X86TargetLowering::isZExtFree ( EVT  VT1,
EVT  VT2 
) const
virtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13956 of file X86ISelLowering.cpp.

References llvm::MVT::i32, llvm::MVT::i64, and llvm::X86Subtarget::is64Bit().

bool X86TargetLowering::isZExtFree ( SDValue  Val,
EVT  VT2 
) const
virtual

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13961 of file X86ISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isInteger(), llvm::EVT::isSimple(), isZExtFree(), llvm::ISD::LOAD, and llvm::MVT::SimpleTy.

void X86TargetLowering::LowerAsmOperandForConstraint ( SDValue  Op,
std::string &  Constraint,
std::vector< SDValue > &  Ops,
SelectionDAG &  DAG 
) const
virtual

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.

Reimplemented from llvm::TargetLowering.

Definition at line 19542 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, llvm::X86Subtarget::ClassifyGlobalReference(), llvm::SelectionDAG::getContext(), llvm::GlobalAddressSDNode::getGlobal(), llvm::Type::getInt32Ty(), llvm::SDValue::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i64, llvm::isGlobalStubReference(), llvm::isInt< 8 >(), llvm::X86Subtarget::isPICStyleGOT(), llvm::X86Subtarget::isPICStyleStubPIC(), llvm::ConstantInt::isValueValidForType(), llvm::TargetLowering::LowerAsmOperandForConstraint(), and llvm::ISD::SUB.

const MCExpr * X86TargetLowering::LowerCustomJumpTableEntry ( const MachineJumpTableInfo *  MJTI,
const MachineBasicBlock *  MBB,
unsigned  uid,
MCContext &  Ctx 
) const
virtual

Reimplemented from llvm::TargetLowering.

Definition at line 1685 of file X86ISelLowering.cpp.

References llvm::MCSymbolRefExpr::Create(), llvm::MachineBasicBlock::getSymbol(), llvm::TargetLoweringBase::getTargetMachine(), llvm::X86Subtarget::isPICStyleGOT(), llvm::Reloc::PIC_, and llvm::MCSymbolRefExpr::VK_GOTOFF.

SDValue X86TargetLowering::LowerOperation ( SDValue  Op,
SelectionDAG &  DAG 
) const
virtual

LowerOperation - Provide custom lowering hooks for some operations.

Reimplemented from llvm::TargetLowering.

Definition at line 13377 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::ADJUST_TRAMPOLINE, llvm::ISD::ANY_EXTEND, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_STORE, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantPool, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EH_RETURN, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, llvm::ISD::ExternalSymbol, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FCOPYSIGN, llvm::ISD::FGETSIGN, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FRAME_TO_ARGS_OFFSET, llvm::ISD::FRAMEADDR, llvm::ISD::FSINCOS, llvm::SDValue::getOpcode(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INIT_TRAMPOLINE, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::JumpTable, llvm_unreachable, LowerADD(), LowerADDC_ADDE_SUBC_SUBE(), LowerADJUST_TRAMPOLINE(), LowerANY_EXTEND(), LowerATOMIC_FENCE(), LowerATOMIC_STORE(), LowerBITCAST(), LowerCMP_SWAP(), LowerCONCAT_VECTORS(), LowerCTLZ(), LowerCTLZ_ZERO_UNDEF(), LowerCTTZ(), LowerEXTRACT_SUBVECTOR(), LowerFGETSIGN(), LowerFP_EXTEND(), LowerFSINCOS(), LowerINSERT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), LowerINTRINSIC_WO_CHAIN(), LowerLOAD_SUB(), LowerMUL(), LowerREADCYCLECOUNTER(), LowerSCALAR_TO_VECTOR(), LowerSDIV(), LowerShift(), LowerSIGN_EXTEND(), LowerSUB(), LowerVACOPY(), LowerXALUO(), LowerZERO_EXTEND(), llvm::ISD::MUL, llvm::ISD::READCYCLECOUNTER, llvm::ISD::RETURNADDR, llvm::ISD::SADDO, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UINT_TO_FP, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, and llvm::ISD::ZERO_EXTEND.

const char * X86TargetLowering::LowerXConstraint ( EVT  ConstraintVT) const
virtual

LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.

Reimplemented from llvm::TargetLowering.

Definition at line 19527 of file X86ISelLowering.cpp.

References llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::EVT::isFloatingPoint(), and llvm::TargetLowering::LowerXConstraint().

SDValue X86TargetLowering::PerformDAGCombine ( SDNode *  N,
DAGCombinerInfo &  DCI 
) const
virtual

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Reimplemented from llvm::TargetLowering.

Definition at line 19097 of file X86ISelLowering.cpp.

References llvm::X86ISD::ADC, llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::X86ISD::BRCOND, llvm::X86ISD::BT, llvm::X86ISD::CMOV, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::X86ISD::FAND, llvm::X86ISD::FANDN, llvm::ISD::FMA, llvm::X86ISD::FMAX, llvm::X86ISD::FMIN, llvm::X86ISD::FOR, llvm::ISD::FSUB, llvm::X86ISD::FXOR, llvm::SDNode::getOpcode(), llvm::ISD::LOAD, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSS, llvm::ISD::MUL, llvm::ISD::OR, llvm::X86ISD::PALIGNR, PerformADCCombine(), PerformAddCombine(), PerformAndCombine(), PerformBrCondCombine(), PerformBTCombine(), PerformCMOVCombine(), PerformEXTRACT_VECTOR_ELTCombine(), PerformFADDCombine(), PerformFANDCombine(), PerformFANDNCombine(), PerformFMACombine(), PerformFMinFMaxCombine(), PerformFORCombine(), PerformFSUBCombine(), PerformISDSETCCCombine(), PerformLOADCombine(), PerformMulCombine(), PerformOrCombine(), PerformSELECTCombine(), PerformSETCCCombine(), PerformSExtCombine(), PerformShiftCombine(), PerformShuffleCombine(), PerformSIGN_EXTEND_INREGCombine(), PerformSINT_TO_FPCombine(), PerformSTORECombine(), PerformSubCombine(), PerformTruncateCombine(), PerformVZEXT_MOVLCombine(), performVZEXTCombine(), PerformXorCombine(), PerformZExtCombine(), llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::ISD::SELECT, llvm::X86ISD::SETCC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::X86ISD::SHUFP, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::ISD::VECTOR_SHUFFLE, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMILP, llvm::ISD::VSELECT, llvm::X86ISD::VZEXT, llvm::X86ISD::VZEXT_MOVL, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

void X86TargetLowering::ReplaceNodeResults ( SDNode *  N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG &  DAG 
) const
virtual

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.

ReplaceNodeResults - Replace a node with an illegal result type with a new node built out of custom code.

Reimplemented from llvm::TargetLowering.

Definition at line 13507 of file X86ISelLowering.cpp.

References llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::array_lengthof(), llvm::X86ISD::ATOMADD64_DAG, llvm::X86ISD::ATOMAND64_DAG, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::X86ISD::ATOMMAX64_DAG, llvm::X86ISD::ATOMMIN64_DAG, llvm::X86ISD::ATOMNAND64_DAG, llvm::X86ISD::ATOMOR64_DAG, llvm::X86ISD::ATOMSUB64_DAG, llvm::X86ISD::ATOMSWAP64_DAG, llvm::X86ISD::ATOMUMAX64_DAG, llvm::X86ISD::ATOMUMIN64_DAG, llvm::X86ISD::ATOMXOR64_DAG, llvm::ISD::BITCAST, llvm::BitsToDouble(), llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::N86::EAX, llvm::N86::EBX, llvm::N86::ECX, llvm::N86::EDX, llvm::ISD::EXTRACT_ELEMENT, llvm::MVT::f64, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FSUB, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::X86Subtarget::hasSSE2(), llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, isIntegerTypeFTOL(), llvm::TargetLoweringBase::isTypeLegal(), llvm::X86ISD::LCMPXCHG16_DAG, llvm::X86ISD::LCMPXCHG8_DAG, llvm_unreachable, N, llvm::ISD::OR, llvm::APIntOps::Or(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::X86ISD::RDTSC_DAG, llvm::ISD::READCYCLECOUNTER, ReplaceATOMIC_BINARY_64(), ReplaceATOMIC_LOAD(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::UINT_TO_FP, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::X86ISD::VFPROUND, and llvm::ISD::ZERO_EXTEND.

void X86TargetLowering::resetOperationActions ( )
virtual

Reset the operation actions based on target options.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 208 of file X86ISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLoweringBase::addBypassSlowDiv(), llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), llvm::ISD::ADJUST_TRAMPOLINE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::lltok::APFloat, llvm::array_lengthof(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::ATOMIC_SWAP, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::APFloat::changeSign(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantPool, llvm::APFloat::convert(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::TargetLoweringBase::Custom, llvm::ISD::DEBUGTRAP, llvm::CodeGenOpt::Default, llvm::ISD::DYNAMIC_STACKALLOC, llvm::N86::EAX, llvm::N86::EDX, llvm::ISD::EH_LABEL, llvm::ISD::EH_RETURN, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, llvm::TargetOptions::EnableSegmentedStacks, llvm::TargetLoweringBase::Expand, llvm::ISD::ExternalSymbol, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FGETSIGN, llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_ROUND_INREG, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FPOW, llvm::ISD::FPOWI, llvm::RTLIB::FPTOUINT_F32_I32, llvm::RTLIB::FPTOUINT_F32_I64, llvm::RTLIB::FPTOUINT_F64_I32, llvm::RTLIB::FPTOUINT_F64_I64, llvm::ISD::FRAME_TO_ARGS_OFFSET, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FSIN, llvm::ISD::FSINCOS, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::TargetMachine::getOptLevel(), llvm::TargetMachine::getRegisterInfo(), llvm::MVT::getSizeInBits(), llvm::X86RegisterInfo::getStackRegister(), llvm::TargetLoweringBase::getTargetMachine(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::APFloat::getZero(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasBMI(), llvm::X86Subtarget::hasCmpxchg16b(), llvm::X86Subtarget::hasFMA(), llvm::X86Subtarget::hasFMA4(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasLZCNT(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasPOPCNT(), llvm::X86Subtarget::hasSinCos(), llvm::X86Subtarget::hasSlowDivide(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE3(), llvm::X86Subtarget::hasSSE41(), llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::Sched::ILP, llvm::ISD::INIT_TRAMPOLINE, llvm::TargetLoweringBase::initActions(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isAtom(), llvm::X86Subtarget::isOSWindows(), llvm::isPowerOf2_32(), llvm::X86Subtarget::isTargetCygMing(), llvm::X86Subtarget::isTargetDarwin(), llvm::X86Subtarget::isTargetELF(), llvm::X86Subtarget::isTargetEnvMacho(), isTargetFTOL(), llvm::X86Subtarget::isTargetMingw(), llvm::X86Subtarget::isTargetWin64(), llvm::X86Subtarget::isTargetWindows(), llvm::ISD::JumpTable, llvm::MVT::LAST_VECTOR_VALUETYPE, llvm::TargetLoweringBase::Legal, llvm::ISD::LOAD, llvm::TargetLoweringBase::MaxStoresPerMemcpy, llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize, llvm::TargetLoweringBase::MaxStoresPerMemmove, llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize, llvm::TargetLoweringBase::MaxStoresPerMemset, llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize, llvm::ISD::MUL, llvm::RTLIB::MUL_I64, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLoweringBase::PredictableSelectIsExpensive, llvm::ISD::PREFETCH, llvm::TargetLoweringBase::Promote, llvm::ISD::READCYCLECOUNTER, llvm::Sched::RegPressure, llvm::APFloat::rmNearestTiesToEven, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::RTLIB::SDIV_I64, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::TargetLoweringBase::setBooleanContents(), llvm::TargetLoweringBase::setBooleanVectorContents(), llvm::ISD::SETCC, llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setExceptionPointerRegister(), llvm::TargetLoweringBase::setExceptionSelectorRegister(), llvm::TargetLoweringBase::setLibcallCallingConv(), llvm::TargetLoweringBase::setLibcallName(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::ISD::SETOEQ, llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setPrefFunctionAlignment(), llvm::TargetLoweringBase::setPrefLoopAlignment(), llvm::TargetLoweringBase::setSchedulingPreference(), llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore(), llvm::TargetLoweringBase::setTargetDAGCombine(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::ISD::SETUNE, llvm::TargetLoweringBase::setUseUnderscoreLongJmp(), llvm::TargetLoweringBase::setUseUnderscoreSetJmp(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::RTLIB::SHL_I128, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::RTLIB::SINCOS_F32, llvm::RTLIB::SINCOS_F64, llvm::ISD::SINT_TO_FP, llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::RTLIB::SRA_I128, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::RTLIB::SREM_I64, llvm::ISD::SRL, llvm::RTLIB::SRL_I128, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::TRAP, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::RTLIB::UDIV_I64, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UMUL_LOHI, llvm::ISD::UMULO, llvm::ISD::UNDEF, llvm::TargetOptions::UnsafeFPMath, llvm::ISD::UREM, llvm::RTLIB::UREM_I64, llvm::TargetOptions::UseSoftFloat, llvm::ISD::USUBO, llvm::MVT::v16f32, llvm::MVT::v16i1, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v4i8, llvm::MVT::v8f32, llvm::MVT::v8f64, llvm::MVT::v8i1, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i64, llvm::MVT::v8i8, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::CallingConv::X86_StdCall, llvm::MVT::x86mmx, llvm::APFloat::x87DoubleExtended, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, and llvm::ISD::ZEXTLOAD.

Referenced by X86TargetLowering().

virtual bool llvm::X86TargetLowering::ShouldShrinkFPConstant ( EVT  VT) const
inlinevirtual

ShouldShrinkFPConstant - If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 734 of file X86ISelLowering.h.

References llvm::MVT::f80.

The documentation for this class was generated from the following files:

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